JPH02290029A - Manufacture of thin film transistor matrix - Google Patents

Abstract

PURPOSE:To obtain a low resistance gate bus line by a method wherein, after Ti and Al are laminated on an insulative substrate, a resist mask is formed, a gate electrode and a wide bus line are formed, and the resist is subjected to isotropic etching, Al is etched and the resist is eliminated. CONSTITUTION:A film 2 of Ti and a film 3 of Al are stacked on a glass substrate 1; a resist mask 4 is formed; Al is etched by H3PO4; Ti is subjected to dry etching; thus a gate electrode G and a bus line GB are formed. The resist 4 of the electrode G is eliminated by O2 ashing, and the resist 4 whose width is reduced is left on the electrode G. By using the residual resist as a mask, Al 3 is isotropically etched, Al 3 on the electrode G is completely eliminated, and, on the bus line GB, Al 3 just under the resist 4 is left. By eliminating the resist, a low resistive gate bus line having two-layer structure of Al and Ti is obtained. By this constitution, manufacturing process of TFT matrix is simplified, and the yield is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing thin film transistor matrix, particularly a method of forming a low resistance gate bus line, which enables formation of a low resistance gate bus line with high precision in a simple process. With the aim of Aluminum film and Ti
removing the exposed portion of the film to form a gate electrode pattern and a gate bus line pattern having a width wider than the gate electrode; and isotropically etching the resist film on each of the patterns. , removing all the resist film on the gate electrode pattern and reducing the width of the resist film on the gate lotus line pattern, and exposing the aluminum film using the resist film remaining on the gate lotus line pattern as a mask. The structure includes a step of removing the part.

[Industrial application field]

The present invention relates to a method of manufacturing a thin film transistor I/Rix, and more particularly to a method of forming a low-resistance cell line.

In recent years, thin film transistors (TFTs) 71 are required to have larger display screens and improved image quality. Along with this increase in size and higher image quality, the degree of integration of elements has increased, and in order to meet these demands, it is required to lower the resistance of the G1 Hassline.

[Conventional technology]

A conventional method for forming a low resistance gate substrate of a thin film transistor matrix is shown in FIGS. 2(a) to 2(g). In addition, the same figure (
f) and (g) are plan views of essential parts, and cross-sections taken along line B-B are shown in sectional views of essential parts (a) to (e).

As shown in Figures (a) and (f), after forming a Ti film 2 on a glass substrate 1'2, unnecessary parts are removed according to a predetermined pattern, and gate electrode G and gate 1/bus line CB are removed. Form a lower layer film.

Next, as shown in FIG. 2(b), Af! of the Ti film 2 is applied. ．． A film 3 is formed.

Next, as shown in (c) and (g), the above AI! ．． membrane 3
A resist 1 and a film 4 are formed thereon. This resist 1/film 4
is formed only on the gate lotus line GB, and its dimensions are:
It is formed to be smaller than the width of the Ti film 2 in the gate 1/lotus line CB portion.

Next, as shown in (d), the lf2 film 3 is etched using the resist 1 and film 4 as a mask to remove the exposed portion.

After that, the resist 1 and the film 4 are removed, and as shown in (e), the Affi film 3 is removed and the gate 1 and the electrode G are formed only of the Ti film 2, and the Ti film 2 and the Affi film 3 are separated. A two-layered Ge1-Has line CB is obtained.

The conventional manufacturing method described above requires forming the resist film twice. Therefore, the manufacturing process is complicated, and problems arise in terms of alignment accuracy.

[Problems to be Solved by the Invention] As described above, in the conventional manufacturing method, the process of forming a low resistance bus line becomes complicated, the reliability and manufacturing yield of the thin film transistor matrix decrease, and the manufacturing cost increases.

SUMMARY OF THE INVENTION An object of the present invention is to enable formation of low-resistance gate bus lines with high accuracy through simple steps.

[Means to solve the problem]

The present invention provides a valve metal film, for example, Tt, on an insulating substrate.
The film and the Aj2 film are laminated in this order, and a resist l- film for forming a gate electrode and a gate bus line is formed thereon.

Next, first, use this resist film as a mask to perform the above step A! The exposed portions of the film and the T1 film are removed, and a pattern of a gate lotus line with a width wider than the gate electrode and the gate lotus line is formed.

Next, an isotropic etching method is applied to the resist film on each pattern described above to such an extent that the resist film on the gate electrode is completely removed. As a result, the width of the resist 1 film on the gate bus line is slightly reduced, and the edge portion of the Aff film is exposed.

Next, the A/2 film is etched using the resist film remaining on the gate bus line pattern as a mask,
Finally, the resist film is removed.

With this, AI! ．． After the exposed part of the film is removed, only the Ti film remains in the gate electrode part, and in the gate pass line part, the Ti film is the lower layer and the AI film is slightly narrower than the Ti film! ．．
A two-layer structure is formed with the membrane as the upper layer.

[Function] In the present invention, a Ti film as a gate electrode layer and a low resistance A
After laminating the I film and forming a resist film thereon, a gate electrode layer is formed. The A2 film of the low resistance layer is etched, and then the resist pattern is isotropically dry etched, but at this time, the pattern width of the gate electrode is smaller than the pattern width of the gate lotus line. The isotropic dry etching eliminates the resist film on the gate electrode, but the resist film remains on the gate bus line H.

After that, if the low resistance layer is etched, the low resistance layer will be completely removed because there is no resist 1 film on the gate electrode, but the resist 1 film will remain on the gate lot line. , the low resistance layer remains unetched. In this way, f resistor gate bus lines can be easily formed by applying isotropic drag-ending.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.
a)-(e) l. t(f), (g) is a main part sectional view showing a cross section taken along the line A-Δ arrow.

First, see figure (a). As shown in (f), the glass substrate 1
- Thickness of approximately 40 nm by sputtering method
1゛i film 2, and on top of it is a film A with a thickness of about 50 nm! A film 3 is formed. Next, a resist film 4 for forming a gate electrode and a gate bus line is formed.

As shown in FIG. 3(b), using the resist film 4 as a mask, the Δρ film 3 and Ti
Film 2 is sequentially etched. For this etching, the AF film can be etched by a wet etching method using phosphoric acid (H, PO4), and the Ti film can be etched by a dry etching method.

As a result, the Ti film 2 and AP. A pattern of the gate 1 electrode G and a pattern of the gate 1 bus line GB, which are made of a laminated film with the film 3, are formed.

Next, as shown in FIG. 2C, the resist l/film used as the mask is etched by an oxygen (02) anosing method. The enching in this process is
This is done to the extent that the upper resist film 4 is removed.

After the above oxygen ashing process, Section 111(d). (g
), the resist 1/film disappears from the gate electrode G portion, but the resist film 4 with a slightly reduced width remains on the gate lot line CB.

Next, using the remaining resist 1 and film 4 as a mask,
Isotropic enoching is performed on the Δf film 3.

Through this step, as shown in FIG. 2(e), the AJ2 film 3 is exposed on the gate electrode G, so the A1 film 3 is completely removed, but the width is reduced on the gate bus line CB. Since there is a resist film 4 that is flu
3, the exposed portions on both sides of the resist 1 and film 4 are removed, and the portion immediately below the resist film 4 remains substantially.

Next, the resist l/film is removed to form a low resistance gate 1 -/low-resistance line with a two-layer structure of an Aβ film and an 'F film, and a 'i'
A single layer gate electrode is obtained.

In the above example, the gate bus line with the two-layer structure of the Aρ film and the Ti film can be formed with one resist film, which simplifies the manufacturing process.
By not forming the resists 1 to 5 twice, there is no occurrence of any misalignment. Therefore, reliability and manufacturing yield are improved.

In the above embodiment, an example was explained in which the lower valve metal film of the gate bus line CB was made of 'l i 19, but instead of this, another valve metal film may be used. That is, Ta Zr
Nb etc. can be used.

[Effects of the Invention] As explained above, according to the present invention, the manufacturing process of the thin film 1-transistor polymer is simplified, and the reliability and manufacturing yield are improved.

[Brief explanation of the drawing]

11F(a) to (g) are explanatory diagrams of one embodiment of the present invention, 2nd
11119(a) to (■■■ are diagrams showing a low resistance gate bus line formation method since IJC. In the diagram, 1 is an insulating substrate (glass substrate), 2 is a valve metal film (Ti film), 3 is a 8p film, 4 resist film, G gate electrode, and CB gate bus line.

Claims (1)

[Claims] A valve metal film (2) selected from valve metals other than aluminum and an aluminum film (3) are laminated in this order on an insulating substrate, and then the aluminum film (3) is laminated in this order. Using the resist film (4) formed above as a mask, the exposed parts of the aluminum film and Ti film are removed to form a gate electrode (G) pattern and a gate bus line (GB) pattern wider than the gate electrode. and performing isotropic etching on the resist film (4) on each of the patterns to remove all the resist film on the gate electrode G pattern, and remove the resist film on the gate bus line GB pattern. a step of reducing the width of the resist film (4) remaining on the gate bus line pattern;
) of the aluminum film (3) as a mask to remove the exposed portion of the aluminum film (3).