JPH0228933B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to cell call buoys, inter-ship cell calls, etc., and particularly relates to improvements in these selective call detection circuits. What is Selcall Buoy?
It is a radio buoy that sends back a response signal when it receives a predetermined unique call signal.
The selective call detection circuit is a circuit that examines the call signal and finds the signal that calls the buoy.

[Conventional technology]

For gillnets, longlines, etc., sercole buoys are attached to fishing gear. This is to confirm the location of the fishing gear based on the response signal issued by the cell call buoy in response to the call signal. The time width and frequency of the calling signal are determined by the Radio Law, and as shown in Figure 5a, one segment is 200 ms, and there is a time interval between each segment.
A 10ms no-signal time is provided. The frequency is
It is defined as a range from 502.5HZ to 802.5HZ, and if the calling signal is composed of four sections, each section has a predetermined frequency f ₁ , f ₂ , f ₃ , f ₄ in the frequency range. assigned to each.
The cell call buoy uses a selective call detection circuit to check the frequencies f ₁ to _{f 4} of the call signal to confirm whether it is a signal to call the buoy or not, and if it is a signal to call the buoy, it issues a response signal.

Conventional selective call detection circuits are shown in FIGS. 1 and 2.
It was as shown in the figure. FIG. 1 shows a block diagram. In the figure, the first section of the input call signal is sent to the analog switch S1.
0 and is added to a tuning fork filter FL10 that allows only the frequency of _f1 to pass. If the frequency of this signal is _f1 , the signal passes through the tuning fork filter FL10 and is applied to the signal presence/absence determination circuit DS10, thereby turning on the analog switch S2 at the next stage. For this purpose, the second section of the ringing signal is applied to tuning fork filter FL20. The frequency of this signal is f ₂
If so, the analog switch S30 at the next stage becomes conductive in the same manner as above. Thereafter, the same operation is repeated, and the frequencies of the first to fourth divisions of the calling signal are applied to the tuning fork filters FL10, FL20,
If it matches the passing frequency of FL30 and FL40, a detection output is output.

FIG. 2 is a circuit diagram showing in particular detail the signal presence/absence determining circuit portion of the block diagram of FIG. 1. The first section of the calling signal that has passed through the tuning fork filter FL10 is amplified by the transistor Q10, and is then amplified by the capacitors C10 and C12 and the diode D.
It is rectified by 10 and D11, and divided by resistors R14 and R15. When the divided voltage applied to resistor R15 exceeds a certain level, transistor Q11 becomes conductive.
The output of transistor Q11 through inverting amplifier A10 makes the next stage analog switch S20 conductive during the second segment of the ringing signal. This timing and time are determined by the values of hfe of the capacitor C12, resistors R14 and R15, and transistor Q11.

[Problem that the invention seeks to solve]

The problems with the conventional selective call detection circuit described above are as follows.

(a) Since there are variations in hfe of the transistor Q11, it is adjusted with resistors R14 and R15 in order to keep the conduction holding time of the next-stage analog switch as designed. However, at this time, the resistors R14, R
As a result of the change in the partial pressure ratio of 15, the timing of switching to the conductive state also changes at the same time, making adjustment difficult. Furthermore, the base of transistor Q11
Since the voltage between the emitters and hfe change depending on the temperature, it is necessary to take these fluctuations into account when making adjustments.

(b) Since the response time of a tuning fork filter differs depending on the frequency, the timing at which the next stage analog switch is turned on must be adjusted for each stage according to the frequency, which is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a selective call detection circuit which solves the above problems and also has a simplified and highly reliable circuit.

[Means for solving problems]

The following measures were taken to solve the above problems and achieve the objectives.

(b) A part that determines the time to make the next stage analog switch conductive in the signal presence/absence determination circuit;
Separate the parts that determine the timing so that they do not affect each other.

(b) Aim to unify the signal presence/absence determination circuit using a counter and a signal switch.

〔Example〕

Next, an embodiment of the present invention shown in the drawings will be described. FIG. 3 is a block diagram of a selective call detection circuit according to an embodiment of the present invention.
The output from each tuning fork filter is a signal switching IC
1 is switched sequentially to determine the presence or absence of a signal.
Added to DS1. A counter IC2 controls the signal switch IC1. The counter IC2 is reset and does not output a detection output unless there is an output from the signal presence/absence determining circuit DS1. First call signal
The frequencies in the fourth to fourth divisions are filtered through the tuning fork filter.
When the frequency matches the passing frequency of FL10, FL20, FL30, and FL40, the counter IC2 outputs a detection output.

FIG. 4 is a circuit diagram showing in detail the block diagram of FIG. 3. The operation of the circuit shown in the figure will be explained with reference to the time chart shown in FIG. The ringing signal (FIG. 5a) applied to the input of FIG. 4 passes through the tuning fork filter FL50 and has the waveform shown in FIG. 5b. Then, it is amplified by transistor Q1, and diode D1, D
2. It is rectified by capacitor C2 (Fig. 5c).
When this rectified voltage exceeds the level set by resistors R5 and R6, transistor Q2 becomes conductive and a collector output having the waveform shown in FIG. 5d is obtained. This collector output is delayed by the delay circuit X2 as shown in FIG.
It is input to the clock terminal CL of No.2. Delay circuit
The delay time of 2 is predetermined to ensure that the delayed collector output shown in Figure 5e is input to the clock terminal CL after counter IC2 has been reliably reset by the undelayed collector output shown in Figure 5d. It is set to a predetermined value. In response to the input signal to the clock terminal CL, the counter IC2 changes the count outputs P1, P2, P3 from 0, 0, 0 to 1, 0, 0 and supplies them to the signal switch IC1. The output of is applied to the signal presence/absence determination circuit. Repeat the above operation until the count outputs P1, P of counter IC2
2, P3 is counted up to the state of 0, 0, 1, a detection output A is output (Fig. 5g, h, i).

On the other hand, the output of transistor Q2 shown in FIG. 5d is applied to delay circuit X2 and also to timer circuit X1. As shown in Figure 4, the timer circuit _X1 consists of a resistor R8 and a capacitor C4.
, and a diode D3 connected between their connection point J and the collector of the transistor Q2. As shown in FIG. 5d, when transistor Q2 becomes conductive, capacitor C
4 is discharged through the diode D3, and the potential at the connection point J decreases. After the capacitor C4 is discharged, it is charged again via the resistor R8, and the potential at the connection point J connected to the reset terminal RST of the counter IC2 gradually increases. When the potential exceeds the threshold value shown in FIG. 5f, the counter IC2 is reset. In addition, timer circuit
1 can also be configured with a trigger type monostable multivibrator as shown in FIG. The output of the transistor Q2, which has passed through the timer circuit X1, has the waveform shown in FIG.
is applied to the reset terminal RST. This timer circuit X1 is provided to prevent the count of the counter IC2 from being reset until the next division of the calling signal is output from the tuning fork filter. This is provided in order to reset the count and not output a detection output when no output is generated. Counter by timer circuit X1
The time T to prevent IC2 from being reset is calculated as T=(length of each segment of the ringing signal)+(difference in response time due to tuning fork filter frequency). Currently, the frequency of the cell call signal used is 502.5Hz to 802.5Hz, and the frequency of the cell call signal used is 502.5Hz to 802.5Hz.
The response time difference between 502.5Hz and 802.5Hz is approximately 50mSec. Therefore, the above T may be approximately 250 mSec.

The case where the call signal is divided into four types has been described above, but even if the signal type changes, it can be easily handled by changing the count number of the counter IC2.

For example, if the call signal repeats four sections twice, the detection output B of the counter IC2 may be used.

Next, FIG. 6 shows an embodiment in which the calling signal consists of five sections. Detection output A is output from output P1 and output P3 of counter IC2 so that it is output when the count number of counter IC2 reaches 5.
is extracted through an AND circuit. Detection output B is provided for the case where the call signal repeats five sections twice.

〔Effect of the invention〕

This invention has the following effects.

(b) When sequentially checking the frequencies of the first to fourth divisions of the calling signal, the timing at which the signal switch is switched in order to check the next division is determined by the delay circuit X ₂ , and the hold time after switching is Since it is determined by timer circuit X ₁ , they can be adjusted independently of each other, making adjustment easy.

(b) Even if the number of call signal divisions changes, it can be easily handled by changing the count number of the counter and increasing or decreasing the number of tuning fork filters.

(c) Only one signal presence/absence determination circuit is required, which simplifies the circuit and enables signal detection at the same level regardless of frequency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional selective call detection circuit, FIG. 2 is a circuit diagram of the block diagram of FIG. 1, FIG. 3 is a block diagram of a selective call detection circuit according to the present invention, and FIG.
The figure is a circuit diagram of the block diagram in Fig. 3, Fig. 5 a, b, c, d, e, f, g,
h and i are time charts of signals flowing through the circuit in FIG. 4, and FIG. 6 is a circuit diagram according to another embodiment.
FIG. 7 is a circuit diagram of the timer circuit. Note that the same reference numerals in the figures indicate the same parts. S10, S20, S30, S40...analog switch, FL10, FL20, FL30, FL40...
Tuning fork filter, FL50, FL60, FL70,
FL80, FL90...Tuning fork filter, DS10,
DS20, DS30, DS40...Signal presence/absence determination circuit,
IC1...signal switch, IC2...counter.

Claims (1)

[Claims] 1. Receive a series of signals in which a plurality of signals of different frequencies are transmitted in a predetermined order, and pass only signals corresponding to each frequency of the plurality of signals and each having a predetermined frequency. In a detection circuit that selects a received signal using a plurality of filters and detects a combination of signals in a specific order, a signal switcher that switches and selects one of the plurality of filters; A signal presence/absence discrimination circuit that outputs a pulse signal having a predetermined duration based on an input of an output signal, a delay circuit that delays the output pulse signal of the signal presence/absence discrimination circuit for a predetermined time, and a signal presence/absence discrimination circuit delayed by the delay circuit. a counter that switches the signal switch in a specific order each time an output pulse signal is input and counts the number of output pulse signals to confirm the arrival of a predetermined number of output pulse signals; and an output of a signal presence/absence determination circuit. A reset device that is driven by a pulse signal and resets the counter after a predetermined time determined based on the sum of the time length of each section of the calling signal and the frequency-dependent deviation of the response time of the tuning fork filter from the input of the output pulse signal. A selective call detection circuit having a timer circuit that outputs a signal.