JPS6080327A - Selective call detecting circuit - Google Patents

Abstract

PURPOSE:To attain ease of circuit adjustment by providing independently a part making a signal selection switch of the next stage of a detection circuit conductive and a part deciding the timing respectively. CONSTITUTION:A serial signal comprising plural frequencies is applied to a signal presence discriminating circuit DS1 via tuning fork filters FL50-FL80 and a signal switch IC1. The switch IC1 selects at first the filter FL50. After a delay circuit X2 delayes an output of the discrimination circuit DS1 for a prescribed time, the X2 counts up to switch the switch IC1 to the filter FL60 of the next stage. When all serial signals are discriminated after the operation above is repeated, a detection output A is given from a counter. On the oher hand, a charge/discharge circuit X1 resets a counter IC2 when a signal of the next section is not inputted within a prescribed time. Since the switching timing of the switch IC1 and the holding time after switching are adjusted independently, the circuit is adjusted easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to cell call buoys, inter-ship cell calls, etc., and particularly relates to improvements in these selective call detection circuits. A cell call buoy is a radio buoy that sends back a response signal when it receives a predetermined unique call signal.

The selective call detection circuit is a circuit that examines the call signal and finds the signal that calls the buoy.

[Conventional technology]

For gillnets, longlines, etc., sercole buoys are attached to fishing gear. This is to confirm the location of the fishing gear based on the response signal issued by the cell call buoy in response to the call signal. As shown in Fig. 5(a), the call signal currently in use consists of four sections with each section being 200 ms, and each section has a predetermined frequency f between 502.5H2 and 802.51 (Z).
, , f2. f3. It has f. The cell call buoy uses a selective call detection circuit to check the frequencies f1 to f4 of the call signal to confirm whether or not it is a signal to call the buoy, and if it is a signal to call the buoy, outputs a response signal.

Conventional selective call detection circuits are as shown in FIGS. 1 and 2. FIG. 1 shows a block diagram. In the figure, the first section of the input ringing signal is applied through an analog switch SIO to a tuning fork filter FL10 that passes only frequencies fl. If the frequency of this signal is fl, the signal passes through the tuning fork filter FLtO, is applied to the signal presence/absence determination circuit DSIO, and turns on the analog switch S20 at the next stage. Therefore, the second section of the ringing signal is processed by the tuning fork filter FL.
Added to 20. If the frequency of this signal is f2, the next-stage analog switch S30 becomes conductive in the same manner as described above. Thereafter, the same operation is repeated, and the frequencies of the first to fourth divisions of the calling signal are applied to the tuning fork filter FL.
If it matches the passing frequency of IO, FL2Q, FL80, FL40, a detection output is output.

FIG. 2 is a circuit diagram showing in particular detail the signal presence/absence determining circuit portion of the block diagram of FIG. 1. The first section of the calling signal that has passed through the tuning fork filter FL1o is amplified by a transistor QIO and then connected to a capacitor C1o,
It is rectified by CI2, diodes DIO, and Dtl, and divided by resistors R14 and R15. When the divided voltage applied to resistor R15 exceeds a certain level, transistor Q11 becomes conductive. The output of the t-transistor Q1t through the inverting amplifier AIO makes the next stage analog switch S2,0 conductive during the second segment of the ringing signal. This timing and time are determined by the values of hfe of the capacitor C12, resistors R14 and R15, and transistor Q11.

[Problem that the invention seeks to solve]

The problems with the conventional selective call detection circuit described above are as follows.

(a) Since there are variations in hfe of transistor Qll, it is adjusted with resistors R1j and R15 in order to keep the conduction holding time of the next stage analog switch as designed. However, as a result of the change in the voltage division ratio of the resistors R14 and R15, the timing of switching to the conductive state also changes at the same time, making adjustment difficult. Furthermore, since the voltage between the base and emitter of the transistor Qll and hfe change depending on the temperature, it is necessary to take these fluctuations into account when making adjustments.

(b) Since the response time of a tuning fork filter differs depending on the frequency, the timing for turning on the analog switch in the next stage must be adjusted for each stage according to the frequency, which is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a selective call detection circuit which solves the above problems and also has a simplified circuit and high reliability.

[Means for solving problems]

The following measures were taken to solve the above problems and achieve the objectives.

(a) In the signal presence/absence determination circuit, the part that determines the time to turn on the next-stage analog switch and the part that determines the timing are separated so that they do not affect each other.

(2)) Use a counter and a signal switch to unify the signal presence/absence determination circuit.

〔Example〕

Next, a practical example of the present invention shown in the drawings will be explained. FIG. 3 is a block diagram of a selective call detection circuit according to an embodiment of the present invention.

The output from each tuning fork filter is sequentially switched by a signal switch ICI and applied to a signal presence/absence determination circuit DSI. Signal switch ■ Counter IC controls C1
It is 2. The counter IC2 is reset and does not output a detection output unless there is an output from the signal presence/absence determination circuit DSI.

The frequencies of the first to fourth divisions of the calling signal are filtered by the tuning fork filter FLIO.

When the frequency matches the passing frequency of FL20, FL80, and FL40, the counter IC2 outputs a detection output.

FIG. 4 is a circuit diagram showing in detail a portion of the block diagram in FIG. 3. The operation of the circuit shown in the figure will be explained with reference to time chart 1 shown in FIG. The call signal applied to the human power in Figure 4 (Figure 5(a)) is
The waveform passes through the tuning fork filter FL50 and becomes the waveform shown in FIG. 5(b). The transistor Q1 then amplifies the diode DI, D2 . It is rectified by capacitor C2 (fifth
Figure (C)). When this rectified voltage exceeds the level set by resistors R5 and R6, transistor Q2 becomes conductive (FIG. 5(d)).

The output of the transistor Q2 is delayed by the delay circuit X2 and input to the clock terminal CL of the counter IC2 (FIG. 5(e)). Therefore, the counter IC2 outputs the count outputs PI, Ps, Ps to 0.0. Ogara I, 0,
, 01 inch is applied to the signal switch IC1, so in the next step the output from the tuning fork filter FL60 is applied to the signal presence/absence determination circuit. Repeat the above operation with counter ■C
2 count output P1. Ps, P8 is o, o, 1 (7
), a detection output A is output (Fig. 5(g), (h), (su)).

On the other hand, the output of transistor Q2 shown in FIG. 5(d) is.

It is added to the delay circuit X2 and also to the charge/discharge circuit X1. Note that the charging/discharging circuit X1 can also be constructed of a monostable multivibrator with a lidrigger as shown in FIG. The output of the transistor Q2 that has passed through the charging/discharging circuit X1 becomes a waveform shown in FIG. 5ff) and is applied to the reset terminal R3T of the counter IC2. This charging/discharging circuit x1 is provided in order to reset the count and not output a detection output if the signal of the next division of the calling signal is not output from the tuning fork filter due to mismatch. The time T for preventing the counter IC2 from being reset by the charging/discharging circuit X1 is calculated as T + (length of each section of the calling signal) + (response time difference depending on the frequency of the tuning fork filter). The frequency of the cell call signal currently in use is 502.
5Hz ~ 802.5H2, tuning fork filter (7)
The response time difference between 502.5Hz and 802.5Hz is approximately 50
mSec. Therefore, the above T is approximately 250m5ec
And it is sufficient.

Above, we have explained the case where the call signal is divided into four types, but even if the signal type changes, the counter IC2
This can be easily handled by changing the number of counts.

For example, if the call signal repeats four sections twice, the detection output B of the counter IC2 may be used.

Next, FIG. 6 shows an embodiment in which the calling signal consists of five sections. The detection output A is output from the counter I so that it is output when the count number of the counter IC2 reaches 5.
Output P1 and output P3 of C2 are taken out through an AND circuit. Detection output B is provided for the case where the call signal repeats five sections twice.

〔Effect of the invention〕

This invention has the following effects.

(B) When sequentially checking the frequencies of the first to fourth divisions of the calling signal, the timing at which the signal switch is switched to check the next division is determined by the delay circuit X2, and the holding time after switching is determined by the charging/discharging circuit XI. Since they are determined by , they can be adjusted independently of each other, and adjustment is easy.

(b) Even if the number of call signal divisions changes, it can be easily handled by changing the count number of the counter and increasing or decreasing the number of tuning fork filters.

(The signal presence/absence determination circuit is a single circuit, which simplifies the circuit and enables signal detection at the same level regardless of frequency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional selective call detection circuit, FIG. 2 is a circuit diagram of the block diagram of FIG. 1, FIG. 8 is a block diagram of a selective call detection circuit according to the present invention, and FIG. 5 is a time chart of signals flowing through the circuit of FIG. 4, FIG. 6 is a circuit diagram of another embodiment, and FIG. 7 is a circuit diagram of FLIO, FL20, FL80, FL40.
=・Tuning fork filter, FL50°FL60, FIL7
0, FLgo, FL90 --- Tuning fork filter, DSlo. DS20, DS30, DS40・Signal presence/absence discrimination circuit, IC1・・Signal switch, IC2・・Counter agent Patent attorney Takashi Higashijima Jiu Yabe ω yaq Chokuya V -1ノ -,ノ ＼Yunoζ Yuno V-1I N,ノ □

Claims (1)

[Claims] (]) It has a filter that separates serial signals of a plurality of frequencies into predetermined frequencies, and examines the output from the filter and outputs a detection output only when the combination of frequencies of the serial signals is constant. a signal switcher that selects one of the plurality of output signals from the filter and applies it to the signal presence/absence discrimination circuit; a first delay circuit that delays the output of the signal presence/absence discrimination circuit; A second delay circuit that determines the presence or absence of a subsequent signal based on the output of the signal presence/absence determination circuit, and a control circuit that controls the signal switcher based on the outputs from the first and X second delay circuits. A selective call detection circuit characterized by: (2) The selective call detection circuit according to claim 1, wherein the control circuit is a counter.