JPH0286258A - Signal detection circuit - Google Patents

Abstract

PURPOSE:To detect only a signal within a range without misdetection by making the signal detection frequency range constant. CONSTITUTION:A slicer circuit 2 converts an input analog signal into a digital signal, the 1st counter circuit 3 decides the upper limit of a detected frequency, detects a frequency lower than the upper limit frequency and a monostable multivibrator circuit 4 decides the lower limit of the detected frequency and detects the frequency higher than the lower limit frequency. Then the 2nd counter circuit 5 generates an output only when the period of the output of the monostable multivibrator circuit 4 is longer than a prescribed period and acts like an on-guard timer. Thus, mis-detection of the signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic calling function of a data transmission device that utilizes a telephone exchange line, and particularly relates to an automatic calling function of a data transmission device that uses a telephone exchange line. The present invention relates to a signal detection circuit that detects a busy tone (busy tone, second dial tone).

[Conventional technology]

Conventionally, this type of signal detection circuit includes a communication transformer 9. as shown in FIG. Bandpass filter circuit 10° full wave rectifier circuit 11. Low-pass filter circuit 12. The level comparison circuit 13 and the timer circuit 14 are connected in series, and the communication transformer 9
The primary side of the timer circuit 14 was used as the input terminal 15 of the signal detection circuit, and the output of the timer circuit 14 was used as the output terminal 16 of the signal detection circuit.

[Problem to be solved by the invention]

The conventional signal detection circuit described above extracts the signal using a bandpass filter circuit. This bandpass filter circuit consists of a capacitor,
It consists of a resistor and an amplifier, and if you try to narrow the signal passband to prevent false signal detection, you must configure a high-order wave circuit. This method has the disadvantage that the signal transmission time delay becomes large, and signals with a large number of interruptions (short intervals) cannot be detected completely.

An object of the present invention is to provide a signal detection circuit that eliminates such drawbacks.

[Means to solve the problem]

The present invention is a signal detection circuit that detects various signals from a telephone exchange line, and includes a conversion circuit that converts an analog signal from the telephone exchange line into a digital signal, a conversion circuit that determines an upper limit of a detection frequency, and a signal detection circuit that detects various signals from a telephone exchange line. A cascade connection of a first detection circuit that detects a lower frequency, a second detection circuit that determines a lower limit of detection frequency and detects frequencies higher than this lower limit frequency, and a detection delay circuit for false detection protection. It is characterized by having a circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This signal detection circuit consists of communication transformer 1. Slicer circuit 2. First counter circuit 3. The monostable multi-bi break circuit 4 and the second counter circuit 5 are connected in cascade, the oscillation circuit 6 is connected to the first counter circuit 3 and the second counter circuit 5, and the primary side of the communication transformer 1 is connected to the input of the signal detection circuit. The terminal 7 is used as the output terminal 7, and the output of the second counter circuit 5 is used as the output terminal 8 of the imperial code detection circuit.

The signal detection circuit of this embodiment has a signal frequency range of (A±
α) (Hz), A + α = 1/Tl (Hz) A - α = 1/T2 (Hz: 1) to detect the frequency of the signal, and turn on T3 (S) by the detection delay circuit to protect against false detection.・This is a method with an added guard.

In FIG. 1, a communication transformer 1 is used to disconnect the direct current circuit of the telephone exchange line from the circuits after the slicer circuit 2 in terms of direct current.

The slicer circuit 2 converts an input analog signal into a digital signal.

The first counter circuit 3 has an upper limit of the detection frequency, that is, A+
α (Hz) is determined, and frequencies lower than this upper limit frequency are detected.

The monostable multi-bi break circuit 4 determines the lower limit of the detection frequency, that is, A-α (Hz), and detects frequencies higher than this lower limit frequency.

The second counter circuit 5 functions as an on-guard timer by generating an output only when the output of the monostable multivibrator circuit 4 is longer than a predetermined period T3 (S).

The oscillation circuit 6 is used as a clock source for the first counter circuit 3 and the second counter circuit 5.

Next, the operation of this embodiment will be explained. In addition, Figures 3 and 4
5 and 5 are signal waveform diagrams of each part of the circuit shown in FIG. 1, and in FIG. 3, the frequency is higher than A-α [H2] (,
And, Fig. 4 is a waveform diagram of each part when a signal with a frequency lower than A + α (Hz) is input, and Fig. 5 is a waveform diagram of each part when a signal with a frequency higher than A + α (Hz) is input. It is a waveform diagram of each part when a signal with a frequency lower than -α (Hz) is input.

First, the frequency is higher than A-α (Hz) (and A+α
The operation when a signal lower than (Hz) is input will be explained.

When the received input signal a of FIG. 3 is input to the input terminal 7 of FIG. 1, the communication transformer l outputs a signal S.

The slicer circuit 2 to which the signal S is input converts the signal S, which is an analog signal, into a signal C, which is a digital signal, and outputs the signal C.

The first counter circuit 3 to which the signal C is input has a high level of signal C.
Counting of the clock g of the oscillation circuit 6 is started from the time when the signal C is at the (high) level, and counting is continued while the signal C is at the H level.

When the time Tl (S) is counted up, while the signal C is at the H level, the signal d, which is the output of the first counter circuit 3, is fixed at the T level, and the The signal d is fixed at the L level when the signal d reaches the L level.

Therefore, the first counter circuit 3 outputs an H level only when an input signal with a period longer than Tl (S) is input. In other words, 1/Tl (H2) is the boundary
Only frequencies lower than Tl (Hz) can be detected.

The monostable multi-by-break circuit 4 to which the signal d has been input has T2 [S
], outputs L level. Here, the period of signal d is 7
If it is shorter than 2 (S), the signal e, which is the output of the monostable multi-bi break 4, outputs the level again for T2 (S) before changing to the H level. Therefore, the period of the signal d is 72 ( S) Signal e can be fixed at L level unless the signal d becomes longer or the signal d is fixed at L level.If the period of signal d is T2
(S), or when the signal d is fixed at the L level, the signal e becomes the H level. Therefore, the monostable multi-bi break circuit 4 has T2 (S)
T2 (S
) to output the level for a longer time. That is, 1/T2
(Hz), only frequencies higher than 1/T2 (Hz) can be expressed in such a way that the signal e is fixed at the L level.

The second counter circuit 5 to which the signal e is input is
Counting starts from the moment the signal e reaches L level.
Continue counting while reaching the level. Time T3
(S) is counted and amplified, the signal r, which is the output of the second counter circuit 5, is fixed at the H level, and the signal f is fixed at the L level when the signal e becomes the H level. Therefore, the second counter circuit 5 calculates that the signal e is T
Only when the L level is longer than 3(S), the H level is output. That is, the second counter circuit 5 is used as an on-guard timer of the signal detection circuit.

FIG. 4 is a waveform diagram of each part when a signal having a frequency higher than A+α (Hz) is input.

The signals a, b, and c are the same as those explained in FIG. 3, but the period of the input signal C of the first counter circuit 3 is TI=1/
Since it is shorter than A+α(S), the first counter circuit 3 cannot count up, and the signal d is fixed at L level.

As a result, the monostable multivibrator circuit 4 and the second counter circuit 5 do not operate, the output terminal 8 of the signal detection circuit is fixed at L level, and no signal is detected.

FIG. 5 is a waveform diagram of each part when a signal having a frequency lower than A-αl''Hz) is input.

Signals a, b, c, and d are the same as those explained in FIG. The output signal e of the stable multivibrator circuit 4 cannot be fixed at level 12. The monostable multi-bi break circuit 4 outputs the L level for T2 (S) from the timing when the signal d changes to the H level, and outputs the H level after T2 (S) until the signal d changes to the H level. As a result, the second counter circuit 5 cannot count up since the time that the input signal e is at the L level is T2 (S), and the output terminal 8 of the signal detection circuit is at the L level. Fixed, no signal detected.

One embodiment of the present invention has been described above, but since the first counter circuit, monostable multi-by-break circuit, second counter circuit, and oscillation circuit constituting this signal detection circuit are composed of digital circuits, integrated circuits can be realized.

〔Effect of the invention〕

As explained above, the present invention can keep the signal detection frequency range constant, and detect only signals within the range without falsely detecting signals outside the range regardless of the input level. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The block diagrams of conventional signal detection circuits, FIGS. 3 to 5, are as follows:
2 is a waveform diagram of each part for explaining the operation of the embodiment of FIG. 1. FIG. 1...Communication transformer 2...Slave circuit 3...First counter circuit 4...Monostable multi-vibration circuit 5...
-Second counter circuit 6...Oscillation circuit 7...Signal detection circuit/Input terminal 8...Signal detection circuit/Output terminal 9...Communication transformer 10... ...Band filter circuit 11...Full-wave rectifier circuit 12, 13, 14, 15, 16, low-pass filter circuit, level comparison circuit, timer circuit, signal detection circuit, input terminal, signal detection circuit, output terminal

Claims (1)

[Claims] (1) A signal detection circuit that detects various signals from the telephone exchange line, including a conversion circuit that converts analog signals from the telephone exchange line into digital signals, and a signal detection circuit that determines the upper limit of the detection frequency and that is lower than this upper limit frequency. A cascade connection circuit includes a first detection circuit that detects a frequency, a second detection circuit that determines a lower limit of the detection frequency and detects a frequency higher than this lower limit frequency, and a detection delay circuit for protecting against false detection. A signal detection circuit comprising: