JPS5912844Y2 - FS signal demodulator - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a demodulator for the FS communication system, which is often used in data transmission.

The FS communication method uses two different frequency carrier waves to represent the digital signals "1" and "0", and transmits these carrier waves alternately, using a type of frequency modulation. It is a communication method.

The transmission signal of the FS communication is a frequency shift signal (FS signal,
Frequency 5hift Signal)
It is called.

On the other hand, the FS signal demodulator on the receiving side is generally
Although C-tuned circuits and zero-crossing point detection methods are used,
These used analog technology.

However, in recent years, advances in semiconductor technology have led to the use of LSIs in various devices, which are advantageous in terms of cost, reliability, miniaturization, etc., and it is necessary to digitize circuits in order to make these LSIs.

In view of the above points, the present invention provides a new demodulation device that performs digital demodulation, and by incorporating it into an LSI, the cost is reduced.
This allows the device to be advantageous in terms of reliability, size reduction, etc.

The following description will be given with reference to the drawings. FIG. 1 is a block diagram showing a conventional demodulation device using a zero-crossing point method.

In FIG. 1, the received FS signal is amplified to an appropriate voltage level by a receiving amplifier (not shown), and then
Only the FS signal component is extracted by the band-limiting filter 1, and the amplitude is made constant by an amplification limiter (not shown) to obtain a shaped FS signal similar to the FS signal at the time of transmission.

This FS signal is a zero point detector (zero cross detector)
2 is introduced into a signal that generates a pulse at a point that cuts the time axis, and then introduced into a pulse conversion circuit 3.

The output of this pulse conversion circuit 3 is subjected to DC component smoothing by an integrating circuit corresponding to the modulation rate or a reduction filter 4 6, and then introduced into a discrimination circuit 5 to discriminate this frequency at a certain judgment level. This is what we do.

As described above, this demodulation method uses analog technology for frequency discrimination, and therefore is difficult to implement in LSI, leaving various problems in terms of cost, miniaturization, and reliability.

Fig. 2 is a block diagram of the demodulator according to the present invention. To explain Fig. 2, the received FS signal is amplified to an appropriate voltage level by a receiving amplifier (not shown), and then the received FS signal is amplified to an appropriate voltage level. The waveform generator 21 extracts the FS signal, and the amplitude is made constant by an amplitude limiter (not shown) to obtain a shaped FS signal similar to the FS signal at the time of transmission.

This FS signal is introduced into the zero point detector 22 to be used as a signal for generating a pulse at the point that cuts the time axis, and then introduced into the pulse conversion circuit 23.

A clock signal is introduced from a clock generation circuit 24 to the zero point detector 22 and pulse conversion circuit 23.

Further, the output of the pulse conversion circuit 23 is output from the clock generation circuit 2.
The clock signal from 4 is input to the shift register circuit 25, and the shift register circuit 25 is set to a size that can store data for one modulation rate.

The shift register circuit 25 is connected to a counting circuit 26, and the counting circuit 26 counts the number of "1"s stored in the shift register circuit 25 for each clock signal.

The counting circuit 26 is connected to a determination circuit 27, which determines whether the output from the counting circuit 26 exceeds a predetermined value and discriminates between the two frequencies. It is used to obtain data.

To explain the configuration of FIG. 2 above for a moment with reference to the waveform diagram of FIG. 6, the waveform ■ in FIG. 6 indicates transmission data, and the digital signals "1" and " The signal is transmitted using FS signals expressed by two different frequency carrier waves (signal frequencies) fl and f2 according to the signal frequency 0.

The received signal on the receiving side is attenuated during transmission and contains noise and distortion, so after amplifying it to the required level with an amplifier, a band-limiting filter 21 is used to remove unnecessary interference signals other than the bandwidth of the FS signal. After that, in order to remove the amplitude change, the amplitude is kept constant through an amplitude limiter and the sixth
Obtain the shaped FS signal shown in Figure 3.

The FS signal shown in FIG. 6 (2) is introduced into the zero point detector 22 and converted into the signal shown in FIG. 6 (2) which generates a pulse at a point that cuts the time axis.

Here, let the frequency f of the FS signal be f=fo±△f, and
The frequency f1 corresponding to "1" is fl-fo-△f, "O"
When the frequency corresponding to f2 = fo + △f, the pulse interval T of the waveform shown in Figure 6 ■ is: T1 = Can? T2 = Within the half-cycle range given by Buy7.

The signal shown in FIG. 6 (2) from the zero point detector 22 is introduced into the pulse conversion circuit 23 and converted into the signal shown in FIG. 6 (2).

The signal shown in Figure 6 ■ is a certain section from the zero crossing point.
This is a pulse train in which the zero crossing point is set to "0" and the section from that section to the next zero crossing point is set to "1".

In this case, the value of t ("0") in Figure 6 (■) is taken seriously, and therefore the signal in Figure 6 (■) which is the output of this circuit 23 is (1 drop #) for fl. The pulse width becomes almost "0" for f2.

The signal shown in FIG. 6 (3) from this pulse conversion circuit 23 is introduced into a shift register circuit 25, which has a length corresponding to one modulation speed.

In other words, if the modulation speed is M and the clock frequency is N, then
The length of the shift register is N/M bits.

For example, if the clock frequency is 89.488625 kHz and the modulation rate is 1200 Hz, it will be 74.57, so 75
Configure a bit shift register.

In other words, this is to obtain an accurate pulse train that exactly corresponds to the "1" or "0" section of the data in the shift register, and if the shift register is longer than the above configuration, The pulse train will include not only the pulse train corresponding to one data but also the pulse trains of previous and subsequent data, and if it is shorter than that, it will not be possible to obtain a complete pulse train corresponding to one data; This is because the pulse train does not accurately correspond to one piece of data, resulting in large errors in the received data.

The shift register circuit 25 reads the output from the pulse conversion circuit 23 each time a clock signal arrives, and the counting circuit 26 counts the number of "1"s stored in the shift register circuit 25 for each clock signal.

After all, these configurations use digital circuits to integrate the pulse train from the pulse train conversion circuit, and as a result, even if there is noise in the pulse train, it has almost no effect, and accurate received data can be obtained. It is made so that it can be obtained.

In this case, the shift register circuit 25 stores
h The number of "1" is vI (1-17) for fl and almost "0" for f2, but the output from this counting circuit 26 is the value counted for each clock signal. The signals are sequentially output, resulting in the signal shown in Figure 6 (■).

The determination circuit 27 discriminates between two frequencies of the signal shown in FIG. 6 (■) by determining whether the signal exceeds a predetermined determination level (J in FIG. 6 (■)).
This will give you a reception data like this.

It is desirable to set the determination level to around 2×M (1T''r) and provide an appropriate dead zone.

On the other hand, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 3 will be explained below.

The configuration shown in FIG. 3 is a further improvement of the configuration shown in FIG.

That is, in the configuration shown in FIG. 2 described above, the modulation speed and signal frequency f1. For example, if the modulation speed is 12008PS and the signal frequencies f1 and f2 are 1
In cases such as 300 Hz and 2100 Hz, see Figure 6■
As shown in FIG. 6, the received data is slightly distorted compared to the transmitted data ((■) in FIG. 6).

This is because there is no increase or decrease in the number of "1"s in the shift register circuit 25 in the period t in the signal shown in FIG.

Therefore, in the configuration of FIG. 3, the shift register circuit 25 of FIG. 2 is divided into two and provided as shift register circuits 25A and 25B.
The output of the shift register circuit 25A and the input to the shift register circuit 25A are introduced into another shift register 25B through the sum circuit 28, and this shift register 25B is connected to the counting circuit 26.

The configuration of the band-limiting filter, drop point detection filter, pulse conversion circuit, clock generation circuit, counting circuit, and determination circuit is the same as that shown in FIG.

The length of the shift register circuit 25A is Pl in FIG.
is set slightly longer than the length of the sum circuit 2.
The output of 8 becomes the signal shown in FIG.

If the length of the shift register circuit 25A is equal to the length of Pl, the pulses A and B shown in Figure 6 (■) will be continuous, and some of the pulses A and B may overlap due to distortion of the received signal. To prevent this, Pl.
It is set slightly longer than the length of the .

The signal shown in FIG. 6 (2) is introduced into the register circuit 25B, and thereafter the two frequencies are discriminated by the same operation as in FIG. 2.

In this case, the output from the counting circuit 26 becomes the signal shown in FIG. 6 (2), and the reception data obtained by the judgment circuit 27 making the judgment level J is shown in FIG. 6 (2).

In this way, when comparing the received data in FIG. 6 (2) and the received data in FIG. 6 (2), the received data obtained with the configuration shown in FIG. 3 is a signal closer to the transmitted data.

The configuration shown in FIG. 3 corresponds to Pl and t in the signal shown in FIG.
The relationship is valid when Pl <t.

In addition, in the case of 2P1<t, as shown in FIG. 4, the shift register circuit 25 in FIG. 2 is replaced with 25 A, 25 B,
25 It is desirable to have a structure that is separated into three parts: 1. It is clear from the above.

Although various methods can be considered for the counting circuit 26 that counts the "1"s stored in the shift register circuit 25 described above, a preferred embodiment of the counting circuit is shown in FIG.

This FIG. 5 shows a counting circuit related to the configuration shown in FIG. 3, and the shift register circuit 25A, sum circuit 28, and shift register circuit 25B are the same as those in FIG. The counting circuit 26 of 2 is indicated by a broken line.
There are 6 blocks.

That is, the counting circuit 26 is an up/down counter 26A.
and gives an up or down command to the counter 26A,
It consists of a control section 26B, and the control section "26B"
output B of shift register circuit 25B and input to shift register circuit 25B (output of sum circuit 28)
A is introduced.

This control section 26B operates the counter as described below.

That is, the input A of the shift register circuit 25B is rl.

If the output B of this circuit 25B is "0", the number of "1"s stored in the shift register circuit 25B increases by 1, so the counter 26A is incremented by 1.

On the other hand, if input A is "0" and output B is "1", the number of "1"s stored in the shift register circuit 25B is "
1", so the counter 26A is brought down.

In addition, input A is rl, output B is "1", or human power A is "
0'' and when the output B is ``0'', there is no increase or decrease in the number of ``1''s stored in the shift register circuit 25B, so no counting is performed.

This can be done by checking the input signal and output signal of the shift register circuit 25B.
The up/down counter 26A counts the number of "1"s stored in the shift register circuit 25B for each clock signal, and the counted value is used as the clock signal. Each signal is sequentially output, resulting in a signal as shown in FIG.

By configuring the counting circuit 26 in this manner, it is possible to count the number of "1"s stored in the shift register circuit 25B with a very simple circuit.

As explained above, the FS signal demodulator according to this invention differs from the one that performs frequency discrimination using analog technology, and uses a digital circuit to perform frequency discrimination, so it is cost-effective due to LSI implementation. It has features that make it an extremely advantageous device in terms of reliability, miniaturization, etc.

In the above explanation, the shift register was constructed, but it could also be constructed from a normal memory, and although the counter circuit was shown to count "1", it could also be constructed by counting "0". This can also be done in the same way.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional FS signal demodulation device, FIG. 2 is a block diagram showing the configuration of the FS signal demodulation device according to the present invention, and FIGS. 3 and 4 show other devices according to the present invention. FIG. 5 is a block diagram showing the configuration of the counting circuit of the device according to the present invention, and FIG. 6 is a diagram showing various waveforms related to FIGS. 2 and 3. 21: Band-limiting P wave device, 22: Zero point detector, 23: Pulse conversion circuit, 24: Clock generation circuit, 25: Shift register circuit, 26: Counting circuit, 27: Judgment circuit.

Claims (1)

[Scope of utility model registration request] A zero-crossing point detector that detects the zero-crossing point of a frequency shift signal (FS signal), and a certain section from the zero-crossing point detected by the detector as "0" and the next zero-crossing point from that section. a pulse conversion circuit for creating a pulse train with a period up to "1"; a memory means for storing a pulse train having a length corresponding to one modulation speed into which the output from the pulse conversion circuit is introduced; “l” or “o”
An FS signal demodulator comprising: a counting means for sequentially counting a frequency in response to a clock signal; and a determination circuit for discriminating frequencies based on a determination level with respect to the counted value of the counting means.