JPS58114552A - Fsk demodulation circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an exclusive LSI, by supplying a modulation signal to a zero cross point detection means via a filter, measuring the time between zero cross points, and outputting 0 or 1 depending on the result of comparison of the time with a predetermined value. CONSTITUTION:A modulation signal is inputted to an LPF11 through a buffer 10 and high frequency noise at the outside of the band is reduced. The output is let to a BPF12 to pass through two frequencies fL, fH. An output signal is applied to a comparator 14 via a limiter amplifier 13 and converted into a pulse signal. The signal is applied to a terminal ZC of an input port 21 of a microprocessor circuit 20. The circuit 20 monitors the zero cross of data incoming to the terminal ZC, i.e., the change in sign, measures the time RZC of zero cross points and compares it with a preset value TH. At RZC<=TH, then RD=1 is outputted and at RZC>TH, the RD=0 is outputted. Thus, the system is constituted with a general-purpose microprocessor.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a modem that transmits data from a computer to a terminal device or from a terminal device to a computer, and particularly relates to a modulator/demodulator that transmits data through a telephone line.
frequency 5hift Keying (hereinafter referred to as F
(denoted as SK) f, related to the IT tone circuit.

(2) Technical Background Data modems generally have two functions. One of the main functions is the modulation function that converts the binary code generated by the terminal equipment into a signal suitable for the analog transmission characteristics of the line, and the demodulation function that returns the signal received from the line to the original binary code. be.

There are various modulation and demodulation methods depending on the number of binary codes that can be sent per second, that is, the transmission speed (bit/sec). In particular, the FSK method is generally used in data modems with a bit rate of 1200 bits or less. There is. This method uses 2 for binary data O and 1.
This is a method in which different frequencies rL and rH are assigned and alternately switched.

(3) Problems with conventional technology The zero-crossing method is used as a demodulation method for the FSK method mentioned above.

P L L (Phase Locked Loop)
There are various laws and regulations, and dedicated LSIs are used. This is largely due to advances in semiconductor integrated circuit technology, with devices becoming smaller in size and having improved characteristics such as higher reliability. However, this LSI is dedicated to this purpose, and if only a small number of them are used, the cost would be high and it could not be realized. One possible way to solve this problem is to use a highly versatile microprocessor. However, it cannot support the transmission speed of the FSK system, for example, the aforementioned 1200 bit/sec, and can only be used for very slow bit rates. This is because the calculation speed of microprocessors was not fast enough for digital transmission signal processing.

(4) Purpose of the Invention The present invention enables the use of a general-purpose microprocessor in a demodulator for FSK data transmission.
The purpose is to develop dedicated LS for each of the zero-crossover method and PLL method by using a general-purpose microprocessor.
An object of the present invention is to provide a zero-crossing demodulation method for a line FSK modem that does not require the provision of an I.

(5) Structure of the invention The characteristics of the present invention are frequency shift,
In a keying type data modulation/demodulation device, a bandpass means for passing a band of a modulated signal, a zero-crossing point detection means for detecting a zero-crossing point of an output signal of the band-passing means, and a zero-crossing point detection means for detecting a zero-crossing point of an output signal of the band-passing means; FSK comprising a time measuring means for measuring the time between zero crossing points, and a comparing means for comparing the output of the time measuring means with a predetermined value and outputting O or 1 depending on the magnitude relationship.
It is in the demodulation circuit.

(6) Embodiments of the Invention Before describing the present invention in detail, a zero-cross demodulation method for FSK signals, which is generally performed by a dedicated LSI, will be explained.

FSK modulation signal F (tl is generally expressed as follows.

F(tl=A sinψ(t)・・・・・・・・・(
1) dψ/dt=2π[H-3D(t) +2πf L (1-3D(tl)) (2) Here, A is the amplitude, and fL and fH are assigned to binary, i.e., 05=3-1 The carrier frequency, S D (tl is a function of time taking the binary transmitted data, i.e. 0.1. Figure 1 shows the FSX modulated signal and the binary transmitted data, 5
The FSX modulation signal changes to a frequency corresponding to D(tl. That is, when 5D(tl is 1, the frequency of F(tl is rH), and when S D(tl is O, it is f1-.

FIG. 2 shows an example of the configuration of the zero-crossing method for the FSK modulated signal shown in FIG. 1. The part containing two carrier frequency components is filtered from the received FSX signal by a receive filter (BPF).
)1. This output is a signal from which noise in unnecessary bands has been removed, and is the FSK signal F before passing through the line.
It is almost the same as (t). Here, the signal is F′
(Set as tl.Next, in order to accurately determine the zero crossing position, input the filter output signal F' (11) to the limiter amplifier 2. In other words, the signal output of the filter is F'ft)
A is converted into a pulsed signal port. Next, the output enters a monostepple multi-circuit 3 and is converted into a signal C having a constant pulse width at the rising and falling edges of the pulsed signal port. In other words, a signal C is generated with a constant pulse width at zero crossing or 5-1 4~. Since the signal becomes a density modulation signal with a constant pulse width, it is converted into a low frequency signal 2 corresponding to the pulse density by a demodulation filter (LPF) 4. This signal is almost the same as the binary signal on the transmitting side, and is input to a slicer 5 that slices it at a certain level to obtain a demodulated signal RDho.

The present invention belongs to the zero-crossing method shown in FIGS.
It uses only time-related information and does not use waveform properties.

The present invention has the following method. The signal port of the limiter amplifier 2 in Fig. 2 is set at the time when the previous sample value and the current sample value have different signs at a constant sampling period Ts, that is, change from O to 1 or from 1 to 0 (hereinafter referred to as zero-crossing time). ) to monitor. That is, a zero-crossing register R1c is provided in the microprocessor circuit 20, and 1 is added to the contents of the register every sampling period TS, and when the sample value changes, the contents of the register RZC are read and simultaneously reset or set to a certain fixed value. Set. This read data indicates a value obtained by quantizing the time between adjacent zero-crossing intervals of the output pulses of the limiter amplifier using the sampling period TS. f
The time intervals Z CL and Z CH of the interval where the binary transmission data Sl]t) in the il formula is 0 or 1 are respectively ZCL-(1/2 f L)-(L/Ts)-fs/2
fL -・-・1al ZCH-(1/2 f H) ・(1/Ts)-f
s/2fH---(4). Here, fs means fs=1/Ts, that is, sampling frequency. Carrier frequency f1-.

Since fH is predetermined, the time interval Z C
By comparing the L, Z CH and the quantized value, that is, the read data, it is possible to determine whether the binary transmission data is 0 or I. By outputting the result as two Buddha monk names, binary transmission data 5D(t)
A demodulated signal, ie, received data RD, can be obtained.

FIG. 3 shows a configuration example of an embodiment of the present invention. A signal input from the input terminal is input to the buffer 10.

The buffer has functions such as amplification and impedance conversion, and inputs the signal to the next stage low-pass filter (hereinafter referred to as LPF) 11. LPFII is a filter made of passive elements that reduces high-frequency noise outside the band. The output of LPFll enters a bandpass filter (hereinafter referred to as BPF) 12, which filters two frequencies rl,
Pass rH. BPF 12 is an active filter consisting of active elements. The output of BPF 12, i.e., the signal F'(
tl enters the comparator 14 via the limiter amplifier 13 and is converted into a pulse-like signal. This signal is signal F
' This is a pulse signal having zero-crossing information of fil.

The output of the comparator 14, that is, the pulse signal having the aforementioned zero-crossing information, enters the terminal Zc of the input/output port 21 of the microprocessor circuit 20. The human output boat 21 is connected to the pass line 22 of the microprocessor MPU. Also connected to the bus line 22 are a read-only memory ROM storing a time measurement program and a random access memory RAM storing time sub-side data. Further, the terminal RD of the input/output port 21 is a demodulation output terminal, and a signal demodulated by the microprocessor MPU is output.

FIG. 4 shows a flowchart within microprocessor circuit 20. FIG. In the monitoring loop 30, a Zc zero crossing detection 31 monitors zero crossings of data entering the terminal Zc, that is, sign changes of the input signal. If the sign has not changed, increment the value of the Zc counter RZC in the memory RAM by 3.
2 and again detects the sign change of the input signal by detecting Zc zero crossing 31
to monitor. Increment 32. Zero cross detection 31 of Zc is a monitoring loop 30. When a sign change of the input signal is detected, the Zc counter R exits from the monitoring loop 30.
Output processing 33 is performed using the ZC value. First, output processing 3
In step 3, the value of the ZC counter Rzc is compared with a preset constant TH. The constant TH mentioned above is (3),
+Time interval Z CL , Z CH shown in formula 41
This is a threshold level that sets the value of the Zc counter RZC to which the value of the Zc counter RZC is closer.
If the value of is equivalently close to the time interval ZCL, the received data R
If D is equivalent to the O1 time interval ZC)l, the received data RD is set to 1. That is, R
If XC≦TH, output processing 35 for RD=1,
If Rzo>T H, output processing 36 for RD=O
I do. When the aforementioned output processing is completed, the value of the Zc counter Rzo for the next received data is set 37. Although it is necessary to measure the interval from immediately after exiting the monitoring loop 30 to the next zero crossing, comparison with the constant TH 34,
Since the output processing 35.36 of the received data RD is being performed, the value that takes into account the time from the time when the monitoring loop exits after the completion of the above-mentioned output processing 35.36 until the end of the output processing 35.36 is set to the Zc counter R or C. After setting this, the monitoring loop begins processing. Note that since the output processing 33 is sufficiently faster than the zero crossing time interval, no zero crossing occurs during the output processing 33. Output processing 35 starts from the time when the above-mentioned monitoring loop is exited.
．． The optimal value considering the time until the end of 36 is the value obtained by dividing the machine cycle M of the output process by the machine cycle N of the monitoring loop. Also, the threshold level T
It is desirable that H be TH=(ZC)l+ZcL)/2Nr. Here, the time is 10 cycles for one machine. Setting the threshold level TH in this way, that is, the time interval ZCL, ZC
By setting the time interval exactly in the middle of H, it is possible to detect errors even if fluctuations occur.The value obtained by multiplying the machine cycle N of the monitoring loop by one machine cycle time τ at this time is The sampling period Ts should be at least smaller than the sampling period Ts mentioned above.

For example, f L = 1.65KHz, f H =
If it is 1.85KHz, ZCL-ZCH= (1/2X1.65XTS)-(
1/2x1.85xTs) ≧Δ...1/ from (5)
Ts≧30.5×Δ(KHz), and Δ may be 1 if there is no fluctuation at all, but it is actually better to be larger.

For example, if Δ==3, then 1/T s= 1/
90 (m5ec), and it is sufficient if N machine cycles are completed within this time.

(7) Effects of the invention The present invention provides an FSK demodulator using a conventional dedicated LSI, etc.
It is possible to construct it using a versatile microprocessor, and by using the present invention, it is possible to obtain an inexpensive FSX demodulator even in a small number.

[Brief explanation of the drawing]

FIG. 1 is a signal waveform diagram of an FSK signal, FIG. 2 is a configuration diagram of a conventional example, FIG. 3 is a configuration diagram of the present invention, and FIG. 4 is a processing flow diagram of the present invention. 2...Band pass filter, 14...Comparator, 20...Microprocessor circuit, 30...Monitoring loop, 33...Output processing. Patent applicant: Fujitsu Limited, -D” It ←
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Claims (2)

[Claims] (1) In an FSK (Frequency Shift Keying) type data modulation/demodulation device, a bandpass means for passing a band of a modulated signal, and a zero-crossing point detection means for detecting a zero-crossing point of an output signal of the band-passing means. , a time measuring means for measuring the time between the zero crossing points obtained by the zero crossing point detecting means, and the output of the time measuring means are compared with a predetermined value, and O or 1 is set depending on the magnitude relationship. An FSK demodulation circuit comprising an output comparison means. (2) The FsKitL adjustment circuit according to claim 2, wherein the time measuring means and the comparing means are comprised of at least one microprocessor circuit.