JPH02287975A - Asynchronous detecting circuit of digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To detect the synchronous/asynchronous by gating an output obtained by decoding an output signal of a counter circuit and a differential output of a reference signal from a video tape recorder VTR. CONSTITUTION:A digital dubbing signal is inputted to a clock signal generating circuit 11 and a clock signal is generated. Also, a prescribed count number is counted by a counter circuit 12. An output signal of the circuit 12 detects and outputs a value set in advance through a decoding circuit 13. A reference signal from a VTR outputs a pulse signal to a rise/fall point of the reference signal by a differentiating circuit 14, inputted to a gate circuit 15 with an output signal of the circuit 13, inputted as a reset signal to the circuit 12, and also, becomes an asynchronous detecting signal. In such a way, the synchronous/ asynchronous can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an asynchronous detection circuit for a device for recording and reproducing audio signals as digital signals in a video tape recorder (hereinafter referred to as a VTR).

Conventional technology When recording and playing back digital audio signals on a VTR, V
It is necessary to synchronize the frequencies of the clock signal that can be used by the TR side circuit and the clock signal that is used by the audio digital signal processing circuit. Generally, a vertical synchronization signal or a horizontal synchronization signal of a video signal on the VTR side is used as a reference signal, and a reference clock signal on the digital signal processing circuit side is generated in synchronization with this signal.

Next, FIG. 4 shows an example of digital dubbing of an audio signal between two recording/reproducing apparatuses. An audio signal is dubbed from the recording/reproducing device No. 41 to the recording/reproducing device No. 42. Both VTRs 43 and 44 output reference signals to digital signal processing circuits 45 and 46, respectively, and digital signal processing circuits 45 and 46 output V'I'R4.
3 and 44, respectively. Then, the digital signal processing circuit 45 outputs a digital audio signal, and inputs it to the digital signal processing circuit 46 to perform digital dubbing. At this time, in the digital signal processing circuit 46, it is necessary that the reference signal from the VTR 44 and the digital dubbing signal input from the digital signal processing circuit 45 are synchronized. Processing will no longer be possible and an incorrect digital signal will be recorded on the VTR 44. As shown in FIG. 4, by inputting the same video signal to the VTRs 43 and 44 as a reference signal, the VTRs 43 and 44 can be synchronized, and as a result, the digital signal processing circuits 45 and 46 can also be synchronized, resulting in correct dubbing. An action is taken.

Problem to be Solved by the Invention However, in the above case, if the same video signal is not input to the VTRs 43 and 44, the VTRs 43 and 44 are out of synchronization, and as a result, the same video signal is input to the digital signal processing circuit 46. This means that the digital dubbing signal received by the VTR 44 is not synchronized with the reference signal from the VTR 44, and a correct dubbing operation cannot be performed.

An object of the present invention is to provide an asynchronous detection circuit that detects whether synchronization is established or not with a simple circuit configuration.

Means for Solving the Problems To achieve this object, the asynchronous detection circuit of the present invention includes a circuit that generates a clock signal from a digital dubbing signal, a circuit that counts this clock signal, and an output signal of this counter circuit. The circuit includes a circuit for decoding a predetermined value, and a circuit for gating the output signal of this decoding circuit and a signal obtained by differentiating a reference signal from a VTR.

Function: With this configuration, the output signal of the gate circuit is used as the reset signal of the counter circuit, and the count number of the counter circuit is set to be the same as the frequency of the reference signal from the VTR.
If the reference signal from the gate circuit is not synchronized with the reference signal from the gate circuit, a signal will be output from the gate circuit, and this output signal can be used to detect the asynchrony.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an asynchronous detection circuit in one embodiment of the present invention. In FIG. 1, 11 is a clock signal generation circuit, 12 is a counter circuit, 13 is a decoding circuit for decoding with a predetermined value, 14 is a differentiation circuit, 1
6 is a gate circuit.

The operation of the asynchronous detection circuit configured as described above will be explained below.

The digital dubbing signal is input to the clock signal generation circuit 11, and a clock signal synchronized with the digital dubbing signal is generated. This clock signal is used by counter circuit 1
2, and a predetermined count number is counted. The output signal of this counter circuit 12 is transmitted to a decoding circuit 13.
The decode circuit 13 detects and outputs a preset value. On the other hand, the reference signal from the VTR is input to the differentiating circuit 14, which outputs pulse signals at the rising and falling points of the reference signal. This pulse signal and the output signal of the decoding circuit 13 are input to the gate circuit 15, and the output signal of the gate circuit 15 is input to the counter circuit 12 as a reset signal and also as an asynchronous detection signal.

Next, a case where the digital dubbing signal and the reference signal from the VTR are synchronized will be explained based on the timing chart shown in FIG. Clock signal generation circuit 11
If the frequency of the clock signal generated by is 2(n+1) times the frequency of the reference signal from the VTR, synchronization can be achieved at the timing shown in Figure 2 by setting the count number of the counter circuit 12 to (n+1). become.

The decoding circuit 13 is set to decode values near the count numbers O and n, as shown in Fig. 2, and the width of the output signal is slightly larger than the time variation of the reference signal from the VTR. Make it.

As a result, no output signal from the gate circuit 15 is output as shown in FIG.

Next, the case where the digital dubbing signal and the reference signal from the VTR are not synchronized will be explained using the timing chart shown in FIG. 3. Clock signal generation circuit 11
In this case, the frequency of the clock signal generated by the clock signal is higher than that of the clock signal generated by the clock signal, and the output signal from the decoding circuit 13 that decodes the output signal of the counter circuit 12 is the second clock signal as shown in FIG.
It is output at an earlier timing than shown in the diagram. As a result, the output signal of the gate circuit 15 is the output signal from the differentiating circuit 14, and is inputted as a reset signal to the counter circuit 12. Since the counter circuit 12 starts counting again from d when the reset signal is input, the same operation is repeated, and a signal is constantly output from the gate circuit 15. Therefore, this gate circuit 15
By using the output signal from as an asynchronous detection signal, it becomes possible to distinguish between synchronous and asynchronous.

Effects of the Invention As described above, the present invention provides an output signal obtained by decoding an output signal of a counter circuit that counts a clock signal generated from a digital dubbing signal using a decoding circuit, and a VTR.
By using a gate circuit to gate the output obtained by differentiating the reference signal from the digital dubbing signal and the output from the VTR
It is possible to detect synchronization or asynchrony with the reference signal from the source, which is highly effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an asynchronous detection circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram in the case of synchronization in the same embodiment, and FIG. 3 is a timing diagram in the case of non-synchronization in the same embodiment. 4 are block diagrams of a digital dubbing device. 11... Clock signal generation circuit, 12... Counter circuit, 13... Decoding circuit, 14...
・Differential circuit, 15...gate circuit. Name of agent: Patent attorney Shigetaka Awano (1 person)

Claims (1)

[Scope of Claims] A clock signal generation circuit that generates a clock signal from an input digital dubbing signal, a counter circuit that counts the clock signal from the clock signal generation circuit, and a predetermined value based on the output signal of the counter circuit. A digital device comprising: a decoder circuit that decodes and outputs a signal; a differentiation circuit that differentiates a reference signal from a VTR; and a gate circuit that gates an output signal of the differentiation circuit and an output signal of the decode circuit. Asynchronous detection circuit for signal recording and reproducing equipment.