JPH02284521A - Unlocking detection circuit - Google Patents

Abstract

PURPOSE:To stabilize the detection of unlocking by providing two detection circuits and outputting an unlocking detection signal when the term of the active levels of an up signal and a down signal from a phase frequency detector becomes longer than one period of a reference input signal or a signal from a voltage control oscillator. CONSTITUTION:A phase frequency detection circuit 10 is included in a PLL circuit which is an object, and the circuit 10 compares the phases of the signal from the voltage control oscillator which is periodically level-changed, the inverse of V with the reference input signal from a crystal oscillator which is periodically changed, the inverse of R. Then, the up signal, the inverse of UP, and the down signal DW are outputted. The first detection circuit 1 outputs the first unlocking signal V13 when the term of the active level of the up signal, the inverse of UP, becomes longer than one period of the reference input signal, the inverse of R. The second detection circuit 2 outputs the second unlocking signal V23 when the term of the active level of the down signal, the inverse of DW, becomes longer than one period of the signal, the inverse of V.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an unlock detection circuit, and particularly to an unlock detection circuit for a PLL circuit.

[Conventional technology]

An example of a conventional unlock detection circuit of this type is shown in FIG.

In FIG. 4, the phase frequency detection circuit 10 receives a signal (hereinafter simply referred to as signal) from a voltage controlled oscillator that is included in the target PLL circuit and whose level changes periodically, and a crystal oscillator that changes periodically. Compare which phase of the reference input signal R from etc., and determine the phase lead or lag of these signals, and the up signal πd and the down signal that are at active level (low level) for a period corresponding to the magnitude of the phase difference. “Output W.

Up signal UP and down signal child W are NAND gate G
After being integrated by 20, it is divided into two parts, one of which is directly connected to N
AND gate G2. and the other is input to the NAND gate G21 via the delay circuit 3.

The NAND gate G21 receives these input signals (Vl,
V2) and outputs a low-level active unlock detection signal ULD.

The delay circuit 3 is an inverter ■4. ■6, resistance R1, R2,
and capacitors C, , C2, and delay the output signal v1 of the NAND gate G20 by the time set by these capacitors.

Therefore, when the active level period of the up signal UP and the down signal DW becomes longer than the delay time of the delay circuit 3, the unlock detection signal ULD of active level (low level) is output.

FIG. 5 shows the operation timing of each part signal of this unlock detection circuit.

FIG. 5 shows a state in which the falling edge of the signal ■ (■1) lags behind the falling edge of the first reference input signal R (R1).

In this case, the up signal UP changes from high level to low level at the falling edge of the reference input signal R (R1), and the signal V (V
It becomes high level at the falling edge of l). That is, the up signal UP signal becomes low level by the amount of phase delay.

Furthermore, the up signal "T" and the down signal DW are NAN
The output signal vl of the D gate G2o and the output signal 2 of the delay circuit 3 are input to the NAND gate G21, so the unlock detection signal ULD is output to the delay circuit 3.
It changes from a high level to a low level at the rising edge of the output signal v2 of the NAND gate, and changes to a high level at the falling edge of the output signal 1 of the NAND gate.

That is, the input signal (R.

Only when the phase difference ((2)) becomes larger than the delay time set by the delay circuit 3, the unlock detection signal ULD becomes low level, and unlocking of the PLL circuit can be detected.

In addition, the third and fourth reference input signals R (R3, R4
), the signal V (V3.V4) indicates a just lock state, and in this case, the unlock detection signal ULD does not go to a low level.

Further, a state in which the phase of the signal V (V6) is ahead of the sixth reference input signal R (R6) is shown.

In this case, the down signal DW changes from high level to low level at the falling edge of the signal V (V6), and the reference input signal R (R
It becomes high level at the falling edge of 6).

Since the low level period of this down signal DW is longer than the delay time of the delay circuit 3, a low level unlock detection signal ULD is output.

Furthermore, in the second and fifth periods, there is no low-level period exceeding the delay time of the delay circuit 3 for both the up signal (2) and the down signal DW, so the low-level unlock detection signal ULD is not output.

Note that FIG. 6 shows an example of a PLL circuit that is subject to unlock detection.

[Problem to be solved by the invention]

The conventional unlock detection circuit described above uses the up signal UP.
and the active level period of the down signal DW is determined by the delay circuit 3.
Inverter I4. I5, resistors R, R2, and capacitors C1 and C2 are configured to output an active level unlock detection signal when the delay time is longer than that determined by R, R2, and capacitors C1 and C2. Since the delay time fluctuates, there is a drawback that the unlock detection criteria changes or becomes unstable.

An object of the present invention is to provide an unlock detection circuit that is not affected by manufacturing variations or environmental changes and is capable of stably detecting unlock based on a fixed standard.

[Means to solve the problem]

The unlock detection circuit of the present invention is included in a target PLL circuit, and compares the phases of a signal from a voltage controlled oscillator whose level changes periodically with a reference input signal whose level changes periodically, and detects these signals. The phase frequency detector outputs an up signal and a down signal that are at an active level for a period corresponding to the phase advance or lag and corresponding to the magnitude of the phase difference. a first detection circuit that outputs a first unlock detection signal when the input signal becomes longer than one period; and a period of the active level of the town signal becomes longer than one period of the signal from the voltage controlled oscillator. and a second detection circuit that outputs a second unlock detection signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, a phase frequency detection circuit 10 receives a signal (hereinafter simply referred to as signal V) from a voltage controlled oscillator that is included in a target PLL circuit and whose level changes periodically, and a crystal oscillator whose level changes periodically. The up signal UP and the down signal DW are at an active level (low level) for a period corresponding to the phase lead or lag of these signals and corresponding to the magnitude of the phase difference by comparing the phases of the reference input signal R from etc. Output.

The first detection circuit 1 includes a NOR game) Gl, G2, an inverter 1, a D-type flip-flop FF1, and a NAN
It is provided with a D gate G5, and outputs a first unlock detection signal v13 when the period of active level (low level) under the up signal π becomes longer than one period in one hundred of the reference input signal.

The second detection circuit 2 includes NOR gates G, G4, inverter 2, D-type flip-flop FF2, and NAN
It includes a D gate G6, and outputs a second unlock detection signal v23 when the active level (low level) period of the down signal DW becomes longer than one cycle of the signal (2).

NAND gate G7 and inverter 3 receive first and second unlock detection signals V1. ．． V2. are integrated and output as an unlock detection signal ULD.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

The first reference input signal π (R1), the signal ■ (Vl) (
In the case of (hereinafter displayed as signal R1, signal ■1),
The signal v1 is in a state lagging behind the signal R2, and the up signal UP is at a low level from the falling edge of the signal R1 to the falling edge of the signal 1, as in the conventional example.

The output signal v12 of the flip-flop FF.1 changes from a low level to a high level at the falling edge of the output signal V11 of the NOR gate G1, and changes to a low level at the rising edge of the up signal UP.

Furthermore, the output signal v11 of the NOR gate G□ and the output signal ■12 of the flip-flop FF are the NAND gate G5.
In this case, the output of the NAND gate G5, that is, the first unlock detection signal V13, remains at a high level, and the unlock detection signal ULD also remains at a high level.

In addition, in the case of the fourth signal R4, signal ■4, signal ■4
is ahead of the signal R4, the down signal DW is at a low level from the falling edge of the signal V4 to the falling edge of the signal R4, as in the conventional example.

The output signal V22 of the flip-flop FF2 changes from a low level to a high level at the rising edge of the output signal 21 of the NOR gate G3, and changes to a low level at the rising edge of the down signal DW.

Also in this case, the second unlock detection signal 23 and the unlock detection signal ULD remain at high level.

However, in the case of the fifth signal R5, for example, the fifth signal V5 (indicated by a broken line) is the sixth signal R5.
If it exists before 6, the timing will be like that of the first signal R1, Vl described above, but since the fifth signal 5 does not exist, the up signal UP is at the falling edge of the fifth signal R5. It goes from high level to low level at the edge, and goes to high level at the falling edge of the sixth signal v6.

Furthermore, the output signal ■12 of the flip-flop FFl is NO.
It changes from low level to high level at the falling edge of R gate G1, and changes to low level at the next falling edge of output signal v11 of NOR gate G1.

The output signal of the NAND gate G, that is, the first unlock detection signal ■IS, is the output signal of the NOR gate G□, ■l
At the rising edge of l, it goes from high level to low level, and NO
It becomes high level at the rising edge of the output signal 11 of the R gate G1.

At this time, the unlock detection signal ULD changes from a high level to a low level at the falling edge of the output signal of the NAND gate G5, and changes to a high level at the rising edge, thereby detecting the unlocked state.

In the case of the ninth signal v9, the aforementioned fifth signal R5
Similarly, since the broken-line 9th signal R9 does not exist for the 9th signal ■9, the down signal DW changes from a high level to a low level at the falling edge of the signal ■9, and the 10th signal R1o The falling edge of causes a high level.

Furthermore, the output signal V22 of flip-flop FF2 is NO.
It changes from a low level to a high level at the falling edge of the output signal V21 of the R gate G3, and changes to a low level at the next falling edge of the output signal V21 of the NOR gate G3.

Further, the output signal of the NAND gate G6, that is, the second unlock detection signal 23 is the output signal V of the NOR gate G3.
The rising edge of 21 changes from high level to low level, and the falling edge changes to high level.

At this time, the unlock detection signal ULD changes from high level to low level at the falling edge of the output signal of the NAND gate G6, and changes to high level at the rising edge, and as described above,
Detects that it is unlocked.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

The difference between this second embodiment and the first embodiment is that the D terminal input of the flip-flops FF, FF2 of the detection circuit is connected to each flip-flop FF, FF2 in the first embodiment.
While the inverted output signal (Q) of FF2 is used, the second
In this embodiment, the power supply voltage is on the high potential side.

Therefore, the low level period of the up signal UP and the down signal DW is long, and within this period, the reference input signal R or the signal ■
When a plurality of cycles occur, in the first embodiment, the output signals of flip-flops FF+ and FF2 are inverted every time the cycle changes, so the unlock detection signal ULD goes to a low level unlocked state every - cycle. On the other hand, in the second embodiment, the output signal of the flip-flop is not inverted, so the unlock detection signal ULD is
It has the advantage that it can be unlocked at a low level.

As mentioned above, in the present invention, the conventional resistance,
Delay circuits such as capacitors and inverters are no longer required, and can be constructed using only digital circuits.

〔Effect of the invention〕

As explained above, the present invention is applicable when the period of the active level of the up signal and down signal of the phase frequency detector of the target PLL circuit becomes longer than one period of the reference input signal or the signal from the voltage controlled oscillator. By adopting a configuration that outputs an unlock detection signal, there is no need for conventional delay circuits such as resistors, capacitors, and inverters.
Since it can be constructed using only digital circuits, it has the advantage of being able to stably detect unlocking based on a fixed standard without being affected by manufacturing variations or environmental changes.

[Brief explanation of drawings]

1 and 2 are a circuit diagram of a first embodiment of the present invention and a timing chart of signals of each part to explain the operation of this embodiment, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. The circuit diagram, FIGS. 4 and 5 are a circuit diagram showing an example of a conventional unlock detection circuit, and the timing diagram of each part signal to explain the operation of this unlock detection circuit, and FIG. 6 is a circuit diagram showing an example of a conventional unlock detection circuit. FIG. 2 is a block diagram of a target PLL circuit. 1, IA, 2.2A...detection circuit, 3...delay circuit, 10...phase frequency detector, 20...reduction filter, 30...voltage controlled oscillator, 40...frequency division vessel,
C1, C2...Capacitor, FF, FF2...Flip-flop, 01-G4...NOR gate, G. ~G7 G11~G21...NAND gate, ■0 ■ ~■5...Inverter,...Resistance.

Claims (1)

[Claims] The phase of the signal from the voltage controlled oscillator, which is included in the target PLL circuit and whose level changes periodically, is compared with the reference input signal whose level changes periodically, and the phase lead or lag of these signals is determined. and when the period of the active level of the up signal of the phase frequency detector that outputs the up signal and the down signal that are at the active level for a period corresponding to the magnitude of the phase difference becomes longer than one period of the reference input signal, the first a first detection circuit that outputs an unlock detection signal; and a second detection circuit that outputs a second unlock detection signal when the active level period of the down signal becomes longer than one cycle of the signal from the voltage controlled oscillator. An unlock detection circuit comprising: a detection circuit.