JPH02284429A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in integration degree and simplification of a process by forming a lower electrode with the same silicon as base extraction polycrystalline silicon of a bipolar transistor and forming an upper electrode with the same silicon as polycrystalline silicon of an emitter part of the above transistor. CONSTITUTION:Both emitter diffusion layer 15 and a base diffusion layer 9 are constructed so that they are extracted with polycrystalline silicon regions 16a and 11a and a capacitor 21 is constructed so that an insulating film 13a is sandwiched between the upper electrode 16b and lower electrode 11b. The capacitor 21 is disposed on a field oxide film 4 and the electrode 11b is formed with the same polycrystalline silicon as silicon 11a and further, the electrode 16b is formed with the same polycrystalline silicon as silicon 16a. In this way, both silicon 11a and the electrode 11b as well as both silicon 16a and the electrode 16b are formed respectively with the same process without making it necessary to give considerations to an interruption which takes place between the conduction of electricity and the diffusion layer of the other circuit elements. Then, the capacitor 21 is disposed at an optional position on the film 4 and this device not only improves an integration extent but also simplifies steps of the process.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technology that is effective when applied to semiconductor devices. The present invention relates to a technique effective for use in a semiconductor device including a bipolar transistor and a capacitor configured such that an insulating film is sandwiched between upper and lower electrodes.

[Prior Art] In order to increase the integration and speed of semiconductor devices, in recent years, bipolar transistors in which the emitter and base are separated in a self-aligned manner have been widely used in semiconductor devices. . This bipolar transistor has an emitter diffusion layer and a base diffusion layer each made of polycrystalline silicon doped with impurities, and the semiconductor device is also equipped with capacitors and the like to form a circuit. . This capacitor may be one in which a diffusion layer formed on the substrate surface is used as a lower electrode, and an insulating film and an upper electrode are sequentially laminated on this diffusion layer, or one in which the emitter polycrystalline silicon of the above-mentioned bipolar transistor is used as a lower electrode. A structure in which an insulating film and an upper electrode are sequentially laminated thereon is known.

[Problems to be Solved by the Invention] However, the semiconductor device including the above bipolar transistor and capacitor has the following problems.

In other words, in a semiconductor device including a capacitor in which a diffusion layer formed on the surface of a substrate is used as a lower electrode, and an insulating film and an upper electrode are sequentially laminated on this diffusion layer, electrical conduction is interrupted by the diffusion layer of the capacitor. Therefore, it must be separated by a certain distance from the diffusion layers of other circuit elements (transistors, capacitors, resistors, etc.), which poses a problem in that it is difficult to achieve high integration.

In addition, in a semiconductor device including a capacitor in which the emitter part of a bipolar transistor is made of polycrystalline silicon as a lower electrode, and an insulating film and an upper electrode are successively laminated thereon, the above-mentioned problem of achieving high integration is solved, but the emitter Since the step of forming the upper electrode above the polycrystalline silicon is added, there is a problem that the process becomes complicated.

Here, it is conceivable that the capacitor structure may be a 5TC (stacked capacitor cell) structure adopted as a DRAM of MOS transistors;
In the TC structure, a capacitor with an insulating film sandwiched between upper and lower electrodes is formed above a semiconductor substrate, and the lower electrode of this capacitor is in contact with a relatively small diffusion layer formed on the surface of the substrate. Therefore, compared to a capacitor in which the diffusion layer, insulating film, and upper electrode are laminated in this order, higher integration can be achieved because the diffusion layer is smaller, but the problem of high integration still remains, and moreover, the problem of high integration still remains. Since the impurities introduced into the base-drawing polycrystalline silicon have a conductivity type opposite to those introduced into the base-drawing polycrystalline silicon, the lower electrode and the base-drawing polycrystalline silicon cannot be formed in the same process, making the process complicated. There is a problem that this is not desirable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device with an improved degree of integration and which can be easily manufactured.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the capacitor of a semiconductor device includes a bipolar 1 helangistor in which both the emitter diffusion layer and the base diffusion layer are made of polycrystalline silicon, and a capacitor configured such that an insulating film is sandwiched between upper and lower electrodes. The lower electrode of this capacitor is formed of the same polycrystalline silicon as the base lead-out polycrystalline silicon of the bipolar transistor, and the upper electrode of the capacitor is formed of the same polycrystalline silicon as the emitter part of the bipolar transistor. It is made of the same polycrystalline silicon.

[Operation] According to the above-described means, the capacitor is disposed on the field oxide film, the lower electrode of this capacitor is formed of the same polycrystalline silicon as the base-drawing polycrystalline silicon of the bipolar transistor, and the upper part of the capacitor is Since the electrode is formed of the same polycrystalline silicon as the emitter polycrystalline silicon of the bipolar transistor, no consideration is given to blocking electrical continuity between the capacitor and the diffusion layer of other circuit elements formed on the substrate surface. The capacitor can be placed anywhere on the field oxide film, and the base polycrystalline silicon and the lower electrode of the capacitor are connected to the emitter polycrystalline silicon and the upper electrode of the capacitor. Since these can be formed in the same process, the process can be simplified, and the above objectives of improving the degree of integration and manufacturing easily can be achieved.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor device according to the present invention. The outline is as follows.

The semiconductor device of this embodiment is a semiconductor device including a so-called 5EPT (Selective Etching of Polysilicon Technology) transistor and a capacitor 21. In this semiconductor device, the 5EPT transistor is N
It is a PN type transistor, and its emitter diffusion layer 15,
Both the base diffusion layers (graft bases) 9 are drawn out with polycrystalline silicon 16a and lla, that is, the emitter and base are separated in a self-aligned manner, and the capacitor 21 is insulated. The membrane 13a is sandwiched between upper and lower electrodes 16b and 11b. In this embodiment, the capacitor 21 is arranged on the field oxide film 4, and the lower electrode 11b of the capacitor 21 is made of the same polycrystalline silicon as the base lead-out polycrystalline silicon lla. The upper electrode 16b of the capacitor 21 is made of the same polycrystalline silicon as the emitter polycrystalline silicon 16a.

Therefore, there is no need to consider cutting off electrical conduction between the capacitor 21 and the diffusion layers of other circuit elements formed on the surface of the substrate 1, and the base is made of bent polycrystalline silicon.
la and the lower electrode 11b of the capacitor 21, and the emitter polycrystalline silicon 16a and the upper electrode 1 of the capacitor 21.
6b can be formed in the same process, the capacitor 21 can be placed at any position on the field oxide film 4, the degree of integration can be improved, and the process can be simplified. It is now simplified,
It is possible to manufacture it easily.

In this embodiment, the semiconductor device constitutes an NTL type circuit composed of transistors and capacitors.

In addition, in the same figure, numeral 2 indicates a buried layer, 3 indicates a well region which is epitaxially grown, llc indicates a lower electrode 11b,
Base drawn polycrystalline silicon is made of the same polycrystalline silicon as the base drawn polycrystalline silicon 11a and has no base electrode formed thereon, 12 is an emitter and base isolation insulating film, and 13 is a capacitor insulating film 13a. 1 (!1m film), 14 is an intrinsic base diffusion layer, 17 is a passivation film, and 18a, 18b, and 18c are an emitter, an electrode, a base electrode, and a capacitor electrode, respectively.

Next, an example of a method for manufacturing the semiconductor device of the above embodiment will be described below based on FIGS. 2(a) to 2(i).

First, an N+ type buried layer 2 is formed in a region of a P- type silicon substrate 1 that will become the bottom of a 5EPT transistor, and an N type epitaxial layer is grown on the entire surface of the P- type silicon substrate 1.
Impurities are introduced to adjust the sheet resistance to form an N-well region, and the epitaxial layer in the inactive region is removed by photoetching to perform element isolation.

Next, a thick field insulating film 4 is formed in the inactive region,
Surface oxidation is performed to form SiO on the N'' well region 3.
After forming the two films 5, the entire surface is coated with the T1 to light films 6, the polycrystalline silicon 7, and the SjO□ film 8, and then a photoresist 20 is placed at a predetermined position (in the center) above the N-well region 3. Using this as a mask, ions of, for example, boron as a P-type impurity are implanted into the entire surface, resulting in the state shown in FIG. 2(a).

Note that the points in the figures shown from FIG. 2(a) onwards indicate the introduced impurities.

Next, the SiO2 film 8 is etched using the photoresists 1 to 20 as a mask, and the SiO2 film not masked by the photoresist 20 is removed, and the SiO2 film under the photoresist 20 is retreated inward to form a 5in2 film 8a.
After that, the photoresist 20 is removed to obtain the state shown in FIG. 2(b).

Next, using a well-known etching solution called hydrazine that selectively etches only the portion of polycrystalline silicon into which impurities (boron) have not been introduced (hereinafter referred to as non-doped polycrystalline silicon), the SiO2 film 8a is used as a mask. Etching is performed to remove the non-doped polycrystalline silicon portions not masked by the SiO□ film 8a, and then the Si◯₂ film 8a is removed to form the state shown in FIG. 2(c). Here, a non-doped polycrystalline silicon portion 7a remains under the removed Si*2 film 8a.

Next, the non-doped polycrystalline silicon portion 7a and the impurity (
Using polycrystalline silicon (hereinafter referred to as doped polycrystalline silicon) 7 as a mask, the nitride film 6
Then, the non-doped polycrystalline silicon portion 7a is etched using an etching solution called hydrazine, and then the nitride film and doped polycrystalline silicon 7 remaining under the non-doped polycrystalline silicon portion 7a are removed.
Using the mask as a mask, the Si◯2 film 5 is wet-etched to obtain the state shown in FIG. 2(d).

Next, as a P-type impurity, for example, boron is ion-implanted into the entire surface to increase the concentration of P-type impurity in the doped polycrystalline silicon 7. P+ type graph 1 on the surface of area 3
~ Form bases 9, 9, then deposit polycrystalline silicon IQ on the entire surface. Next, heat treatment is performed to diffuse the doped polycrystalline silicon 7 and the P type impurities in the P+ type graft bases 9, 9 to the polycrystalline silicon 10 side, as shown in FIG. 2(e).
The state shown in According to this diffusion step, the P-type impurity is sufficiently diffused into the flat portion of the polycrystalline silicon 10, but the P-type impurity is diffused to the portion above the nitride film remaining above the element region of the polycrystalline silicon 10. Almost no impurities are diffused.

Next, the non-doped portion of the polycrystalline silicon 10 is etched using the etching device called hydrazine, and the nitride film exposed on the surface by this etching is removed, as shown in FIG. 2(f). be in the state shown. It should be noted that if the doped polycrystalline silicon 7 and the doped polycrystalline silicon 10 formed on this side are drawn separately, the diagram will be complicated, so from FIG. Silicon 7.10 is depicted together as doped polycrystalline silicon 11.

Next, the P-type doped polycrystalline silicon 11 is patterned using one mask, and the lower electrode 11 of the capacitor 21 is patterned. , b, 5EPT type transistor's base-drawing polycrystalline silicon lla and base-drawing polycrystalline silicon 11c on which no base electrode is formed are simultaneously formed, and the second
The state is as shown in Figure (g).

Next, by a partial oxidation process of the base-drawing polycrystalline silicon lla, 11c, an N edge film 12 for emitter and base separation is formed on the upper surface of the region other than the region where the emitter diffusion layer 15 will be formed, and then this Opening the upper part of the lower electrode 11b of the emitter/base isolation insulating film 12,
Thereafter, an insulating film 13 is formed on the entire surface to obtain the state shown in FIG. 2(h).

Next, the emitter portion polycrystalline silicon 16 of the insulating film 13 is
The portion where a is to be formed is removed, and then the insulating film is removed to expose the Sin.

After the film 5 is etched to expose the N-well region 3, polycrystalline silicon is deposited over the entire surface. Then, as a P-type impurity, for example, boron is implanted into the entire surface and thermally diffused to form a P-intrinsic base diffusion layer 14 in the N'' well region 3. Next, as an N-type impurity, for example, arsenic is implanted into the entire surface and thermally diffused. Diffusion is performed to form N+ on the surface of N-well region 3.
An emitter diffusion layer 15 is formed. Due to the introduction of impurities and thermal diffusion, the polycrystalline silicon deposited on the entire surface becomes N type. After that, this N-type doped polycrystalline silicon is patterned using a mask to form capacitor 2.
Upper electrode 1 on capacitor insulating film 13a constituting 1
6b, polycrystalline silicon 16a for the emitter electrode of the 5EPT type 1-transistor is simultaneously formed to obtain the state shown in FIG. 2(i).

Next, a passivation film 17 as a protective film is deposited on the entire surface, and then contact holes are opened to form an emitter electrode 18a, a base electrode 18b, and a capacitor electrode 18c, respectively, to obtain the semiconductor device shown in FIG. It will be done.

As described above, in the semiconductor device of the above embodiment, the lower electrode 11b of the capacitor 21 is formed of the same polycrystalline silicon as the base lead polycrystalline silicon 1], and the upper electrode 16b of the capacitor 21 is formed of the emitter polycrystalline silicon. Since the silicon 16a is made of the same polycrystalline silicon, as described above, the lower electrode 11b and the base lead polycrystalline silicon lla are formed in the same process, and the upper electrode 16b and the emitter polycrystalline silicon 16a are formed in the same process. This simplifies the process.

Incidentally, in the above process, 1M for the capacitor! A
In order to form the rim film 13a, the insulating film 13 is formed on the entire surface of the emitter and penis separating insulating film 12.
It is also possible to form the capacitor insulating film 13a by oxidizing or nitriding the exposed portion of the lower electrode (polycrystalline silicon) 11b. In this case, there is no need for a subsequent process of removing the portion of the insulating film 13 where the emitter polycrystalline silicon 1.6a will be formed.
Furthermore, the process can be simplified.

Note that in FIGS. 1 and 2 (g) to (1), the nitride film 6 is omitted to avoid complicating the drawings.

According to the semiconductor device configured in this way, the following effects can be obtained.

That is, the capacitor 21 is disposed on the field oxide film 4, the lower electrode 11b of the capacitor 21 is formed of the same polycrystalline silicon as the base-drawing polycrystalline silicon lla of the bipolar 1-transistor, and the upper electrode of the capacitor 21 is Since the capacitor 16b is made of the same polycrystalline silicon as the emitter polycrystalline silicon 16a of the bipolar transistor, electrical continuity between the capacitor 21 and the diffusion layers of other circuit elements formed on the surface of the substrate 1 can be interrupted. Due to the fact that there is no need to consider this, the capacitor 21 can be placed at any position on the field oxide film 4, and the base drawing polycrystalline silicon l
la and the lower electrode 11b of the capacitor 21, and the emitter polycrystalline silicon 16a and the upper electrode 1 of the capacitor 21.
6b can be formed in the same process, the process can be simplified, the degree of integration can be improved, and manufacturing can be simplified.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, although the semiconductor device of the above embodiment constitutes an NTL type circuit, it is also applicable to a semiconductor device constituting a VTL type circuit, an SPL type circuit, etc. that require a capacitor.

In the above embodiment, both the emitter diffusion layer 15 and the base diffusion M9 are made of polycrystalline silicon 1 doped with impurities.
Although only an example of application to a 5EPT type transistor, which is drawn out at 6a and lla, is described,
This embodiment can be similarly applied to transistors using GST (Gate Self Line Technology) technology and 5ICO8 (Side Double Base Contacts 1 to Structure) type 1-transistors; in short, the emitter diffusion layer The present invention is applicable to all bipolar transistors in which both the base diffusion layers are made of polycrystalline silicon doped with impurities, that is, the emitter and base are self-aligned.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a semiconductor device including a bipolar transistor in which both an emitter diffusion layer and a base diffusion layer are drawn out using polycrystalline silicon, and a capacitor configured such that an insulating film is sandwiched between upper and lower electrodes, the capacitor is formed on a field oxide film. The lower electrode of this capacitor is formed of the same polycrystalline silicon as the base-drawing polycrystalline silicon of the bipolar transistor 1 to the transistor, and the upper electrode of this capacitor is
Since the emitter of the transistor is made of the same polycrystalline silicon as the polycrystalline silicon, there is no need to consider cutting off electrical continuity between the capacitor and the diffusion layer of other circuit elements formed on the substrate surface. At the same time, it becomes possible to form the base polycrystalline silicon and the lower electrode of the capacitor, and the emitter polycrystalline silicon and the upper electrode of the capacitor in the same process. As a result, the capacitor can be placed anywhere on the field oxide film, improving the degree of integration.
The process is simplified and it becomes possible to manufacture easily.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view of an embodiment of a semiconductor device according to the present invention. FIGS. 2(a) to 2(i) are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment. 4...Field oxide film, 9...Base diffusion layer, 11a...Base extraction polycrystalline silicon, 11b
...Lower electrode, 13a...Insulating film, 15...
- Emitter diffusion layer, 16a... Emitter portion polycrystalline silicon, 16b... Upper electrode, 21... Capacitor. permission

Claims (1)

[Claims] 1. A semiconductor device including a bipolar transistor in which both an emitter diffusion layer and a base diffusion layer are made of polycrystalline silicon, and a capacitor configured such that an insulating film is sandwiched between upper and lower electrodes, The capacitor is disposed on the field oxide film, the lower electrode of the capacitor is formed of the same polycrystalline silicon as the base leading polycrystalline silicon of the bipolar transistor, and the upper electrode of the capacitor is formed on the emitter part of the bipolar transistor. A semiconductor device characterized in that it is formed of polycrystalline silicon, which is the same as polycrystalline silicon. 2. The semiconductor device according to claim 1, wherein the bipolar transistor is a self-aligned transistor in which an emitter and a base are separated in a self-aligned manner. 3. The semiconductor device is NTL, VTL or S
3. The semiconductor device according to claim 1, wherein the semiconductor device constitutes a PL type circuit.