JPH1012754A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the manufacture process of the semiconductor device constituted by providing a bipolar transistor, a MIS transistor, a capacity element, etc., on the same semiconductor substrate. SOLUTION: After collectors 101 and 102 and a base 103 are formed in a first area 100 of the semiconductor substrate 40, a capacity dielectric film 305 is formed on the semiconductor substrate 40 in a 3rd area 300. An infer-layer insulating film 44 which has an opening above a second area 200 is formed on the semiconductor substrate 40 and a gate insulating film 202 is formed on an exposed surface of the semiconductor substrate 40. The center part of a base 103 and the infer-layer insulating film 44 on the 3rd area 300 are removed after a polysilicon film 45 is formed on the semiconductor substrate 40, the polysilicon film 45, infer-layer insulating film 44, and gate insulating film 202 are patterned to form an emitter electrode 104 in the first area 100, a gate electrode 203 in the second area 200, and an upper electrode 306 on the capacity dielectric film 305 in the third area 300. Then impurities for forming a source and a drain are injected into the second area 200 and an emitter is formed by impurity diffusion from an emitter electrode 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a bipolar transistor, an MIS transistor, and a capacitor on the same substrate.

[0002]

2. Description of the Related Art In recent years, with the advancement of functions and miniaturization of semiconductor devices, there is a tendency that a plurality of different elements are provided on the same semiconductor substrate. FIG. 5 shows a bipolar transistor 50 and a MIS transistor 6 on the same semiconductor substrate 80.
FIG. 2 is a diagram showing an example of a semiconductor device 5 provided with 0 and a capacitance element 70. In the semiconductor device 5, the bipolar transistor 50 has a conventional structure,
Each electrode 82 provided on each element is formed of a metal such as aluminum. However, the gate electrode 601 of the MIS transistor 60 is made of polysilicon.

In forming the semiconductor device 5, after forming the emitter 501 of the bipolar transistor 50 by ion implantation, a contact hole reaching the emitter 501 is formed in the interlayer insulating film 401 provided on the upper surface of the semiconductor substrate 80. Thus, an emitter electrode 502 (82) and another electrode 82 made of aluminum are provided. For this reason, it is necessary to increase the formation area of the emitter 501 in consideration of misalignment at the time of forming a contact hole, and this is a factor that hinders a reduction in the element area and an improvement in the degree of integration in the semiconductor device 5. I have. In the capacitance element 70 of the semiconductor device 5, the capacitance dielectric film 7
01 has a defect such as a pinhole, the upper electrode 702 is formed through this pinhole during the subsequent heat treatment.
The aluminum of (82) may reach the semiconductor substrate 80 constituting the lower electrode, and the upper electrode 702 and the lower electrode (semiconductor substrate 80) may be short-circuited.

Therefore, in a semiconductor device requiring a high degree of integration and high reliability, a bipolar transistor 50a having a polysilicon structure and an upper electrode 702a made of polysilicon are used as in a semiconductor device 5a shown in FIG. The provided capacitive element 70a is used. The bipolar transistor 50a having the polysilicon structure has an emitter electrode 502a made of polysilicon.
The emitter 501a on the surface layer of the semiconductor substrate 80 is formed by the solid phase diffusion from the emitter electrode 502a. Therefore, there is no need to provide a margin for aligning the emitter electrode 502a with the emitter 501a, and the element area is reduced. Further, in the capacitive element 70a in which the upper electrode 702a is formed of polysilicon, the stability of the upper electrode 702a with respect to the heat treatment can be obtained. For this reason, even if a heat treatment step is performed after the formation of the upper electrode 702a, the upper electrode 7
02a and the lower electrode (semiconductor substrate 80) are prevented from being short-circuited.

When the semiconductor device 5a is formed, the following is performed. First, the gate electrode 60 is provided on the surface side of the semiconductor substrate 80 separated by the separation region 83.
1, a collector 503 and a base 504 of the bipolar transistor 50a, and a lower electrode diffusion layer 703 of the capacitor 70a. Next, an interlayer insulating film 81 is formed on the semiconductor substrate 80, and a contact hole for forming an electrode is formed in the interlayer insulating film 81. At this time, the capacitive dielectric film 701 of the capacitive element 70a
A contact hole is also formed in the formation part. Thereafter, the capacitor dielectric film 701 of the capacitor element 70a is patterned, and then the polysilicon film formed so as to cover the capacitor dielectric film 701 and the interlayer insulating film 81 is patterned, thereby forming the emitter electrode 5 of the bipolar transistor 50a.
02a, and the upper electrode 702a of the capacitance element 70a made of the polysilicon film. After the above, another electrode 82 made of aluminum is formed to complete the semiconductor device 5a.

[0006]

However, in the above method of manufacturing a semiconductor device, the emitter electrode of the bipolar transistor and the upper electrode of the capacitor are formed after the MIS transistor is formed. The step of forming the gate electrode of the MIS transistor is performed separately from the step of forming the emitter electrode and the upper electrode similarly formed of a polysilicon film. For this reason, there is a problem that the manufacturing process of the semiconductor device is complicated.

[0007]

The present invention for solving the above-mentioned problems is a method of manufacturing a semiconductor device having a bipolar transistor and a MIS transistor provided on the same semiconductor substrate, and is performed by the following procedure. In the first step, a base is formed on the surface side of the first region where the collector is formed in the semiconductor substrate, and in the second step, an interlayer insulating film having an opening is formed on the second region of the semiconductor substrate. Forming a gate insulating film on the surface of the semiconductor substrate in the region; In a third step, after removing the interlayer insulating film on the central portion of the base, in a fourth step, the polysilicon film formed on the semiconductor substrate is patterned to form an emitter electrode reaching the base in the first region. Is formed, and a gate electrode is formed in the second region. Thereafter, in a fifth step, impurities for forming a source and a drain are introduced into the surface side of the semiconductor substrate in the second region. In a sixth step, impurities are diffused from the emitter electrode to the surface layer of the base by heat treatment. The emitter of the bipolar transistor is formed.

According to the method of manufacturing a semiconductor device, the same polysilicon film is patterned to form the emitter electrode of the bipolar transistor and the gate electrode of the MIS transistor, and thereafter, the impurity is diffused from the emitter electrode to form the bipolar transistor. Are formed. For this reason, the bipolar transistor has a polysilicon structure in which the required area of the emitter is small. In the manufacture of the semiconductor device provided with the bipolar transistor and the MIS transistor, the polysilicon film forming step and the patterning step are performed once each.

In the case of forming a semiconductor device in which a capacitor is further provided on the same semiconductor substrate as described above,
Before or after forming the base in the first region of the semiconductor substrate on which the collector has been formed in the first step, a capacitive dielectric film is formed in the third region of the semiconductor substrate;
In the process, the capacitor dielectric film is formed in the same manner as the gate insulating film. Then, in the fourth step, an upper electrode is formed on the capacitor dielectric film together with the emitter electrode and the gate electrode.

According to the method of manufacturing a semiconductor device, an upper electrode on a capacitor dielectric film in a capacitor is formed together with the emitter electrode and the gate electrode by patterning the same polysilicon film. Therefore, in the manufacture of the semiconductor device, the polysilicon film forming step and the patterning step are performed once each.

Further, after performing the heat treatment of the sixth step in each of the above-described manufacturing methods, the exposed surface layers of the emitter electrode, the gate electrode, the base, the source and the drain may be silicided. When the exposed surfaces are silicided, the silicide lowers the resistance of the exposed surface.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in each embodiment of the present invention,
Bipolar transistors and M on the same semiconductor substrate
The description will be made by taking an example in which an IS transistor and a capacitor are formed. Here, N is added to the first region of the semiconductor substrate.
A PN-type bipolar transistor is formed, and a P-channel MIS transistor is formed in the second region.
A capacitor is formed in the region. Note that the bipolar transistor and the MIS transistor may be of a conductivity type opposite to that described above or may be of two types.
Further, the patterning of each layer in each of the following embodiments is performed, for example, by etching using a resist pattern formed by a lithography technique as a mask, and description thereof is omitted.

(First Embodiment) FIGS. 1 and 2 are manufacturing process diagrams showing a manufacturing method according to a first embodiment. The manufacturing method according to the first embodiment will be described with reference to these drawings. First, as shown in FIG. 1A, a semiconductor substrate 40 for forming the above-mentioned semiconductor device is made of single-crystal silicon and an epitaxial layer of N-type silicon formed on the upper surface thereof. This epitaxial layer serves as a collector of the bipolar transistor, and its surface side (the surface side of the semiconductor substrate 40) is separated by a separation region 41 such as a LOCOS oxide film into a first region 100, a second region 200, and a third region. It is separated into an area 300. Also, the first area 1
A separation region 41 for separating the collector take-out portion and the base is also arranged on the front surface side of the semiconductor substrate 40 in the region 00, and also separates the upper electrode and the lower electrode on the surface side of the semiconductor substrate 40 in the third region 300. An isolation region 41 is provided. Then, the first area 100 and the second area 20
An isolation 42 is formed below the isolation region 41 between the zero and third regions 300. Also, the first area 100
The N-type buried collector 101 is formed in the semiconductor substrate 40 in the second region 200 and the third region 300.
An N-type separation / diffusion layer (buried region layer) 201.301 is formed in the semiconductor substrate 40 therein.

Then, an N-type collector extraction portion 102 is formed on the surface side of the first region 100 in the semiconductor substrate 40 formed as described above. The collector extraction portion 102 is provided on one of the front surfaces of the semiconductor substrate 40 separated by the separation region 41 in the first region 100. Thereafter, a silicon oxide film 43 having a thickness of about 10 to 30 nm is formed on the surface of the semiconductor substrate 40 by, for example, a thermal oxidation method. Next, a resist pattern (not shown) having an opening in a region on the front surface side of the semiconductor substrate 40 separated by the separation region 41 in the first region 100 where the collector extraction portion 102 is not provided is formed. Then, an impurity for forming the base 103 of the bipolar transistor is introduced into the surface side of the semiconductor substrate 40 by ion implantation using this as a mask. This ion implantation is performed, for example, by using boron ions (B ⁺ ) as P-type impurities in an amount of 30 to 50.
At an implantation energy of keV, 10 ¹⁴ -10 ¹⁶ / cm ²
Just to introduce. Thereafter, the resist pattern is removed, and then heat treatment (for example, 90 minutes in a nitrogen atmosphere) is performed.
(0 ° C. for 30 minutes) to activate the impurities.

After performing the above steps in the same manner as before,
In the third region 300, the silicon oxide film 43 in one region separated by the separation region 41 is removed. Next, an insulating film such as a silicon nitride film is formed on the semiconductor substrate 40, and the insulating film is patterned to form a capacitive dielectric film 305 made of the insulating film in the third region 300 on the semiconductor substrate 40. . This capacitor dielectric film 305
Is formed with an appropriate thickness depending on the capacitance required for the capacitor. In this step, the silicon oxide film 43 serves as an etching stopper at the time of the above patterning and also serves as a protective film for the semiconductor substrate 40. The step of forming the capacitor dielectric film 305 may be performed after forming the silicon oxide film 43 and before forming the base 103 in the first region 100.

Next, as shown in FIG. 1B, an interlayer insulating film 44 made of silicon oxide is formed on the semiconductor substrate 40 by the CVD method. Next, the interlayer insulating film 44 on the semiconductor substrate 40 on the second region 200 is removed, and the surface of the semiconductor substrate 40 on the second region 200 is exposed. Thereafter, silicon oxide is generated on the surface of the semiconductor substrate 40 in the second region 200 by, for example, a thermal oxidation method, and a gate insulating film 202 made of the silicon oxide is formed. The thickness of the gate insulating film 202 is about 10 to 30 nm.

Next, as shown in FIG. 1 (3), the interlayer insulating film 44 is patterned to form a central portion of the base 103 in the first region 100, the semiconductor substrate 40 in the collector extraction portion 102, and a third region 300. The interlayer insulating film 44 on the semiconductor substrate 40 in the above is removed. On this occasion,
The semiconductor substrate 40 in the second region 200 is covered with a resist pattern to prevent etching damage in patterning the interlayer insulating film 44 from affecting the gate insulating film 202.

Thereafter, as shown in FIG. 1D, a polysilicon film 45 is formed on the semiconductor substrate 40 so as to cover the interlayer insulating film 44, the gate insulating film 202, and the capacitor dielectric film 305. Next, N-type impurities are introduced into the polysilicon film 45 by ion implantation. Here, for example, arsenic (As) ions are used as N-type impurities at 40 to 60 nm.
A dose of about 10 ¹⁵ to 10 ¹⁶ / cm ^{2 is} introduced with an implantation energy of keV. Incidentally, the introduction of impurities into the polysilicon film 45 may be solid-phase diffusion from an oxide film containing impurities.

Next, a silicon oxide film 46 is formed on the polysilicon film 45 by the CVD method. After that, the silicon oxide film 46, the polysilicon film 45, and the interlayer insulating film 44
By patterning the gate insulating film 202, an emitter electrode 104 reaching the central portion of the base 103 and a collector electrode 105 reaching the collector take-out portion 102 are formed in the first region 100 on the semiconductor substrate 40, and the second region 200 is formed. A gate electrode 203 is formed, an upper electrode 306 is formed on the capacitive dielectric film 305 in the third region 300, and a lower electrode 307 is formed on the exposed surface of the semiconductor substrate 40 in the third region 300. In the above patterning, the surface portion of the base 103 is exposed. As described above, the same polysilicon film 4
5 are etched in the same step.
4, 105, 203, 306.307 are formed.

Next, as shown in FIG. 2 (5), the base 1 of the first region 100 is ion-implanted using the electrodes 104, 105, 203, 306.307 as masks.
03 is formed on the surface side of the semiconductor substrate 40 in the second region 200 and the source 20
4 and a P-type impurity for forming the drain 205 are introduced. Here, for example, boron difluoride ions (BF ₂ ⁺ ) are introduced as P-type impurities at a dose of about 50 to 70 keV and about 10 ¹⁵ to 10 ¹⁶ ions / cm ² .

Thereafter, a silicon nitride film (not shown) is formed on the semiconductor substrate 40 to a thickness of about 50 to 100 nm. After that, a heat treatment (for example, at 900 ° C. for 30 minutes) is performed to activate the impurities in the semiconductor substrate 40 and to remove the base 10 from the emitter electrode 104.
Solid-phase diffusion of N-type impurities into the surface layer of
7, a low-resistance layer 108 is formed by solid-phase diffusion of an N-type impurity from the collector electrode 105 to the surface layer of the collector extraction portion 102, and the semiconductor substrate 40 is formed from the lower electrode 307.
Solid-phase diffusion of an N-type impurity on the surface layer of
To form Thereafter, the entire surface of the silicon nitride film is etched back by anisotropic etching to form an emitter electrode 10.
4. On the side walls of the collector electrode 105, the gate electrode 203, the upper electrode 306, and the lower electrode 307, a sidewall 47 made of the silicon nitride film is formed.

Next, as shown in FIG. 2 (6), after removing the silicon oxide film (18) on each of the electrodes 104, 105, 203, 306.307, the semiconductor substrate is subjected to, for example, a self-aligned silicide method. Electrodes 104, 105, 203, and 30 made of 40 and polysilicon film 45
The silicide film 48 is formed on the exposed surface layer of 6.307. The self-aligned silicide method is performed as follows. First, each of the electrodes 104, 105, 203, 30
After forming a high melting point metal film such as tungsten in a state covering 6.307, a heat treatment (for example, Rapid Ther
mal Anneal: RTA at 1000 ° C. for 10 seconds to selectively generate high-melting-point metal silicide at the contact portion between the high-melting-point metal film and silicon (semiconductor substrate 40 and polysilicon film 45), thereby forming a silicide film. Set to 48. After the silicide film 48 is formed, the remaining high melting point metal film is selectively removed by etching.

As described above, the bipolar transistor 10 having the polysilicon structure and the MIS
(MOS) transistor 20 and MIS type capacitive element 30
Is formed to form the semiconductor device 1.

The bipolar transistor 10 of the semiconductor device 1 thus formed has a so-called poly-washed structure in which the emitter 107 is formed by impurity diffusion from the emitter electrode 104.
7 can be reduced to achieve high integration of the semiconductor device 1. Further, the capacitive element 30 includes an upper electrode 306
Is made of polysilicon, the upper electrode 306 is kept in a thermally stable state even if a heat treatment is performed after the above manufacturing process, and the high reliability of the semiconductor device 1 is maintained.

Further, in the semiconductor device 1 described above, each of the electrodes 104, 105, 203, 306.307 and the base 1
03, the exposed surface layers of the source 204 and the drain 205 are silicided, so that the resistance of the exposed surface portion can be reduced.

In the above manufacturing method, the same polysilicon film 45 is patterned to form the emitter electrode 104 of the bipolar transistor 10, the gate electrode 203 of the MIS transistor 20, and the upper electrode 306 of the capacitor 30. Therefore, in the manufacturing process of the semiconductor device 1 having the above-described effects, the polysilicon film forming process and the patterning process can be reduced to one each.

(Second Embodiment) FIGS. 3 and 4 are manufacturing process diagrams showing a manufacturing method according to a second embodiment. The manufacturing method according to the second embodiment will be described with reference to these drawings. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description of the same steps as those in the first embodiment will be omitted. The difference between the second embodiment and the first embodiment resides in that the capacitance element is formed of a MOS type, as described below.

First, as shown in FIG. 3A, a semiconductor substrate 40 on which a semiconductor device is formed has the same configuration as that of the first embodiment. On the front side, a collector take-out part 102 is formed in the same manner as described with reference to FIG.
Thereafter, a silicon oxide film 43 having a thickness of about 10 to 30 nm is formed on the semiconductor substrate 40, and then a base 103 of the bipolar transistor is formed on the surface side of the semiconductor substrate 40 in the first region 100. The above steps are performed in the same manner as in the first embodiment.

Next, as shown in FIG. 3B, an interlayer insulating film 44 made of silicon oxide is formed on the semiconductor substrate 40 so as to cover the silicon oxide film (43).
The portion of the interlayer insulating film 44 on the upper electrode formation region of the third region 300 and the upper region 00 is removed. At this time, the silicon oxide film (43) is also removed at the same time, and the surface of the semiconductor substrate 40 is exposed in the second region 200 and the third region 300. Next, silicon oxide having a thickness of about 10 to 30 nm is generated on the exposed surface of the semiconductor substrate 40 by, for example, thermal oxidation, and a gate insulating film 202 made of the silicon oxide is formed in the second region 200 and the third region 30 is formed.
Then, a capacitor dielectric film 301a made of the silicon oxide is formed at 0.

Next, the steps shown in FIGS. 3 (3) and 3 (4) are performed in the same manner as described with reference to FIGS. 1 (3) and 1 (4) in the first embodiment. Thereby, the semiconductor substrate 40
, An emitter electrode 104, a collector electrode 105, a gate electrode 203, and an upper electrode 306 made of the same polysilicon film.
And a lower electrode 307 are formed.

Thereafter, the step shown in FIG. 4 (5) is performed in the same manner as described in the first embodiment with reference to FIG. 2 (5). Thus, the emitter 107 and the graft base 106 of the bipolar transistor and the source 204 and the drain 205 of the MIS transistor are formed. Also,
Side walls 47 are formed on the side walls of the electrodes 104, 105, 203, 306, and 307.

Next, the step shown in FIG.
This is performed in the same manner as described with reference to FIG.
Thereby, the emitter electrode 104 and the collector electrode 10
5, gate electrode 203, upper electrode 306, lower electrode 30
7. A silicide film 48 is formed on the surface layers of the graft base 103, the source 204 and the drain 205.

As described above, the bipolar transistor 10 having the polysilicon structure and the MIS
(MOS) Transistor 20 and MOS-type capacitive element 30
a to form a semiconductor device 1a.

The semiconductor device 1a has the same effect as that of the first embodiment. In the above manufacturing method, the gate insulating film 202 of the MIS transistor 20 and the capacitive dielectric film 305a of the capacitive element 30 are formed in the same step, and the manufacturing steps of the gate insulating film 202 and the capacitive dielectric film 305a are individually performed. No need. Therefore, the number of manufacturing steps of the semiconductor device is further reduced as compared with the method of the first embodiment.

In each of the above embodiments, impurities are introduced for forming a graft base by ion implantation. However, when the silicide film 48 is formed, the resistance of the surface of the base 103 is reduced by the silicide film 48. Therefore, it is not necessary to particularly form the graft base, and the manufacturing steps of the semiconductor device can be further reduced. . Further, the emitter electrode 104 and the lower electrode 30
7 does not necessarily need to be formed of a polysilicon film.
When the emitter electrode 104 and the lower electrode 307 are not formed of a polysilicon film, a silicide film is also formed on the collector extraction portion 102 in the first region 100 and the exposed surface layer of the semiconductor substrate 40 in the third region 300.
This silicide film reduces the contact resistance between the emitter and the lower electrode (semiconductor substrate 80).

[0036]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the same polysilicon film is patterned to form an emitter electrode of a bipolar transistor, a gate electrode of a MIS transistor, and a capacitor element. An electrode is formed, and then the emitter of the bipolar transistor is formed by impurity diffusion from the emitter electrode. From this, the bipolar transistor having the polysilicon structure and the MIS are formed on the same semiconductor substrate.
In the manufacture of a semiconductor device provided with a transistor and a semiconductor device provided with a capacitor on this semiconductor substrate, it is possible to reduce the film forming process and the patterning process of the polysilicon forming the electrode each one time. become. Therefore, the manufacturing process of the semiconductor device can be simplified. In addition, the emitter electrode, the gate electrode, and the upper electrode are formed, and after forming a diffusion layer on the semiconductor substrate, the exposed surfaces of the semiconductor substrate and the electrodes are silicided to reduce the connection resistance in the semiconductor device. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional process view (1) showing a first embodiment of the present invention.

FIG. 2 is a sectional process view (part 2) showing the first embodiment of the present invention.

FIG. 3 is a sectional process view (1) showing a second embodiment of the present invention.

FIG. 4 is a sectional process view (part 2) showing the second embodiment of the present invention.

FIG. 5 is a sectional view of a conventional semiconductor device.

FIG. 6 is a sectional view of another conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 1a Semiconductor device 10 Bipolar transistor 20 MIS transistor 30, 30a Capacitance element 40 Semiconductor substrate 41 Isolation region 45 Polysilicon film 48 Silicide film 100 First region 101 Embedded collector 102 Collector extraction part 103 Base 1
04 Emitter electrode 107 Emitter 200 Second region 203 Gate electrode 204 Source 205 Drain 300 Third
Region 305, 305a Capacitive dielectric film 306 Upper electrode

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device comprising a bipolar transistor and a MIS transistor provided on a same semiconductor substrate, wherein a front surface is separated into a first region and a second region by an isolation region, and A first step of forming a semiconductor substrate provided with a collector of the bipolar transistor in one region, and forming a base of the bipolar transistor on a front surface side of the semiconductor substrate in the first region; and an opening on the second region. Forming a gate insulating film on an exposed surface of the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, and removing the interlayer insulating film on a central portion of the base. Forming a polysilicon film on the semiconductor substrate so as to cover the interlayer insulating film and the gate insulating film; A fourth step of forming an emitter electrode reaching the base in the first region and forming a gate electrode in the second region by patterning the interlayer insulating film and the gate insulating film; and masking the gate electrode. A fifth step of introducing an impurity for forming a source and a drain on the surface side of the semiconductor substrate in the second region, and diffusing the impurity from the emitter electrode to the surface layer of the base by heat treatment. A method of forming an emitter of the bipolar transistor and activating an impurity in the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate is made of silicon, and after said sixth step, each of said emitter electrode, gate electrode, base, source and drain is exposed. Performing a seventh step of silicidizing the surface layer. 3. A method of manufacturing a semiconductor device comprising a bipolar transistor, an MIS transistor, and a capacitor provided on a same semiconductor substrate, wherein the first side, the second side, and the third side are separated by an isolation region on a surface side.
After forming a semiconductor substrate which is separated into regions and the collector of the bipolar transistor is provided in the first region, the base of the bipolar transistor is formed on the surface side of the semiconductor substrate in the first region, and the third substrate is formed.
Forming a capacitive dielectric film on a semiconductor substrate in a region
Forming an interlayer insulating film having an opening on the second region on the semiconductor substrate, and forming a gate insulating film on an exposed surface of the semiconductor substrate; A third step of removing the interlayer insulating film on the third region; and forming a polysilicon film on the semiconductor substrate so as to cover the interlayer insulating film, the gate insulating film, and the capacitor dielectric film.
By patterning the polysilicon film, the interlayer insulating film, the gate insulating film and the like, an emitter electrode reaching the base is formed in the first region, a gate electrode is formed in the second region, and a gate electrode is formed in the second region. A fourth step of forming an upper electrode on the capacitor dielectric film, and a fifth step of introducing impurities for forming a source and a drain on the surface side of the semiconductor substrate in the second region using the gate electrode as a mask Performing a sixth step of diffusing impurities from the emitter electrode into the surface layer of the base by heat treatment to form an emitter of the bipolar transistor and activating impurities in the semiconductor substrate. Manufacturing method of a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 3, wherein said semiconductor substrate is made of silicon, and after said sixth step, said emitter electrode, gate electrode, upper electrode, base, source and drain. Performing a seventh step of silicidizing each exposed surface layer. 5. A method of manufacturing a semiconductor device comprising a bipolar transistor, an MIS transistor, and a capacitor provided on the same semiconductor substrate, wherein the first side, the second side, and the third side are separated by an isolation region on a surface side.
A first step of forming a semiconductor substrate that is separated into regions and provided with the collector of the bipolar transistor in the first region, and then forming a base of the bipolar transistor on the surface side of the semiconductor substrate in the first region; Forming an interlayer insulating film having an opening on the second region and the third region on the semiconductor substrate, and forming a gate insulating film and the same material as the gate insulating film in a second region on an exposed surface of the semiconductor substrate; A second step of forming a capacitive dielectric film of: a third step of removing the interlayer insulating film on a central portion of the base and on the third region; and removing the interlayer insulating film, the gate insulating film, and the capacitive dielectric film. After forming a polysilicon film on the semiconductor substrate in a covering state,
By patterning the polysilicon film, the interlayer insulating film, the gate insulating film and the like, an emitter electrode reaching the base is formed in the first region, a gate electrode is formed in the second region, and a gate electrode is formed in the second region. A fourth step of forming an upper electrode on the capacitor dielectric film, and a fifth step of introducing impurities for forming a source and a drain on the surface side of the semiconductor substrate in the second region using the gate electrode as a mask Performing a sixth step of diffusing impurities from the emitter electrode into the surface layer of the base by heat treatment to form an emitter of the bipolar transistor and activating impurities in the semiconductor substrate. Manufacturing method of a semiconductor device. 6. The method according to claim 3, wherein the semiconductor substrate is made of silicon, and after the sixth step, the emitter electrode, the gate electrode, the upper electrode, the base, the source, and the drain. Performing a seventh step of silicidizing the exposed surface layer of the semiconductor device.