JPH0228380A - Manufacture of semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To seek to improve the controllability of the thickness of the first gate insulating film by thermally oxidizing the first insulating film of a memory cell part, and then thermally nitriding it so as to form. CONSTITUTION:Phosphor is implanted into a P-type Si substrate 1, an n-well region 2 is formed, a field oxide film 3 is formed, and the first gate insulating film 4 is formed in 400Angstrom by dry oxidation, for example, at an oxidation temperature of 1000 deg.C at a memory cell part, and then it is formed by being annealed in the ammonium atmosphere for one hour, for example, at a nitrizing temperature of 900 deg.C. The thickness of the thermally nitrized oxide film formed at this time is 400Angstrom . Hereafter, the first gate insulating film 4 only at a peripheral circuit is etched so as to form the second gate oxide film 5 of 300Angstrom at the peripheral circuit by dry oxidation, for example, at an oxidation temperature of 1000 deg.C. At this time, the thickness of the first gate insulating film is 405Angstrom . Hereby, even if it goes through the process to form the second gate insulating film 5 of the peripheral circuit by thermal oxidation, the thickness of the first gate insulating film 4 is not increased, thus the controllability of the thickness of the first gate insulating film 4 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a method of manufacturing a floating gate type semiconductor nonvolatile memory that can be easily electrically written and erased.

[Summary of the Invention 1 This invention is a method for manufacturing a floating gate type semiconductor nonvolatile memory that can be easily electrically written and erased, in which a first gate insulating film in a memory cell portion is formed by thermal oxidation and then thermal nitridation. This provides a highly reliable semiconductor nonvolatile memory in which the thickness of the first gate insulating film is highly controllable even after the next step of thermally oxidizing and forming the second gate insulating film of the peripheral circuit. .

[Prior art] Figures 3(a) to 3(d) show a conventional semiconductor nonvolatile memory (
Hereinafter, it will be referred to as EEPROM. ) is a cross-sectional view showing the order of manufacturing steps of the peripheral circuit. Figure 4 (a) to (d)
1 is a cross-sectional view showing the order of manufacturing steps of a memory cell portion of a conventional EEPROM.

Using a P-type Si substrate 101, phosphorus is implanted into the P-type Si substrate 101, an n-well region 102 is formed, a field oxide film 103 is formed, and a first gate oxide film 104 is thermally oxidized in the memory cell area. Form. [Figure 3(a), 4th
Figure (a)] After this, first gate oxidation III is applied only to the peripheral circuits.
104 is etched, and a second gate oxide film 105 of the peripheral circuit is thermally oxidized. [Figure 3 (b), Figure 4 (
b)] Next, an n-type tunnel region 106 and an n-type control gate region 107 in the memory cell section are formed, and a tunnel insulator 1 is formed in that part.
A thin oxide 1*tog is formed with I1108, a polycrystalline silicon layer is formed, and the polycrystalline silicon layer is made into an N'' type by a phosphorus diffusion method to form a floating gate electrode 110.At this time, in the peripheral circuit, , form the gate electrode 1.10 of the MOS transistor. [Figure 3 (C), Figure 4 (C
)] Boron is implanted to form the source 11 of the P-channel transistor.
1 and a drain 112 are formed, and arsenic is implanted to form a source 113 and a drain 114 of an n-channel transistor. [Fig. 3(d), Fig. 4(d)] [Problems to be Solved by the Invention] The first gate oxide film 104 in the memory cell portion is added when forming the second gate oxide film 105 in the peripheral circuit. This has the disadvantage that it is oxidized, making it difficult to control the thickness of the first gate oxide film 104.

[Means for solving the problem 1 In order to solve the above problem, the first gate insulating film in the memory cell part is thermally oxidized and then thermally nitrided to make it an insulating film that is difficult to oxidize.
The second gate insulating film of the peripheral circuit was formed by thermal oxidation.

[Function] As mentioned above, since the first gate insulating film in the memory cell portion was thermally oxidized and then thermally nitrided to form an insulating film that is resistant to oxidation, the second gate insulating film in the peripheral circuit was formed through a process of thermal oxidation. Also, the controllability of the film thickness of the first gate insulating film was improved without increasing the film thickness of the first gate insulating film.6 [Example 1] Hereinafter, the present invention will be explained using an example. Figure 1(a)
-(d) are cross-sectional views showing the order of manufacturing steps of the peripheral circuit of one embodiment of the semiconductor nonvolatile memo of the present invention. Figure 2 (a
) to (d) are cross-sectional views showing the order of manufacturing steps of the memory cell portion of an embodiment of the EEPROM of the present invention.

Using a P-type S1 substrate 1', non-ion is implanted into the P-type Si substrate 1 to form an n-well region 2, and a field oxide film 3 is formed.
A first gate insulating film 4 is formed in the memory cell portion by, for example, dry oxidation at an oxidation temperature of 1000° C., followed by annealing for one hour in an ammonia atmosphere at a nitriding temperature of 900° C. At this time, the thickness of the thermal nitrided oxide film formed was 400 mm. [Figure 1 (a), Figure 2 (a)
)] Thereafter, only the first gate insulating film 4 of the peripheral circuit is etched, and the second gate oxide 115 of the peripheral circuit is formed by dry oxidation at an oxidation temperature of 1000 DEG C. for 300 times. At this time,
The thickness of the first gate insulating film is 405. [Figure 1(b)
, FIG. 2(b)] Next, an n-type tunnel region 6 and an n9-type control gate region 7 in the memory cell part are formed, a tunnel insulating film 8 and a thin oxide film 9 are formed in these parts, and a polycrystalline silicon layer is formed. The polycrystalline silicon layer is formed with N0 by the phosphorus diffusion method.
A mold is formed to form a floating gate electrode IO. At this time, the gate electrode 10 of the MOS transistor is formed in the peripheral circuit. [Fig. 1(C), Fig. 2(C)] Boron is implanted to form the source 11 of the P-channel transistor.
A source 13 and a drain 14 of an n-channel transistor are formed by implanting arsenic. [
FIG. 1(d), FIG. 2(d)] As mentioned above, the first gate insulating film in the memory cell portion is thermally oxidized and then thermally nitrided to make it an insulating film that is resistant to oxidation. Even through the process of thermally oxidizing the film, the thickness of the first gate insulating film was not increased, and the controllability of the thickness of the first gate insulating film was improved.

[Effect of the Invention 1] The EEPROM of the present invention has a first gate insulating film in the memory cell portion that is formed by thermal oxidation and then thermal nitridation. The present invention provides a highly reliable semiconductor nonvolatile memory in which the thickness of the first gate insulating film is highly controllable.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process order of the peripheral circuit of the semiconductor nonvolatile memory of the present invention, and FIGS. 2(a) to 2(d)
(d) is a cross-sectional view showing the manufacturing process order of the memory cell part of the EEFROM of the present invention, and FIGS.
4(a) to 4(d) are cross-sectional views showing the order of manufacturing steps of the peripheral circuit of FROM, and FIGS. 4(a) to 4(d) are sectional views showing the order of manufacturing steps of the memory cell portion of a conventional EEFROM. ■...P-type silicon substrate 4...First gate insulating film 5 consisting of thermal nitrided oxide film...Second gate oxide film and above Applicant Seiko Electronics Industries Co., Ltd. Agent Patent Attorney Keinosuke Hayashi +02 +01 +02 Figure s) +0S b) ot +01 Fig.

Claims (1)

[Claims] In a method for manufacturing a semiconductor nonvolatile memory having two types of gate insulating film thicknesses, a first gate insulating film is thermally oxidized and then thermally nitrided, and a second gate insulating film is then formed by thermal oxidation. A method for manufacturing a semiconductor nonvolatile memory, comprising the steps of: