JPH023982A - Nonvolatile storage element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an EEPROM having no scattering in the deleting characteristics, by positioning the side of a control gate back from the side of a floating gate while extending at least one of source and drain regions up to under the end of the control gate. CONSTITUTION:A floating gate electrode 3 is provided on a semiconductor substrate 1 with a first gate insulating film 2 interposed therebetween. A control electrode 5 is provided thereon with a second insulating film 4 interposed therebetween. A source region 61 and a drain region 62 are formed under the electrode 3 such that they are spaced from each other and overlap partially with the electrode 3. Then, a side wall spacer 7 is provided on the side of the electrode 5. Said electrode 3 is formed with reference to the end of the spacer 7. In this manner, the side of the electrode 5 is located back from the side of the electrode 3. Accordingly, stable tunnel current is ensured when data is deleted, and variance in deleting characteristics is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applicable to non-volatile memory elements, and furthermore to EEFROMs.
(Electrically erasable and writable read-only memory).

For example, it relates to a technique that is effective for use in flash (batch erasing type) EEPROM.

[Prior Art] As a conventional non-volatile memory element of this type, for example,
There is a floating gate type memory element as shown in the figure (Nikkei Electronics 1 published by Nikkei McGraw-Hill).
April 4, 988 issue no.

444J, pages 151-157).

The nonvolatile memory element shown in FIG. 4 is configured for use in a flash EEPROM having a one transistor/bit configuration, and is a floating memory element provided on a semiconductor substrate 1 with a first gate insulating film 2 in between. a gate electrode 3; a control gate electrode 5 provided on the floating gate electrode 3 with a second gate insulating film 4 in between; A source region 61 and a drain region 62 are formed with partial overlap.

Writing is performed by injecting hot electrons generated at the end of the drain region 62 into the floating gate electrode 3. Erasing is done using floating gate voltage t
! This is performed by tunneling the electrons which have been subjected to W[3 into the source region 61.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, there are problems such as large variations in erasing characteristics between memory elements and a relatively small number of times that data can be repeatedly replaced.

The erase characteristics largely depend on the shape of the floating gate electrode 3, especially the shape at its end 3E.

Floating gate electrode 3 and source region 61 during erasing
The electric field applied between them is over 10'V/m, but
The intensity distribution is not uniform and tends to be concentrated at the end 3E of the gate electrode 3 due to the so-called edge effect. Therefore, slight variations in the shape of the gate electrode 3 cause large variations in the erasing characteristics. Furthermore, if the applied electric field during erasing is concentrated at a specific location, the insulating film is likely to be destroyed or deteriorated at the concentrated location.

Therefore, the number of times the erase voltage is applied, that is, the number of times rewriting is repeated is limited.

Here, as a means to solve the above-mentioned problem, the present inventors have considered increasing the overlapping area between the source region and the floating gate electrode to obtain a stable tunnel area.

However, in conventional manufacturing methods, the source region and drain region are formed by self-alignment using the floating gate as a mask, so the overlapping area of the source region or drain region and the floating gate electrode is limited to a certain amount or more. It was not possible to make it larger. Self-alignment is an essential processing technology for miniaturizing memory elements.

Therefore, in order to increase the overlapping area between the source/drain region formed by self-alignment and the floating gate electrode, the present inventors increased the ion implantation concentration of the conductivity-imparting material and stretched it by heat treatment after implantation. We considered increasing the diffusion processing temperature.

However, in the source/drain regions formed as described above, the diffusion state at the overlapped portion with the floating gate electrode is easily influenced by the implant concentration, heat treatment conditions, and shape of the floating gate electrode, making it difficult to control. and lacked reproducibility. For this reason, it has not been possible to reduce the variation in erasing characteristics.

In addition, since the concentration in the area expanded by stretching diffusion is low, during the erase operation, depletion layers are likely to expand and inversion layers are formed in the low-concentration overlapping area, so that the overlapping area does not function effectively. A problem arises.

The object of the present invention is to provide excellent reproducibility and controllability.

To provide a technology that uses a process that allows microfabrication through self-alignment to reduce variations in erasing characteristics, and to increase the number of times that it can be repeatedly rewritten, thereby making it possible to create a highly reliable nonvolatile memory element. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a first electrode layer for forming a floating gate electrode and a second electrode layer for forming a control gate electrode are formed, and at least one of the source region and the drain region is covered with the control gate electrode as a mask. After forming the control gate electrode by self-alignment, a sidewall spacer is formed to laterally extend the side of the control gate electrode, and a floating gate electrode is formed by self-alignment using the sidewall spacer and the control gate electrode as a mask. That is what it is.

[Operation] According to the above-described means, the overlapping area between the source region or drain region and the floating gate can be increased while using self-alignment microfabrication technology without forcing unnecessary stretching and diffusion processing. be able to.

As a result, by using a process that has excellent reproducibility and controllability, and allows microfabrication through self-alignment, it is possible to reduce variations in erase characteristics, increase the number of times that can be repeatedly rewritten, and create highly reliable nonvolatile memory elements. enable. That purpose is achieved.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a schematic configuration of a nonvolatile memory element according to a first embodiment of the present invention.

The nonvolatile memory element shown in the figure is a flash EEPROM.
1 is a semiconductor substrate made of p-type silicon, 2 is a first gate insulating film, 3 is a floating gate electrode, 4 is a second gate insulating film, and 61 and 62 are nI type. A source region and a drain region are made of a scattering type scattering layer, 7 is a side wall spacer formed by unshaving the photoresist, and 8 is an aluminum wiring.

The nonvolatile memory element shown in the figure is a type of MIS (conductor-insulator-semiconductor) type FET (field effect transistor), and is a floating device provided on a semiconductor substrate 1 with a first gate insulating film 2 in between. A gate electrode Vi3, a control gate electrode 5 provided on the floating gate electrode 3 with a second gate insulating film 4 in between, and a control gate electrode 5 which is spaced apart from each other under the floating gate electrode 3 and is connected to the floating gate electrode 3. Source region 61 and drain region 62 formed with partial overlap
formed by etc.

Here, sidewall spacers 7 are provided on the sides of the control gate electrode 5.

The floating gate electrode 3 is formed with the end of the sidewall spacer 7 as a reference. As a result, the side portions of the control gate electrode 5 are formed to be set back from the side portions of the floating gate electrode 3.

In this way, the side portions of the control gate electrode 5 are formed to be recessed inward from the side portions of the floating gate electrode 3, and the tips of the source region 61 and the drain region 62 are respectively By reaching below the side portions, a relatively large overlapping portion is formed between the source region 61 and the drain region 62 and the floating gate electrode 3 with good reproducibility and controllability.

In this case, the dimension of the floating gate electrode 3 is 0.2 to 0.3 μm at one end part of the control gate electrode 50 due to the sidewall spacer 7.
It is set fairly large.

Regarding the film thickness, the first gate insulating film 2 has a thickness of 10 nm.
The floating gate electrode 3 and control gate electrode 5 have a thickness of about 100 to 300 nm, and the second gate insulating film 4 has a thickness of about 25 nm.

In the nonvolatile memory element configured as above, first,
Since the overlapping area between the source region 61 and the drain region 62 and the floating gate electrode 3 is securely secured, during erasing, the floating gate electrode 3
This makes it possible to avoid the influence of the shape of the side portions of the tunnel, etc., and ensure a stable tunnel current. Thereby, variations in erasing characteristics can be reduced. At the same time, the concentration of the electric field at the edge is alleviated, making it possible to increase the erasing voltage and increase the erasing speed.

Next, an example of a method for manufacturing the above-mentioned nonvolatile memory element will be described.

FIG. 2 shows the main parts of the method for manufacturing the nonvolatile memory element shown in FIG. 1 in the order of steps (A-L).

(A) On the surface of the p-type silicon semiconductor substrate 1, in the region where the P channel M and ISFET are formed,
By implanting phosphorus ions (~I x 10"/aJ) and performing bow-stretching diffusion, the n-type well region 11
form. Next, boron ions are implanted to form a channel stopper 12 using a P-type diffusion layer, and then a field insulating film 13 is formed to a thickness of about 600 nm using a known selective oxidation technique. Thereafter, a first gate insulating film 2 made of silicon dioxide is formed to a thickness of about 10 nm on a portion exposed between the field insulating films 13.

(B) To form a floating electrode, a first electrode layer 14 made of a polycrystalline silicon film is formed. This first electrode layer 14 is formed over the entire surface of the semiconductor substrate 1 by, for example, CVD.
After it is formed to a thickness of 100 to 200 nm by chemical vapor deposition, it is doped with an n-conductivity imparting substance such as phosphorus by ion implantation or the like in order to lower the resistance. Thereafter, the first electrode layer 14 is patterned using photolithography technology. At this time, patterning of the floating gate electrode is not yet performed. At this stage, a first layer is applied to the entire surface of the area including the floating gate electrode and its surrounding area, that is, the nonvolatile memory element area.
The electrode layer 14 remains.

(C) By oxidizing the semiconductor substrate 1, a second gate insulating film 4 having a thickness of about 25 nm is formed on the surface of the first electrode layer 14, and the other surface of the semiconductor substrate 1 is A third gate insulating film 15 having a thickness of about 17 nm is formed. The third gate insulating film 15 is M for peripheral circuits.
Used as a gate insulating film for ISFET. Next, a second electrode layer 16 made of a polycrystalline silicon film with a thickness of about 300 nm is formed on the gate insulating film 4.15.

Furthermore, in order to lower the resistance of the second electrode layer 16, it is doped with an n-conductivity imparting substance such as phosphorus by ion implantation or the like. After this, for example by CVD, 1
A silicon oxide film 17 having a thickness of approximately 0.00 to 200 nm is formed.

(D) The second electrode layer 16 is patterned by an etching process using a photoresist mask to form the control gate electrode 5 of the nonvolatile memory element and the gate electrode J8 of the MISFET for the peripheral circuit.

(E) M for control gate electrode 5 and peripheral circuits
Each exposed surface of the gate electrode 18 of the ISFET is thermally oxidized to form a silicon oxide film 31. Thereafter, using the resist 19 as a mask, a 10"/10"/n conductive substance such as phosphorus is applied to the source region side of the nonvolatile memory element.
By stopping the ion bombardment to about a#, an n-type diffusion layer 16 which will become a source region is formed. In this ion implantation, ions are implanted into the second gate insulating film 4. The energy is transmitted through the first electrode layer 14 and the first gate insulating film 2 and reaches the surface of the semiconductor substrate 1.

For example, if the thickness of the multi-nodule silicon film forming the first electrode layer 14 is 1100 nm, implantation is performed with an energy of about 150 keV. After this, the resist 19 is once removed.

(F) Using the newly formed resist 19 as a mask,
A p-type diffusion layer 20 is formed in a portion that will become the drain region by ion-implanting a p-conductivity imparting substance such as boron to about 1011 to 10147 aJ on the drain region side of the nonvolatile memory element. The ion implantation at this time also uses such energy that the ions pass through the second gate insulating film 4, the first electrode layer 14, and the first gate insulating film 2 and reach the surface of the semiconductor substrate 1. Let's do it.

The implantation energy in this case is selected to be about 50 keV. After this, resist 19 is removed.

(G) The semiconductor substrate 1 is heat-treated at a high temperature of, for example, 1000° C. for about one hour in an inert gas atmosphere to stretch and diffuse the p-type diffusion layer 2o. As the inert gas, for example, g, element, or argon, or a mixed gas obtained by adding acid li4 to these gases is used.

Next, using the newly formed resist 19 as a mask,
In the source region and drain region of the nonvolatile memory element,
For example, add n-conductivity-imparting substances such as arsenic to 101s to 10"
A high concentration of IF is achieved by stopping the ions to about /-
A type 4 semiconductor region 32 is formed. The implantation energy at this time is selected to be about 250 keV. After this, resist 19 is removed.

(H) Using the newly formed resist 19 as a mask,
For example, 50k of n1fli property imparting material such as phosphorus is applied to the formation region of the n-channel MI S FET for the peripheral circuit.
Ion implantation is performed at approximately 1.0''/aJ with an energy of approximately eV to form an n-type semiconductor region 22 that will become a source/train region.

After this, the resist is re-formed and the p-channel MI
Also in the formation region of the SFET, a P conductivity imparting substance such as boron is applied at 1013/a with an energy of about 15 ksV.
By implanting ions at the J position, a p-type semiconductor region 23 which will become a source/drain region is formed. 6 (I) Sidewall spacers 7 made of resist are formed along the sides of the control gate electrode 5. The sidewall spacer 7 is formed by forming a resist to a predetermined thickness over the entire surface and then uniformly scraping off the thickness by anisotropic etching. At this time,
The sidewall spacer 7 portion is formed where the resist remains at the end. In other words, anisotropic etching is performed to such an extent that only the sidewall spacer 7 is left uncut. In this case, the sidewall spacers 7 are formed so as to protrude laterally from both sides of the control gate electrode 5 by about 0.25 μm on each side.

(,I) The floating gate electrode 3 of the nonvolatile memory element is formed by patterning the first electrode layer 14 by self-alignment using the control gate electrode 5 and the sidewall spacer 7 as a mask. As a result, floating gate electrode 3 is formed which is expanded by about 0.25 μm on one side compared to control gate electrode 5 .

(K) After forming a silicon oxide film on each exposed surface of the floating gate electrode 3 and the semiconductor substrate 1 by oxidizing the semiconductor substrate 1, a rough mask of the resist 19 is used to form a silicon oxide film on the nonvolatile memory element and the peripheral circuit. Approximately 60% of n-conductivity imparting material, such as arsenic, is applied to the source and drain regions of each n-channel MISFET.
At 0, ions are implanted at the l O''/d position with an energy of θV (22').

Similarly, in the source/drain regions of P-channel MISFETs for peripheral circuits,
For example, ions of a PR conductivity imparting substance such as boron are implanted into the 101s/ff1 position at an energy of about 15 keV (23').

Thereafter, the ion implantation layers 22' and 23' are activated by annealing at about 900°C.

(L) 1 on the entire surface of the semiconductor substrate 1 by, for example, CVD;
An insulating film 26 made of PSG, BPSG, or a laminated film of a silicon oxide film and PSG or BPSG is formed.

After this, a contact hole 27 for electrode connection is formed,
A wiring layer 8 made of aluminum is patterned to perform electrode extraction and wiring.

Then, a final protective film (not shown) is formed.

In the above manner, as shown in FIG.
A floating gate electrode 3 provided above with a first gate insulating film 2 in between, a control gate electrode 5 provided on this floating gate electrode 3 with a second gate insulating film 4 in between, and the floating gate. A nonvolatile memory element having a source region 61 and a drain region 62 that partially overlap electrode 3 is formed together with a MISFET for peripheral circuitry.

As a result, it is possible to increase the overlapping area between the source region 61 or drain region 62 and the floating gate electrode 3 while using self-alignment microfabrication technology without having to forcefully perform unnecessary stretching and diffusion processing. and the source region 6 at the overlapping part.
1 and the drain region 62 can be increased with good reproducibility and controllability.

FIG. 3 shows another embodiment of a nonvolatile memory element according to the present invention.

In the embodiment shown in the figure, floating gate voltage #@3
and control gate electrode 5 are asymmetric on the source region 61 side and the drain region 62 side. In this case, the source region 61 side of the floating gate electrode 3 is
Similar to the embodiment described above, the side wall spacer 7 is 0.2 to 0.
It is formed to protrude laterally by 3 μm. However, on the drain region 62 side, the respective ends of the floating gate electrode 11 and the control gate electrode 23 are aligned at substantially the same position.

With such an asymmetric structure, it is possible to increase the overlap between the source region 61 and the floating gate electrode 3 to improve erase characteristics, while reducing the overlap between the drain region 62 and the floating gate electrode 23 to improve write characteristics. At the same time, it becomes possible to improve the characteristics.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. 111 For example, the floating gate electrode 3 and the control gate electrode 5 may be partially or entirely made of Mo, W, or T.
a, it may be replaced with a high melting point metal such as Ti.

[Effects of the Invention] The effects obtained by the typical inventions disclosed in item-1 of this application are briefly explained below.

That is, 1. Since the overlap between the source region and the floating gate electrode can be reliably obtained, variations in erase characteristics can be eliminated.

2. Since the concentration of the conductivity-imparting substance in the source region under the floating gate electrode can be increased with good controllability, the influence of the formation of an inversion layer or the spread of a depletion layer on the surface of the semiconductor substrate during erase operation is reduced ( Second, the tunnel current is increased by applying the erase electric field only through the gate insulating film, thereby making it possible to increase the erase characteristics, especially the erase speed.

3. Microfabrication by self-alignment is possible.

This effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the main parts of a non-volatile memory element according to an embodiment of the present invention, and FIG. 2 shows the main parts of a method for manufacturing a semiconductor memory device having the non-volatile memory element shown in FIG. 3 is a sectional view showing the main parts of a nonvolatile memory element according to another embodiment of the present invention, and FIG. 4 is a sectional view showing a conventional nonvolatile memory element. It is a sectional view showing an outline. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First gate insulating film, 3... Floating gate electrode, 4... Second gate insulating film, 5... Control gate electrode, 61...Source region, 62...Drain region, 7...Side wall spacer, 8...Aluminum wiring, 14...First electrode layer, 16...
- Second electrode layer, 19...photoresist.

Claims (1)

[Claims] 1. A floating gate electrode provided on a semiconductor substrate with a first gate insulating film in between, and a control gate electrode provided on the floating gate electrode with a second gate insulating film in between. and an electrically erasable nonvolatile memory element having a source region and a drain region formed under the floating gate electrode, spaced apart from each other and partially overlapping with the floating gate electrode, the electrically erasable nonvolatile memory element comprising: A non-volatile device characterized in that a side portion of the gate is set back from a side portion of the floating gate, and at least one of the source region or the drain region is formed below an end of the control gate. Sexual memory element. 2. Forming a first insulating film on the semiconductor substrate of the first conductivity type; forming a first electrode layer on the first insulating film; forming a second electrode layer on the first electrode layer; forming a gate insulating film, forming a second electrode layer on the second insulating film, patterning the second electrode layer to form a control gate electrode, masking the control gate electrode. a step of forming a source region and a drain region of opposite conductivity type on the semiconductor substrate of the first conductivity type, a step of forming a sidewall spacer on the side of the control gate electrode, and a step of forming the control gate electrode and the sidewall spacer. A method for manufacturing a non-volatile memory element, comprising the step of forming a floating gate electrode that extends outward from a side portion of the control gate electrode by patterning the first electrode layer as a mask. 3. The thickness of the mask formed over the entire surface of the control gate electrode is removed by anisotropic etching, and sidewall spacers are left on the sides of the control gate electrode. A method for manufacturing a nonvolatile memory element according to item 1. 4. The method for manufacturing a nonvolatile memory element according to claim 1 or 2, wherein a polycrystalline silicon film is formed as the first electrode layer and the second electrode layer.