JPH113948A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent impurities from being diffused from a floating gate to a tunnel oxide film, by a method wherein the tunnel insulating film which is partially formed in the thin film thickness of an insulating film is provided between an insulating diffused layer and the floating gate, and, after the floating gate introduced with impurities is formed, a heat treatment of a specified temperature is performed on the floating gate. SOLUTION: A polysilicon one layer type EEPROM consists of a structure, wherein a tunnel insulating film 3a, which is partially formed in the thin film thickness of an insulating film, is provided between an impurity diffused layer 1 provided in a semiconductor substrate and a floating gate 2 consisting of a polysilicon film, and a control gate is adjacent to the gate 2. A gate electrode material may be formed into a polysilicide structure such as a tungsten structure without limiting to a polysilicon structure. Here, if the temperature of a heat treatment after the gate 2 introduced with impurities is formed is set at 950 deg.C or lower, the amount of the impurities which are diffused from the gate 2 to the tunnel oxide film is inhibited, and the characteristic amount of a charge to pass through the oxide film until the oxide film reaches a level causing dielectric breakdown can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device having a structure in which a tunnel insulating film having a small insulating film thickness is partially provided between an impurity diffusion layer provided in a semiconductor and a floating gate. In the device, a nonvolatile memory (Electricica) for electrically erasing and writing data by injecting and emitting electrons to the floating gate using Ferrari-Nordheim tunneling through the tunnel oxide film.
lly Erasable Programmable
Read Only Memory; EEPROM)
It is related to technology that is effective when applied to

[0002]

2. Description of the Related Art A tunnel insulating film having a thin insulating film is provided partially between an impurity diffusion layer provided in a semiconductor and a floating gate, and has a single-gate structure in which a control gate is arranged adjacent to the floating gate. Conventionally, in a semiconductor nonvolatile memory device, a floating gate is formed even in a case where an impurity to be introduced into a floating gate is set to a low concentration in order to prevent impurity diffusion from a floating gate to a tunnel oxide film. If the subsequent heat treatment is performed at a temperature higher than 950 ° C., impurities diffuse from the floating gate to the tunnel oxide film, and endurance characteristics and dielectric breakdown characteristics of the tunnel insulating film deteriorate.

[0003]

According to the first aspect of the present invention, a tunnel insulating film having a small insulating film thickness is partially provided between an impurity diffusion layer provided in a semiconductor and a floating gate, and a control gate is provided. In the case of a semiconductor nonvolatile memory device having a single-layered gate structure disposed adjacent to the floating gate, if the heat treatment after forming the floating gate into which the impurity is introduced is performed at a temperature higher than 950 ° C., the tunnel oxidation is performed from the floating gate. There is a problem that impurities are diffused into the film and endurance characteristics and dielectric breakdown characteristics of the tunnel insulating film are deteriorated.

[0004] Therefore, regarding the invention described in claim 1,
By limiting the heat treatment temperature after the formation of the floating gate into which the impurities are introduced to 950 ° C. or less, the diffusion of the impurities into the tunnel oxide film is prevented, thereby deteriorating the endurance characteristics and the dielectric breakdown characteristics of the tunnel insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device in which such a problem is solved.

[0005]

According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a tunnel insulating film having a small insulating film thickness is provided between an impurity diffusion layer provided in a semiconductor and a floating gate, In a semiconductor nonvolatile memory device having a single-gate structure in which a control gate is disposed adjacent to the floating gate, a heat treatment after forming the floating gate into which the impurity is introduced is performed at 950.
It is characterized in that the temperature is limited to not more than ° C.

According to the above structure, the diffusion of impurities from the floating gate to the tunnel oxide film is prevented, thereby improving the endurance characteristics and the dielectric breakdown characteristics of the tunnel insulating film.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a main part of an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, 1 is an impurity diffusion layer provided in a semiconductor substrate, 2 is a floating gate made of polysilicon,
Reference numeral 3 denotes an insulating film, 3a denotes a tunnel film which is a partly thin region of the insulating film, 4 denotes a high breakdown voltage transistor, 5 denotes a well region provided in a semiconductor substrate, and 6 denotes a semiconductor substrate. The structure will be described. A tunnel insulating film 3a having a thin insulating film is provided partially between an impurity diffusion layer 1 provided in a semiconductor and a floating gate 2 made of polysilicon, and a control gate is adjacent to the floating gate. FIG. 3 is a cross-sectional view of a single-layer polysilicon type EEPROM having a structure as described above. The gate electrode material is not limited to polysilicon, and may have a polycide structure of tungsten, titanium, molybdenum, or the like.

FIG. 2 is a diagram showing the temperature dependence of the heat treatment after the formation of the floating gate 2 of the standardized Qbd (the amount of charge passing through the oxide film until the dielectric breakdown occurs). As is apparent from FIG. 2, when the temperature of the heat treatment after the formation of the floating gate 2 is 950 ° C. or higher, the Qbd characteristics tend to deteriorate. This is because when the temperature of the heat treatment after the formation of the floating gate 2 into which the impurity is introduced is set to 950 ° C. or lower, the amount of the impurity diffused from the floating gate into the tunnel oxide film is suppressed, and the Qbd characteristic is improved. Can be. Therefore, it is preferable to limit the heating step using a furnace to 950 ° C. or less, except for a heat treatment that is completed in a relatively short time, such as lamp annealing, after the formation of the floating gate 2 into which the impurities are introduced.

According to the above-described configuration, by preventing the diffusion of impurities from the floating gate 2 to the tunnel oxide film 3a, it is possible to improve the endurance characteristics and the dielectric breakdown characteristics of the tunnel insulating film.

[0011]

According to the first aspect of the present invention, a tunnel insulating film having a small insulating film thickness is provided partially between an impurity diffusion layer provided in a semiconductor and a floating gate, and the control gate is formed of the floating gate. In the semiconductor non-volatile memory device having a single-layered gate structure, the heat treatment temperature after the formation of the floating gate into which the impurity is introduced is limited to 950 ° C. or lower, so that the floating gate can be removed from the tunnel oxide film. The amount of impurities eluted can be reduced, and the endurance characteristics and the insulating characteristics of the tunnel insulating film can be improved.

[Brief description of the drawings]

FIG. 1 shows a semiconductor having a single-gate structure in which a tunnel insulating film having a small insulating film thickness is provided partially between an impurity diffusion layer provided in a semiconductor and a floating gate, and a control gate is arranged adjacent to the floating gate. FIG. 3 is a cross-sectional view illustrating a main part of the nonvolatile memory device.

FIG. 2 is a diagram showing the temperature dependence of a heat treatment after a standardized Qbd floating gate is formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Impurity diffusion layer provided in the semiconductor substrate 2 ... Floating gate made of polysilicon 3 ... Insulating film 3a ... Tunnel film which is a partially thin region of the insulating film 4 ... High Withstand voltage transistor 5 ... Well region provided in semiconductor substrate 6 ... Semiconductor substrate

Claims (1)

[Claims] 1. A tunnel insulating film having a thin insulating film is provided partially between an impurity diffusion layer provided in a semiconductor and a floating gate, and a control gate has a single-layer structure in which the control gate is arranged adjacent to the floating gate. In the semiconductor nonvolatile memory device, the heat treatment temperature after the formation of the floating gate into which the impurity is introduced is set to 95
A method for manufacturing a semiconductor memory device, wherein the temperature is limited to 0 ° C. or lower.