JPH02283171A - Vertical synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To obtain a vertical synchronizing pulse by obtaining the length for one horizontal period to a composite synchronizing pulse and discriminating a level of a composite synchronizing pulse for a period such as 1/4H and 3/4H. CONSTITUTION:A composite synchronizing pulse Pc is fed to a trailing detection circuit 41, from which a pulse Pd for each trailing of the pulse Pc is extracted. A count N when the pulse Pd is obtained represents the length of present one horizontal period and a level L of a latch 23 represents the length of one horizontal period before one preceding horizontal period. The level L is supplied to division circuits 24-26, in which the value is divided into 1/4, 3/4, 6/4, the quotient is fed to an A input of comparator circuits 31. 33 and a value N is fed to a B input of the comparator circuits 31. 33. Then a pulse P1 is obtained from the circuit 31 at a point of time of 1/4H and a pulse P2 is obtained from the circuit 32 at 3/4H. The pulses P1, P2 are supplied to the latch 12 as clocks through an OR circuit 34 and a vertical synchronizing pulse Pu separated from the pulse Pc is obtained at the output of the latch 12.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a vertical synchronization separation circuit.

[Summary of the Invention] The present invention provides a synchronization separation circuit for vertical synchronization pulses that separates vertical synchronization pulses based on the level of a composite synchronization pulse at a predetermined point in time. This is done stably regardless of the pulse width of the pulse or the presence or absence of an equivalent pulse.

[Conventional technology]

FIG. 4 shows an example of a circuit that separates the vertical synchronization pulse from the composite synchronization pulse.

That is, in the integrating circuit (1), a composite synchronizing pulse Pc (Ph is a horizontal synchronizing pulse) shown in FIG. 5A is generated.

(Pv is a vertical synchronizing pulse, Pe is an equalization pulse, and LH is one horizontal period) is integrated, and an integrated signal Si whose level decreases for each pulse Pv is extracted as shown in FIG. In the comparator circuit (2), the voltage is compared with the reference voltage Vr and the pulse Pv is generated as shown in FIG.
A pulse that reaches the "1. TI level", that is, a vertical synchronizing pulse Pu, is extracted every time.

[Problem to be solved by the invention]

However, in the vertical synchronization separation circuit described above, if the level of the reference voltage Vr deviates as shown in FIG. 6B, for example, the separated vertical synchronization pulse Pu will suffer from chattering as shown in FIG. This can cause jitter and unstable interlace.

In addition, in the NTSC system, the horizontal frequency = 4.5 MHz/286 - 15.734, the pulse width (existence period) of the 7 vertical synchronizing pulses Pv = 3 horizontal periods, the pulse width of the equalization pulse Pe - 3,000 periods. However, in devices that output video signals, such as personal computers, the synchronization-related formats vary depending on the manufacturer and model. for example,
As shown in FIG. 7A, the horizontal frequency is higher than that of the NTSC system, and the pulse width of the vertical synchronizing pulse Pv is NT
Some methods are shorter than the SC method.

Then, there is a so-called multi-scan CRT display, that is, a CRT display that can display an image by following the horizontal frequency even if the horizontal frequency is different. Even in the case of a composite synchronization pulse Pc such as Pc, an image must be displayed according to this.

However, in the case of the synchronization separation circuit shown in FIG. 4, when the composite synchronization pulse Pc of FIG. 7A occurs, the state shown in FIG. 7B and C occurs, and the vertical synchronization pulse Pu cannot be obtained.

Of course, in this case, if the reference voltage Vr is shifted higher, the seventh
Although the pulse Pu can be separated using the pulse Pc in FIG. A, this tends to cause chattering as shown in FIG. 6.

This invention attempts to eliminate the above-mentioned problems.

[Means to solve the problem]

Therefore, in the present invention, the length of one horizontal period is determined for the composite synchronization pulse Pc, and the length of the horizontal period is determined, for example, 1/
The vertical synchronizing pulse Pu is obtained by determining the level of the pulse Pc at the time points of 4H and 3/4H.

[Effect]

Horizontal frequency, pulse width of vertical synchronization pulse Pv.

Vertical synchronization pulse Pu with or without equalization pulse Pe
is taken out.

〔Example〕

In FIG. 1, the composite synchronization pulse Pc is passed through the terminal (11) to the D
is supplied to the input, and its Q output is connected to the terminal (13).
It is taken out.

In this case, this synchronization separation circuit is for multi-scan, and the format of the pulse Pc varies as mentioned above, but here it is assumed that the pulse Pc is of the NTSC system, as shown in FIG. 2B. . Further, as shown in FIG. 1A, the 1/4H and 3/4H points in each horizontal period are indicated by O marks and X marks.

Furthermore, the clock CLCK is supplied as a count input to, for example, a 12-bit counter (22) through the terminal (21), and the pulse Pc is supplied to the falling edge detection circuit (41) to generate a pulse as shown in FIG. Pc
A pulse Pd is taken out at each falling edge of
) to the clear input CL of the counter (22).

In this case, the clock CLCK has a frequency sufficiently higher than the horizontal frequency of the pulse Pc, in this example, the pulse Pc.
The horizontal frequency at c is about 15kHz to 1.28
Since it covers frequencies up to kHz, it is considered to be 16 old [2]. Further, the switch circuit (42) is used to ignore the pulse Pd when the equalization pulse Pe is generated, and is basically always on, although the details of its operation will be described later.

Therefore, the counter (22) is set to 1 by the pulse Pd.
It is cleared every horizontal period, and the clock CL (
J is counted, so the count value N is "0" when the pulse Pd is in each horizontal period, as shown in the second diagram.
” and then gradually increases in size. In addition, pulse Pd
When cleared by , the count value N indicates the length of one horizontal period of the pulse Pc.

This power count value N is supplied to the D input of the latch (23), and the pulse Pd is supplied to the D input of the latch (23).
4) is supplied as a clock to the latch (23). Note that the switch circuit (44) is the same as the switch circuit (44).
This is the same as 2).

Therefore, the latch (23) latches the count value N of the counter (22) every horizontal period with the pulse Pd, and the counter (22) also latches the count value N of the counter (22) with the pulse Pd.
When cleared by d, this clearing is done by the latch (23
) is delayed by the pulse width period of the pulse Pd, so the count value N of one horizontal period immediately before is latched in the latch (23).

That is, when a pulse Pd is obtained for each horizontal period, the count value N indicates the current (latest) length of one horizontal period, and the value of the latch (23) is equal to the length of the current (latest) one horizontal period. This indicates the length of the horizontal period.

This value is then supplied to the division circuits (24) to (26) and divided by the size of, for example, 1/4.3/4.6/4, respectively, and the quotient is the comparator circuit (31) to (26). 33), and the count value N is supplied to the B inputs of comparison circuits (31) to (33).

Therefore, from the output terminal (A=B) of the comparator circuit (31), as shown in FIG. When , pulse P1 is obtained and the output terminal of the comparison circuit (32) (A=B
), as shown in 11F, a pulse P2 is obtained when N-3/4H, that is, at 374H (point of time marked with an x).

Since these pulses P, , P2 are supplied as clocks to the latch (12) through the OR circuit (34), the Q output of the latch (12) is as shown in G in the figure, when the vertical synchronization pulse Pν is It is at the "L" level, and at other times it is at the "H" level, which is nothing but the vertical synchronizing pulse Pu. Therefore, the vertical synchronizing pulse Pu separated from the pulse Pc is taken out to the terminal (13).

And in this case, the switch circuits (42), (44)
is controlled as follows.

That is, each output terminal (
When N<3/4L and N<6/4L from A<B), the comparison output Q2 becomes "H" level. Q, is taken out, and these outputs Q, , Q:l are supplied to the logic circuit (51), and from the logic circuit (51), 3/4 L <
When N < 6/4 L, α-“H′” level When other than the above, a signal α with α=“′L” level is taken out. Then, this signal α is transmitted to the switch circuit (
42) as its control signal, and is also supplied as its control signal to the switch circuit (44) through the OR circuit (52).
) is turned on when α=“H”.

Therefore, as shown in FIG. 3, at the time of 1/2H, that is, at the time of the equalization pulse Pe0, it is α-“L”, so the switch circuits (42) and (44) are off, and the equalization pulse Pe0 The pulse Pd detected from is ignored, and as described above, the counter (22) and latch (23) are cleared and latched by the pulse Pd every horizontal period.

Furthermore, from the output terminal (A=B) of the comparator circuit (33), N=
At 6/4L, a pulse P3 that reaches the HII level is taken out, and this pulse P3 and pulse P2 are supplied to the logic circuit (51), which outputs (N≦3/4L or 6/4L). 4L≦N), for example, 64 times in a row β=“°H°゛ level Other than the above
A signal β with β = “L” level is taken out, and this signal β is applied to an OR circuit (5
2) is supplied to the switch circuit (44) as its control signal, and the switch circuit (44) is turned on when β-“°H°”.

Therefore, the horizontal cycle days have changed significantly (less than 374 or more than 674), and the state is 6
When it continues for four horizontal periods or more, the horizontal period H after the change is latched in the latch (23), and thereafter, the vertical synchronizing pulse Pu is taken out as described above.

〔Effect of the invention〕

Thus, according to the present invention, regardless of the horizontal frequency, the vertical synchronizing pulse Pu Therefore, the vertical synchronization pulse Pu can be obtained for a wide range of horizontal frequencies, such as from 15 kHz to 128 kHz.

Also, in the composite synchronization pulse Pc, the vertical synchronization pulse P
Even if the pulse width of ν is 1/2 H, as is clear from FIG. 2, Pu = "L 11", so the vertical synchronizing pulse Pu can be taken out.

Furthermore, to separate the vertical synchronization pulse Pu, the equalization pulse Pe
Since the presence or absence of the interlace does not matter, chattering does not occur, and therefore jitter and interlacing do not become unstable.

Also, the separated vertical synchronization pulse Pu must be 1/4H
Or, since it is synchronized to the 3/4H time point (pulse P+ or P2), the raster is always 50% when interlaced.
becomes interlaced.

Furthermore, the division circuit (24) only needs to shift the parallel data representing the value by two bits to the right and supply it to the comparison circuit (31), and is not actually required to be provided as hardware. Furthermore, the division circuit (25) only needs to add the parallel data of the value to the data shifted to the right by 2 bits and the data shifted to the right by 1 bit. , it is only necessary to add the data obtained by shifting this one bit to the right, so the cost is low.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 7 are diagrams for explaining the same. (12), (23) are latches, (22) are counters, (24) to (26) are division circuits, (31) to (33)
is a comparison circuit, and (51) is a logic circuit.

Claims (1)

[Scope of Claims] A first latch to which a composite synchronization pulse is supplied; a counter that measures the length of one horizontal period of the composite synchronization pulse; a second latch that latches at , and a first pulse is formed from the count output of the counter and the value of the second latch at a time point between the horizontal sync pulse and the equalization pulse in the composite sync pulse. a circuit for forming a second pulse at a time between the equalization pulse and the horizontal synchronization pulse from the count output of the counter and the value of the second latch; and a vertical synchronization separation circuit which supplies a second pulse to the first latch as its clock and extracts a vertical synchronization pulse from the first latch.