JPH02281293A - Multiwindow display controller - Google Patents

Abstract

PURPOSE:To rapidly display the window screen after the end of an edition processing on a display by providing a frame memory, a window memory, a reading out signal control section, a writing control section, and an address selection control section. CONSTITUTION:The reading out signal control section 11 accepts the address read out of the address selection control section 13, reads out the image signal stored in the window memory 2 and outputs the signal to the writing control section 12. The writing control section 12 accepts the writing address from the address selection control section 13 and writes the image signal inputted from the reading out control section 11 to the frame memory 3. The address selection control section 13 outputs the writing address different from reading out order to read out the image signal from the window memory 2 to the writing control section 12 in the case of changing the content of the window screen in accordance with the image signal stored in the window memory 2. The edition processing is executed without changing the contents of the window memory at all in the case of executing the edition processing in this way. The display screen after the edition processing is thus rapidly displayed on the display.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multi-window display control device that displays a plurality of window screens on a display screen of a display.

(Prior Art) In recent years, display screens of personal computers, word processors, and the like have been designed to have multiple windows so that various types of information can be displayed at once. That is, the information already displayed on the display is not completely erased, but other information is displayed in a superimposed manner on a part of the display screen. By adopting such a display method, various types of information can be referred to at once, and processing can be performed efficiently.

FIG. 2 shows a block diagram of a conventional multi-window display control device.

In the figure, a window memory 2 and a frame memory 3 are connected to a processor l. Frame memory 3
A display control section 4 is connected to the . A display 5 is connected to the display control section 4 .

The processor 1 controls each part constituting the device. The window memory 2 includes a RAM (not shown) that stores signals read by an image reading device and signals input manually from a keyboard as dot information. The frame memory 3 is composed of a RAM and the like that stores an image signal corresponding to one screen of the display 5 as dot information. The display control unit 4 is composed of a known display control circuit or the like that controls the display on the display 5 based on the image signal stored in the frame memory 3. Note that the operation timing of this display control section 4 is controlled by the processor 1. The display 5 is a display device that displays the image signal of the frame memory 3.

The operation of the multi-window display control device having the above configuration will be explained with reference to FIG.

FIG. 3 is an explanatory diagram of the operation of a conventional multi-window display control device.

The figure shows a window memory 2, a frame memory 3, and a display screen 5a of a display 5.

In the figure, the window memory 2 has multiple areas (area a
,,b,,c,...).

Each area is an area for storing an image signal such as a window screen, which will be explained later. Here, it is assumed that the area a stores an image signal read by an image reading device, the area b1 stores an alphabetical image signal, and the area c1 stores a kana image signal.

When displaying these image signals on the display screen 5a of the display 5, the image signals of each area are first read out from the window memory 2. Then, each image signal is written into the frame memory 3. At this time, the image signal of area a1 is
Writing starts from the write start point a3 of the frame memory 3. Similarly, the image signals of area b1 and area C8 are respectively written at the writing start point t)5. Start writing from C3. Note that the image signal written from the write start point a3 of the frame memory 3 is used for display on the window screen a2 of the display screen 5a. Similarly, the image signals written from the write start point b3 and the write start point C3 are respectively applied to the window screen b2. c.
Used to display 2.

Now, in the display screen 5a shown in FIG. 3, the window screen b2 has the highest priority, and from then on, the window screen 02%
The priority order is set in the order of window screen a2.

This priority becomes a problem in the overlapping portion of each window screen. The higher the priority, the more its own window screen is displayed in the overlapping portion. Specifically, in the state shown on the display screen 5a, the window screen a
2+b2. When displaying C2, the processor 1 first reads the image signal from the area a1 of the window memory 2 and writes it into the frame memory 3. Similarly, the area ct l
The image signals are read out in the order of bl and written into the frame memory 3. In this way, the area al + C+ l bl
By writing to the frame memory 3 in the order of
On the display screen 5a, the window screen a2 is displayed first, and then the window screens c, , b2 are displayed in this order. As a result, in the overlapping part between the window screen a2 and the window screen c2, the window screen C2 is
Furthermore, the window screen b2 is displayed in the overlapping portion between the window screen c2 and the window screen b2.

Through the above-described operations, a so-called multi-window display in which a plurality of window screens are displayed on the display screen 5a is performed.

(Problems to be Solved by the Invention) Now, with reference to FIG. 4, a case will be described in which editing processing is performed to change the contents of the window screen b2 in the display screen 5a shown in FIG. 3.

Specifically, as shown in FIG. 3, the window screen b2 has the alphabets A to D in the first line, the alphabets E to H in the second line, the alphabets 1 to 1 in the third line, and the alphabets in the fourth line. M-P is displayed. A case will be described in which editing processing is performed in which among these lines, the first line is moved to the fourth line, and the second to fourth lines are moved from the first line to the third line.

FIG. 4 shows an operation explanatory diagram of editing processing of a conventional multi-window display control device.

The figure shows the window memory 2, the frame memory 3, and the display screen 5a of the display 5, as in FIG. Note that for window memory 2, area b
Only + is shown.

First of all, in the area b1 of the window memory 2, the first line is alphabets A to D, the second line is alphabets EH,
The third line is the alphabets 1 to L1, and the fourth line is the letters M to P (the state marked ■ in the figure). area b
1 is in this state, a window screen b2 as previously explained with reference to FIG. 3 is displayed. Here, processing to rewrite the contents of the window memory 2 is performed. That is, the area
The first row of is moved to the fourth row, and the second to fourth rows are moved from the first row to the third row. Through this editing process, the contents of area b1 become alphabets E-H in the first row, alphabets E-L in the second row, alphabets M-P in the third row, and alphabets A-D in the fourth row ( (state shown in the figure)
. When the window memory 2 area S is in this state,
The processor 1 reads the area bl of the window memory 2 and writes from the write start position b3 of the frame memory 3.

The display control unit 4 displays the display screen 5a on the display 5 based on the newly rewritten contents of the frame memory 3. That is, the first to third lines of the window screen b2 are changed to alphabets EP, and the fourth line is changed to alphabets A-D. Note that area b of window memory 2
Although the rewriting of 1 has been explained line by line, in reality, one line is rewritten bit by bit.

Now, as explained above, when editing a window screen conventionally, it was necessary to first rewrite the window memory 2 and then write to the frame memory. For this reason, for example, as explained in FIG. 4, even when simply moving the image signal that has been stored in the window memory 2, the entire area must be rewritten. Since this area b1 is rewritten bit by bit, it takes a very long time to complete the rewriting. For this reason, a problem has arisen in that it takes time from the start of the editing process until the display screen 5a after the editing process is actually displayed.

The present invention has been made with attention to the above points, and is capable of quickly displaying the window screen after the editing process is completed on the display without rewriting the window memory when performing the editing process. The object of the present invention is to provide a multi-window display control device.

(Means for Solving the Problems) A multi-window display control device of the present invention includes a display, a frame memory that stores image signals for at least one display screen to be displayed on the display, and a predetermined number of the display screens of the frame memory. a window memory for storing an image signal for the window screen to be written into an area; a readout control section for reading the image signal for the window screen from the window memory; and a readout control section for writing the image signal for the window screen to the frame memory. and an address switching control section that outputs a read address to the read control section and outputs a write address that is different from the read order according to the read address to the write control section.

(Function) In the above device, the read control section normally receives a read address from the address switching control section, reads out the image signal stored in the window memory, and outputs it to the write control section. The write control section receives the write address from the address switching control section and writes the image signal input from the read control section into the frame memory. When changing the contents of the window screen based on the image signals already stored in the window memory, the address switching control unit outputs a write address different from the read order for reading the image signals from the window memory to the write control means. . Thereby, the arrangement of image signals in the frame memory can be changed without changing the arrangement of image signals stored in the window memory.

(Embodiment) FIG. 1 is a block diagram of a multi-window display control device of the present invention.

In the figure, a window memory 2 and a frame memory 3 are connected to a processor 1. Frame memory 3
A display control section 4 is connected to the . A display 5 is connected to the display control section 4 .

The processor 1 controls each part constituting the device. The window memory 2 includes a RAM (not shown) that stores signals read by an image reading device and signals input manually from a keyboard as dot information. This window memory 2 has areas al+b+,...C+ corresponding to window screens to be explained later.
It is divided into. The frame memory 3 stores an image signal corresponding to one screen of the display 5 in dot format.
It is composed of a RAM and the like that stores information. The display control unit 4 is composed of a known display control circuit or the like that controls the display on the display 5 based on the image signal stored in the frame memory 3. Display 5
is a display device that displays the image signal of the frame memory 3.

The processor 1 includes a read control section 11 and a write control section 1.
2, and an address switching control section 13 are provided. The read control section 11 is composed of a gate circuit and the like that reads an image signal from the window memory based on the read address RA output from the address switching control section 13 and outputs it to the write control section. The write control section 12 is composed of a gate circuit and the like that writes the image signal input from the read control section 11 into the frame memory 3 based on the write address WA output from the address switching control section 13.

The operation of the multi-window display control device having the above configuration will be explained with reference to FIG.

FIGS. 5(a) to 5(d) are explanatory diagrams of the operation of the multi-window display control device of the present invention.

The figure shows an area b4 of the window memory 2 and an area b4 of the frame memory 3.

In the figure, for the window memory 2, the area b1 is the write start position, and for the frame memory 3, the write start position bs
(FIG. 4) shows a region b4 starting at (FIG. 4). This area b4 is an area for storing the image signal stored in area b1 of the window memory 2. The image signal stored in this area b4 is used to display the window screen b2 in the display screen 5a of the display 5 shown in FIG.

Now, as shown in FIG. 5(a), the area S of the window memory 2 stores image signals representing the alphabets AZ and numbers O to 9 arranged in 6 rows and 6 columns. Corresponding to the image signal in the window memory 2, it is assumed that image signals indicating the alphabets A to Z and numbers O to 9 are also stored in the area b4 of the frame memory 3 in the same arrangement.

In this way, the reason why the image signals in area b2 of the window memory 2 and area b4 of the frame memory 3 have the same arrangement is that the address switching control section 13 informs the readout control section 11 and the write control section 12 of the readout order and the write order. This is because the read address and write address are output so that the order matches. That is, the address switching control unit 13 first assigns the read address RA (0,
0), is output. On the other hand, first, the write address WA (0,0) is output to the write control unit 12. As a result, the arrangement of the image signals stored in the area b4 of the frame memory 3 becomes the same as the arrangement of the image signals stored in the area b+ of the window memory 2. Note that each matrix is configured as a set of image signals in bit units.

Here, as shown in FIG. 5(b), the frame memory 3
A case will be described in which editing processing is performed in which the first line consisting of the alphabet A-F arrangement in area b4 is moved to the sixth line, and the second to sixth lines are moved from the first line to the fifth line.

Here, the address switching control unit 13 sends a read address WA indicating the starting point of the area b4 to the write control unit 12.
The case where (0,0) is output first will be explained.

Normally, the read address that the address switching control section 13 first outputs to the read control section 11 is the read address RA (0,0) indicating the starting point of the area b1. but,
In the case of FIG. 5(b), α is
Read address RA (
0, α) is output first.

The address switching control unit 13 controls this read address RA.
Starting from (0, α), read address RA (n,
α).

・”RA (0, n), ・RA (n, n),
Then, read addresses RA(0,0) to RA(n,
0) and finally the read address RA (n, α-1
) is output. On the other hand, the address switching control unit 13 instructs the write control unit 12 to select the starting point of the frame memory 3, that is, write addresses WA (0,0) to WA (
n, n). Therefore, the area b4 of the frame memory 3 includes the first row of the area b1 of the window memory 2, and
The second to sixth rows are moved to the sixth row and the first to fifth row, respectively. As a result, each row is also displayed on the window screen b2 of the display screen 5a. This means that the read control unit 11
This is because the image signals are sequentially read out from the second row of the frame memory 3, while the write control section 12 writes the image signals sequentially from the first row of the area b4 of the frame memory 3.

Next, as shown in FIG. 5(c), from the state shown in FIG. 5(b), the first row consisting of the arrangement of alphabets G to L in area b4 of the frame memory 3 is moved to the sixth row, A case will be described in which editing processing is performed to move the second to sixth lines to the first to fifth lines.

Here, the address switching control unit 13 sends a read address RA indicating the starting point of the area b2 to the read control unit 11.
The case where (0,0) is output first will be explained.

First, the address switching control section 13 controls the readout control section 11.
Read addresses RA (0, O) to RA (n
, n). On the other hand, as the write address output to the write control unit 12, the write address WA (0, β) shifted in the row direction by β dots is output first. Starting with this write address WA (0, β), from now on, write addresses WA (n, β), ... WA (0, n
), -WA (n, n), and write address W
A (0, O), .W A (n, 0), and outputs up to the write address WA (n, β-1). Therefore, in the area b4 of the frame memory 3, the first and second rows and the third to sixth rows of the area b1 of the window memory 2 are the fifth and sixth rows, and the first row is, respectively. Move to the 4th line. Therefore, the window screen b2 of the display screen 5a
Also, each line is displayed moved. This is because the read control unit 11 reads image signals sequentially from the first row of area b2 of the window memory 2, while the write control unit 12 writes image signals sequentially from the fifth line of area b4 of the frame memory 3. This is because it is crowded.

Finally, as shown in FIG. 5(d), from the state shown in FIG. 5(C), the first column consisting of the alphabets A-Y and the number 4 in the area b4 of the frame memory 3 is 6
A case will be described in which editing processing is performed to move the second column to the sixth column from the first column to the fifth column.

Here, the address switching control unit 13 sends a successive address WA indicating the starting point of the area b4 to the write control unit 12.
The case where (0, O) is output first will be explained.

First, the address switching control section 13 controls the readout control section 11.
The read address RA is shifted by α dots in the column direction and γ dots in the row direction by switching the read address output to
(α.Y) is output. And this read address RA
Starting from (α.y), read address RA(n
,y),RA(0,Y),"・RA(a-1,Y),
...RA (a, n), -RA (a-1, n
), and read address RA(α, 0),...
Read address RA (α
-1, γ-1). On the other hand, the address switching control unit 13 outputs write addresses WA (0,0) to WA (n, n) to the write control unit 12.

Q Therefore, in the area b4 of the frame memory 3, the first column of the area b+ (FIG. 5(C)) of the window memory 2 is moved to the sixth column, and the second to sixth columns are transferred from the first column to the sixth column. Move to column 5.

As explained above, the image signal after the editing process is stored in the area b4 of the frame memory 3 without rewriting the area s of the window memory 2, and the window screen b2 of the display screen 5a (FIG. 1) is stored in the area b4 of the frame memory 3. The display will also change. This is because the address switching control unit 13 outputs read addresses and write addresses so that the order in which image signals are read from the window memory 2 is different from the order in which the image signals are written in the frame memory 3. It is. Therefore, image signals are written into the frame memory 3 in an arrangement as if the window memory 2 had been rewritten, and the display on the window screen b2 is accordingly changed.

The multi-window display control device of the present invention is not limited to the above embodiments.

Although the embodiment has been described using an example of editing processing in which the order of character arrangement patterns is changed, since the window memory 2 and frame memory 3 are read and written in units of dots,
It can also be applied to changing the arrangement of image data such as graphics.

(Effects of the Invention) The multi-window display control device of the present invention configured as described above has the following features:
Editing can be performed without changing the contents of the window memory at all, so there is no need for time required to rewrite the window memory. Therefore, the display screen after the editing process can be quickly displayed on the display.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multi-window display control device of the present invention, FIG. 2 is a block diagram of a conventional multi-window display control device, FIG. 3 is an explanatory diagram of the operation of a conventional multi-window control device, and FIG. 5(a) to 5(d) are explanatory diagrams of the operation of the editing process of the conventional multi-window display control device. 1... Processor, 2... Window memory, 3...
- Frame memo, 4...Display control unit, 5...Display, 5a...Display screen, 11...Reading control unit, 12...Writing control unit, 13...Address switching control Department. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A display; and at least one display screen displayed on the display.
a frame memory that stores image signals for a screen; a window memory that stores image signals for the window screen written in a predetermined area of the frame memory; and a readout that reads the image signal for the window screen from the window memory. a control unit; a write control unit that writes an image signal for the window screen to the frame memory; and a write control unit that outputs a read address to the read control unit, and that outputs a read address to the write control unit in a different order from the read order according to the read address. A multi-window display control device comprising: an address switching control section that outputs a write address.