JPH01202787A - Image memory - Google Patents

Abstract

PURPOSE:To execute a parallel processing of each storage part and to execute picture drawing in an image memory at a high speed by controlling an operation of a picture drawing storage part and a store storage part by a built-in picture drawing control part. CONSTITUTION:The structure of the title image memory contains a store storage part 15 in which a bit pattern is stored as data, a picture drawing storage part 17 in which a prescribed bit pattern is brought to picture drawing by the data fetched from the store storage part 15, and a picture drawing control part 11 for giving an address of a picture drawing position to the picture drawing storage part 17, and also, controlling an output of the data sent to the picture drawing storage part 17 from the store storage part 15. Accordingly, an operation of each storage part 15, 17 is controlled by the picture drawing control part 11 being independent from the outside. In such a way, a parallel processing of each storage part 15, 17 can be executed, and picture drawing in an image memory 1 can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention uses an image memory, that is, VRAM (Video), when displaying on a display or printing.

RA! J) It relates to a technique that is particularly effective when applied to a technique for drawing bit patterns such as characters on the surface.

[Conventional technology]

For example, Japanese Patent Laid-Open No. 62
There is No.-7087.

In the above publication, a direct memory access controller, a read-modify-write means, a bit shift means, and a means for performing a logical operation on the read result from the VRAM and external data and providing it again to the VRAM are installed in the periphery of the VRAM. The configured technology is shown.

In the above technology, when drawing a bit pattern on a VRAM, the following procedure is used.

That is, first, the bit pattern is read from the bit pattern storage storage unit in which the bit pattern is stored in advance, and second, the data is read from the address to be drawn on the VRAM, and the logic between the bit pattern and the read data is determined. This requires an execution procedure of performing an operation and, thirdly, writing data obtained as a result of the logical operation to the VRAM.

[Problem to be solved by the invention]

However, with the above-mentioned conventional technology, the number of bits that can be drawn in one cycle of writing is limited by the number of bits that can be read and written at once from the input/output terminal of the VRAM, so it is difficult to draw a large number of bits in one process. If this is attempted, a large number of VRAMs will inevitably be required.

For example, a VRA that can read and write 512 bits simultaneously
If an attempt was made to create an M system, 128 VRAMs capable of simultaneous reading and writing of 4 pits would be required, which would not only increase costs but also occupy a large area, which could lead to a decrease in reliability.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can speed up the drawing of bit patterns in an image memory such as a VRAM.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a storage storage section in which bit patterns are stored as data, a drawing storage section in which a predetermined bit pattern is drawn using data retrieved from the storage storage section, and an address of a drawing position is given to the drawing storage section. The structure includes a drawing control section that controls the output of data from the storage storage section to the drawing storage section.

[Effect]

According to the above-mentioned means, the image memory includes therein a drawing storage section and a bit pattern storage section, and the operation of each of these storage sections is controlled by a drawing control section independent from the outside. Therefore, each note 1. Parallel processing of the α part becomes possible, and the drawing speed in the image memory can be extremely increased.

Further, since the number of bits that can be drawn in one cycle does not depend on the number of input/output terminals of the image memory, even faster drawing is possible.

〔Example〕

FIG. 1 is a diagram showing the configuration of V RAM which is an embodiment of the present invention, FIG. 2 is a diagram showing the address configuration of the memory in the drawing storage section of FIG. 1, and FIG. 3 is a diagram showing the bit pattern in the character storage storage section. FIG. 4 is an explanatory diagram showing the flow of data when one line of character data is drawn on the drawing storage section.

As shown in FIG. 1, the image memo 'JVRAMI of this embodiment has a drawing control unit 11 that controls the drawing process within the VRAMI, and the operation of each part is controlled by manual selection signals from the drawing processor 10. a selection control section 12 that performs
A write control unit 13 that controls reading and writing based on read/write signals, and a drawing processor 10
a data width matching section 14 that matches the data width within the VRAMI with the external data width when inputting and outputting data signals from the character storage section 15 that stores bit patterns of characters such as character fonts; Storage section 15
It has a barrel shifter section 16 that shifts this data by a certain bit amount and outputs it after the control of the drawing control section 11 when outputting data from the PM screen memory 17. It constitutes a VRAM unit.

The address structure of the drawing storage section 17 is as shown in FIG. 2, for example. In the figure, one word as a unit of reading and writing of the memory is made up of bits arranged in the X direction, but this is not necessarily the case. There is no need to limit the arrangement.

Further, FIG. 3 shows an example of a character font stored in the character storage storage section 15, in which the English character "rA" is displayed using an 8×8=64 bit pattern.

Next, the operation of the VRAM 1 of this embodiment will be explained based on FIG. 1 above.

First, when using the drawing storage section 17 as a general memory and reading and writing to it, the selection control section 12
The drawing storage section 17 is selected by a selection signal from
Subsequently, a read/write signal from the write control section 13 instructs reading or writing, and data reading or writing is performed based on an address signal from the drawing control section 11. Such operations are similar to conventional memories.

Next, a case will be described in which characters are drawn using VRAMI.

Note that at this time, it is assumed that character fonts are stored in the character storage storage section 15 in advance. The character storage storage section 15
Writing of a character font to, for example, a character storage storage unit 15 composed of a RAM, is performed by writing a character font to a VRAM1 during operation.
It has a structure in which bit pattern data related to predetermined characters can be written from outside. To write such bit pattern data, first, the selection control section 12 writes the character storage storage section 15 based on a selection signal from the drawing processor 10.
At the same time, the selection control section 12 selects the drawing control section 1.
1. Output control signals to the write control section 13 and data width matching section 14, respectively.

Subsequently, a read/write signal is manually input from the drawing processor 10 to the character storage storage section 15 via the write control section 13. Here, a write mode is selected for the character storage storage section 15.

Next, the drawing processor 10 outputs an address signal to the drawing control section 11, and this address is further given to the character storage section 15 from the drawing control section 11. In synchronization with this, character data is applied from the drawing processor 10 to the character storage storage section 15 through the data width matching section 14, and bit pattern data of the character font is written to the designated address.

In the above explanation, the character storage storage section 15 is a volatile RAM.
Although a case has been described in which the font is configured as follows, it may also be configured with a ROM in which character fonts are fixedly written in advance. When configured with a ROM in this manner, there is an advantage that the writing operation to the character storage storage section 15 as described above is not necessary.

On the other hand, when configured with RAM that requires writing operations as described above, it is easy to change character fonts, and in actual use, for example, it is possible to store character fonts in a invasive manner starting from the most frequently used character fonts. This also has the effect of shortening the overall character drawing time.

Next, a case will be described in which characters are drawn in the drawing storage section 17 based on the character font data stored as described above.

First, the drawing processor 10 sends the drawing control unit 11 the address of the target drawing character on the character storage storage 15 and the number of bits in the X direction and Y direction of the drawing character (8 bits in each case in FIG. 3). ) and the X coordinate of the drawing position on the drawing storage section 17. At the same time, attribute data input manually by the drawing processor 10 is set in the drawing control section 11. This attribute data includes, for example, a color code, and by using the character font output from the character storage storage unit 15 as a mask and applying this attribute data, a character pattern of a predetermined color is stored in the drawing storage unit 17. is now written.

Through these series of operations, the drawing control section 11 enters the character drawing mode.

Next, the Y coordinate of the character drawing position in the drawing storage section 17 is input from the drawing processor 10, and the drawing storage section 17 is brought into a selected state by a selection signal from the selection control section.
The write mode is designated by the read/write signal. Subsequently, the drawing control section 11 writes the character storage section 15.
When is selected and given the start address where the character font is stored, the character storage storage unit 15 stores character data for one line in the character pattern to be drawn in the drawing storage unit 17 for the character font at the corresponding address. The signals are sequentially output to the barrel shifter section 16. The barrel shifter section 16 shifts the take by a predetermined amount corresponding to the drawing position in the drawing storage section 17 based on the control signal from the drawing control section 11, and sends the shifted character data to the writing control section 13. Output.

The character data in FIG. 4 is an example of 1947 minutes of character data shifted as described above.

On the other hand, the drawing control section 11 outputs a control signal to the selection control section 12 to put the writing control section 13 and the drawing storage section 17 in a selected state. Along with this, the drawing control unit 11
outputs the attribute data set above. The write control unit 13 outputs a write signal to each bit in the X direction of the drawing storage unit 17 based on the character data for one line shifted by the barrel shifter unit 16 as described above and the control signal from the drawing control unit 11. do. Drawing storage unit 1
7, character data and attribute data are associated with each other, and one line of the character specified by the address indicating the Y coordinate input manually from the drawing processor 10 and the write signal from the drawing control section 11 is written. Write data.

In this way, in this embodiment, all the data for one line of one character can be drawn by just writing the Y coordinate one time (one cycle) from the external drawing processor 10 to VRAMI. Once this one line of data has been drawn,
The drawing control unit 11 updates the address of the data to be output to the character storage storage unit 15 to the address corresponding to the next line.

Here, as shown in Figure 3, the English letter r is drawn with 64 dots.
When drawing AJ, writing to the drawing storage section 17 is completed by updating the address by 8 cycles, that is, 8 dots in the Y direction.

When such writing processing is completed, the drawing control unit 11
is released from the character drawing mode and waits for the next access from the drawing processor 10.

In the above-described series of character writing operations, in this embodiment, the VRAM itself has a character storage storage section 15, which operates in parallel with the drawing storage section 17 under the control of the drawing control section 11. Because of this structure, the drawing speed for the drawing storage section 17 can be increased.

In addition, since the character font attribute data for the drawing storage section 17 is generated within VRAMI, the number of bits that can be written to the drawing storage section 17 in the ■ cycle is set to V
It becomes possible to increase the number of RAMI input/output terminals without depending on the number, and the drawing speed can be further increased.

In the above explanation, when drawing a character font for one character, the structure is such that the drawing storage unit 17 is activated by giving an address in the Y direction from the external drawing processor 10 every time one line of character data is drawn. However, the present invention is not limited to this. For example, the drawing processor 10 may provide an address in the X direction and draw one line at a time in the Y direction, or two-dimensional dot data that extends in both the X and Y directions may be drawn in one line. It is also possible to have a structure in which data is written simultaneously by cycle access.

Furthermore, for the drawing control unit 11,
A structure may be adopted in which the Y coordinate is also set in addition to the coordinates, and subsequent drawing of one character in the drawing storage section 17 is performed only under the control of the drawing control section 11.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, character fonts are stored in the drawing storage unit 1.
7, but other characters such as symbols and figures, or even a set of any number of bits may be used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, it has a drawing memory section and a bit pattern storage memory section inside it, and since the operation of each of these memory sections is controlled by the built-in drawing control section, parallel processing of each memory section is possible. , the drawing speed in the image memory can be extremely increased. Further, since the number of bits that can be drawn in one cycle does not depend on the number of input/output terminals of the image memory, even faster drawing is possible.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a VRAM that is an embodiment of the present invention. FIG. 2 is a diagram of an address configuration of the memory in the drawing storage section of FIG. 1. FIG. 3 is an explanatory diagram showing a dot pattern in the character storage storage section. , FIG. 4 is an explanatory diagram showing the flow of data when one line of character data is drawn on the drawing storage section. ■...VRAM (Image memo IJ), 11... Drawing control section, 12... Selection control section, 13... Writing control section, 14... Data width matching section, 15... Character storage Storage unit, 16... Barrel shifter unit, 17... Drawing storage unit, 10... Drawing processor. Agent Patent Attorney Daiwa Tsutsui Figure 2 → X Figure 4

Claims (1)

[Claims] 1. A storage storage section in which bit patterns are stored as data, a drawing storage section in which a predetermined bit pattern is drawn using the data retrieved from the storage storage section, and an address of a drawing position is given to the drawing storage section. An image memory incorporating a drawing control section that controls output of data from the storage storage section to the drawing storage section.