JPS62203193A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image display device fK, which is a dot map type screen memory having a storage element corresponding to one dot for each dot of an image displayed on a display on a load. Regarding writing data.

[Conventional technology]

In a conventional image display device of this kind, the process of partially changing the dot data stored in the screen memory is carried out by the central processing unit f, for example, when transferring the dot data of a character pattern stored in the character generator to the screen memory.
(hereinafter referred to as the CPU): (1) Reads the dot data already stored in the corresponding part of the screen memory and imports it into the CPUK.

(2) Shift the dot data to be added to the display bit position.

(31) Read out the non-rewritten portion from the light dot data that has been taken into the CPU through mask processing, extract only the write bits from the shifted dot data that should be added through mask processing, calculate the logical sum of the two, and write a new write bit. Create dot data.

(4) Write new write dot data to the corresponding portion of the screen memory.

The following processing steps were taken. However, originally the CPU
The bit processing is slow, and in particular, the data shift of multiple bits is processed by repeating the 1-bit shift command step multiple times, which has the disadvantage of increasing the number of processing steps.

In order to improve these shortcomings, K. JP-A-59-901
As described in Japanese Patent No. 56, a memory control method has been proposed in which data is shifted using a shift register. However, even with this method, the shift operation is a 1-bit shift in 1 clock, so it takes time for multiple clocks to shift multiple bits of data.

On the other hand, what text is stored in the character generator? −
If the pattern has a matrix configuration of 24 x 24 dots and the processing unit of the CPU is a 16-bit word unit, the dot data is read from the character generator by dividing it into 16 bits on the right side and 8 bits on the left side. Generally, word access is performed by adding 8 bits of invalid data to the 8 bits.

[Problem that the invention seeks to solve]

In the method of reading the dot data of a character pattern using such a character generator access method, performing the data shift processing described above, and writing new dot data to the screen memory, the displayed character is shifted by several bits in the direction of the scanning line. In this case, the dot data must be read out from the character generator in multiple steps, resulting in an inconvenience that the display speed becomes slow.

Therefore, an object of the present invention is to further speed up the shift processing of dot data and to further speed up the display speed by continuously reading out the dot data from the character generator.

[Means for solving problems]

In order to solve this problem, the present invention has a character generator that divides the dot data of a 24 x 24 dot matrix into byte units in the scanning line direction, and divides each set of dot data into byte units in the scanning line direction. A memory for storing bytes in continuous addresses in parallel is provided, the screen memory is configured to have address order in the direction in which the scanning lines are arranged, and 24 bytes stored in the character generator are arranged in parallel.
A character generator read control circuit that reads out dot data of 24 dots either on the left 16 bits or on the right 16 bits in the scanning line direction in units of 16 bits and 1 word according to instructions from the CPU, and the dot data of the image given from the CPU side. A barrel shifter that shifts data by the amount of bits according to the shift amount command value given from the CPU, a mask controller that generates mask data that limits the write range of dot data given from the CPU side, and a mask controller that generates mask data that limits the write range of dot data given from the CPU side. The present invention is characterized in that it is provided with a write controller that synthesizes the dot data outputted from the barrel shifter and the dot data outputted from the barrel shifter in accordance with mask data to create new write data.

[Effect]

When accessing the character generator, the CPtr outputs a read address signal using a string instruction, and accesses either the left 16 bits or the right 16 bits of the memory sequentially in the direction of the scanning lines in the dot pattern to read the 16 bits. It captures dot data in units and outputs it together with the address signal of the corresponding part in order to write it into the screen memory. The barrel shifter immediately shifts this dot data by the amount of bits according to the shift amount command value from the CPU and outputs it. On the other hand, the write controller synthesizes the dot data read from the screen memory in response to the address signal and the dot data output from the barrel shifter according to the mask data from the mask controller, creates new write data, and writes it to the corresponding portion. By sequentially executing such processing for 24 words on either the left 16 bits or the right 16 bits of the memory read by the string instruction, and similarly executing it on the other side, Complete writing of dot data in the image pattern area for one character.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an image display device according to the present invention. Reference numeral 11 designates a central processing unit f (hereinafter referred to as CPU) for controlling the display function section, and for example, Intel's 8086 is suitable. 12 is an interrupt controller that gives an interrupt signal to the CPU 11 and branches the program in response to an external event. 13 is CPU
This is a program memory that stores programs executed by 11 and data processing information. 14 is a character generator (hereinafter referred to as CG) that stores characters (turns) to be displayed in a dot matrix, and is generally constituted by a ROM. 19 is a CG that changes the right side and left side of the d output data from CG 14. A continuous output control circuit 15 is an interface circuit for receiving commands from the host CPU which is a higher level display function section.16 is an interface circuit for generating an address signal for sequentially reading out the contents of the screen memory 20;
゛In addition, a graphic display controller (hereinafter referred to as GDC) that generates a synchronization signal to control the CRT monitor 24
). A control circuit 17 generates timing signals for the screen memory 20 and its peripheral circuits. 1B is a double-sided memory control circuit that supports drawing processing by the CPU 1 in synchronization with a write signal from the CPU II to the screen memory 20. 20 is the dot matrix image displayed on the CRT monitor 240 screen.
This is a bitmap type screen memory in which storage elements for storing dots correspond to the screen, and are composed of a dynamic RAM. 21 is horizontal from GDC16,
This is a synchronization circuit for synchronizing the vertical synchronization signal and the video signal from the shift register 23. 22 is screen memory 2
This is a latch that temporarily stores image dot data that continues from 0, 23 is a shift register that receives the image dot data stored in the latch 22, and converts it from parallel to serial, and 24 receives a video signal and a synchronization signal. The screen is displayed on a 5CRT monitor.

51-1.51-2 is CPU path signal line a and GDC16
A transceiver/receiver (52-
1, 52-2, and 52-3 are multiplexers that select and output a set of signals from among the input signal lines.

Details of the screen memory control circuit 18, which performs important functions as a component of this device, will be explained with reference to FIG.

In Figure 2, 18-1 is a data latch for the CPU 11.
Retains data from A barrel shifter 18-2 shifts the data from the data latch 18-1 in designated bit units. A write controller 18-3 generates data to be written to the screen memory 20. Reference numeral 18-4 is an operation register that holds operation commands for image dot data in bit units to be given to the light controller 18-3. Bit registers 18-5 and 18-6 hold a designated value of the amount of data shift by the barrel shifter 18-2. A mask register 18-7 holds a bit width command value for write operation. 18-8 is an arithmetic unit (hereinafter referred to as ALU)
), and the barrel shifter 18
Calculate the shift) [to be shifted by -2. A mask controller 18-9 outputs mask data for masking the writing of write data from the CPU II to the screen memo IJ 20 in accordance with the bit width command value held in the mask register 18-7. 18-10 is a control circuit that controls these operation timings.

Next, the busy access to the screen memory 20 will be explained. The screen memory 20 operates by read-modify-write when the CPUI 1 writes data. In other words, the dot data from CPU II is transferred to data latch 1.
8-1, processed by barrel shifter 18-2, and inputted to one input terminal of light controller 18-3. The lllli image dot data at the designated address in the screen memory 20 is read out and applied to the other input terminal of the write controller 18-3.

The above two inputs are logically operated on a bit-by-bit basis based on instructions stored in the operation register 18-4.
It will be written to the address specified by 00.

Next, the address structure of the double-sided memory 20 will be explained using diagram 43.

The video signal is composed of mask units as a series of image dots. That is, reading by the GDC 16 for refreshing the screen is in units of 16 pits from the beginning of the screen, which is serially converted from the MSB to the LSB.
After , the next 16 bits of MSB are consecutive.

By the way, when the CPU II handles a 24x24 bit character pattern, the depth is 3 bytes in the mask scan direction and 24 bytes in the direction of the mask arrangement order. Intel's 8086, which is used as a CPU II, has a string instruction for repeated processing of sequential addresses.

According to this string instruction, a specified number of words or bytes of data is transferred from a source address specified in a predetermined register to a destination add in the minimum instruction steps and the shortest processing time.

In order to obtain the maximum effect in this processing method, it is effective to increase the number of - transfers. Considering this point, the addresses of the screen memo IJ20 viewed from the CPUI 1 should be arranged in the forward direction of the raster arrangement.

FIG. 3 shows the address structure of the screen memory 20 realized based on the above points.

Next, CG14 will be explained. In this embodiment, the dot data of the character pattern is stored in 1% ROM as shown in FIG.
is stored in In other words, the dot data of the pattern constituting one character is divided into three groups in byte units in the scanning line direction: 24 bytes on the left side, 24 bytes in the center, and 2 groups on the right side.
4 bytes are stored in a row in the vertical direction and divided into 3 ROMs.

FIG. 5 shows the CG14 in which patterns are stored in three ROMs divided into 8 bits each in the scanning direction.
This figure shows a detailed configuration of a CG read control circuit 19 that controls when the CPU I reads out data in units of words.

In FIG. 5, the CG 14 consists of three ROMs 14-1 to 14-3 each having an 8-bit data bus.

19-1. ~19-4 is this ROM14-1~14-3
This is a transceiver that performs buffering when outputting dot data read from the CPU data bus to the CPU data bus.

If the left word of CG14 is accessed from CPUII, transceivers 19-1 and 19-2
is enabled by the data select circuit 19-5, and the left 16 bits of the character pattern dot matrix are output. Similarly (if the right word is accessed, the right 16 bits are output).

FIG. 6 clearly shows the relationship between addresses and dot data when the character pattern dot matrix of the Chinese character "Kan" is read out by the CGd output control circuit 19 of FIG. 5. The 8 bits in the scanning direction in the center are on the left! Duplicate reading is possible with both word access and right word access.

Note that the relationship between the read address and dot data in the conventional case without the CG read control circuit 19 is shown in the seventh column.
It is a diagram. When the left word of the character pattern dot matrix is accessed, the left 8 bits out of 16 bits are read out as invalid data.

Next, the operation of writing image dot data to the screen memory 20 and displaying the contents of the screen memory 20 on the CRT monitor 24 will be explained.

The image is displayed by writing dot data of screen memo 17201c'l' (bright dot) or 101 (dark dot) in bit units. Characters are displayed on the screen by writing dot data of a character pattern designated by the CG 14 to a word address on the screen memory 20 to be displayed using a string command.

The bit positions of the character pattern dot data when data is read from the CG 14 are arranged in word units as shown in FIG. Therefore, for example, when displaying the character example "Kanji" as shown in FIG. A mismatched state occurs due to an 8-bit shift. At this time, in the configuration without the screen memory control circuit 18, in the character pattern dot data transfer process from the CG 14 to the screen memory 20,! Bit shift processing must be performed on @ for word transfer. In other words, even in the 8086 series CPU II,
Memory movement using string instructions, which is more powerful than the aforementioned word transfer, could not be used.

In this embodiment, by providing the screen memory control circuit 18 shown in FIG. 2, the barrel shifter 18-2 is controlled by the CPU
Performs bit shift processing in place of IK. Further, since the barrel shifter 18-2 rotates word data, the data to be shifted and written to the next address is masked bit by bit by the mask controller 18-9 to prohibit writing. Since then, by using the process shown in hi, it has become possible to display the character pattern ``character'' with two word string commands.

In addition, when displaying the character pattern of the first character "Kan" shown in FIG. 8, the read data from the CG14 is 8 bits on the left side and 6 bits on the right side as shown in the conventional If the screen memory 20 is read out by dividing into
The first side memory control circuit 18
Even if A, B%C is used as shown in the lower part of Figure 8,
The word write process had to be performed three times for each area. However, using the CG readout control circuit 19 shown in FIG. 5 in this embodiment, the CG readout control circuit 19 shown in FIG.
It is possible to divide the image into two areas and display it by performing word writing twice.

In this way, the first side memory control circuit 18 and C
It is clear that by combining the G readout control circuit 19, dot data of a single character pattern can be displayed at a higher speed than before.

In addition, in the above embodiment, the CPU II is 80
86 was used to illustrate the effect of a string instruction, but a similar effect can also be produced by DMA transfer between memories. Therefore, it can also be realized by CPUs other than 8086.

〔Effect of the invention〕

According to the present invention, by supplementing the processing of reading dot data of a character pattern from a character generator, writing it to an arbitrary position in the screen memory, and displaying it at an arbitrary position on the display screen, using a dedicated circuit, the CPU can be used at high speed. Available in a variety of forms. Further, writing to memory in bit units becomes faster not only when displaying character patterns but also when drawing figures.

The above means that the display processing time can be shortened in the display device fi using the CPU, resulting in improved operability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit of a display device according to the present invention, FIG. 2 is a block diagram showing details of a screen memory control circuit, and FIG. 3 is an explanatory diagram showing an address structure of a screen memory according to the present invention. Figure 4 is an explanatory diagram showing how character pattern dot data is stored in the character generator, Figure 5 is a block diagram showing details of the character generator readout circuit, and Figure 6 is a diagram showing character pattern dot data read out according to the present invention. FIG. 7 is an explanatory diagram showing the relationship between address and data when character pattern dot data is read in the conventional case. FIG. 8 is character display processing according to the present invention. FIG. 2 is an explanatory diagram showing data in the mFffi memory for explaining the process. 11...CPU, 14...Character generator, 18...Screen memory control circuit,
18-2... Barrel shifter, 18-3...
...Write controller, 18...Mask controller, 19...CG readout control circuit, 20
......: Field memory, 24...CRT monitor. Figure 2 +8: t6 side f mo, sumy box 1 78-2: Barrel shifter IB-3 Nilight controller/8-9: Mask controller Figure 3 Sleep: CPU? Bottom of dress 1 ku: CRT address Figure 4 Figure 5 ψ

Claims (1)

[Claims] 1. A character generator that stores dot data of a character pattern composed of a 24 x 24 dot matrix, a display that displays an image in a dot matrix, and a storage element that corresponds to one dot for each dot of the image displayed on this display. a bitmap type screen memory having a bitmap type screen memory; a CPU that executes control to read dot data of a character pattern from the character generator and store it in the screen memory; In an image display device equipped with a display control circuit for supplying data to a display device, the character generator divides each set of dot data into byte units in the scanning line direction from 24×24 dot data into an arrangement of scanning lines in byte units. It has a memory for storing 24 bytes in parallel in consecutive addresses in the direction, the screen memory is configured to have the address order in the direction in which the scanning lines are arranged, and the 24×24 dots stored in the character generator A character generator read control circuit reads out either the left 16 bits or the right 16 bits in the scanning line direction in units of 16 bits according to instructions from the CPU, and a
A barrel shifter that shifts the amount of bits according to the shift amount command value given from the PU, a mask controller that generates mask data that limits the write range of dot data given from the CPU side, and a dot read out from the screen memory. An image display device comprising: a write controller that combines data and dot data output from a barrel shifter according to mask data to create new write dot data.