JPS62133487A - Linear drawing system for display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a graphic drawing method in a bitmap display, and in particular to a method for drawing straight lines at high speed.
This invention relates to such a straight line drawing method.

[Background of the invention]

Conventionally, there is an invention as described in Japanese Patent Application Laid-Open No. 101696/1983 as a means for realizing raster operations at high speed. Since the processing speed of raster operations is greatly influenced by updating the contents in the graphic memory, the invention as described above is extremely useful.

However, drawing a straight line on a display requires two processes: generating dots on the straight line and writing the generated dots into the graphic memory. Usually, the above dot generation is sped up using hardware.

In other words, the above invention is based on CAD (Computer A).
It was intended for use with relatively expensive systems that require fairly sophisticated graphics, such as IDEdDesign.

Word processors and intermediate personal computers
The generation of dots on a straight line is performed by software, and the CPU writes the generated dots into the graphic memory, so the processing speed of graphic drawing is slow.

In particular, as high-definition CRTs are used for displays, the insufficient processing speed of graphics has become noticeable, but the above invention is not cheap enough to be applied to low-cost equipment such as word processors. Therefore, there was a need for an inexpensive, high-speed linear drawing method that could be applied even to low-cost systems.

Next, a conventional technique for generating dots on a straight line (straight line generation) using software will be explained.

Figure 9 shows a general KDDA (Digital Diffe)
This is a flowchart showing a conventional program for drawing straight lines using an algorithm called a rental analyzer (digital differential analyzer).

In other words, in the same flow, the starting point coordinates are (x, yL, the length in the X direction is Δx, the length in the y direction is Δy, and ΔX≧Δy>O
This is a program file p- that generates (draws) a straight line when the following conditions are met.

This program sequentially generates (draws) coordinates (XI, yi) on a straight line. Here, 1≦i≦ΔX, and xj−
xj-1+1 (2<J<Δx, x1-x). In step 81 in the figure, if the value of e is larger than O, yH increases by one from the value of Yi-j, but if the value of e is thicker than 0 (then it is the same value as Yi-1). Chiru.

The algorithm used in this program is simple and does not require complicated calculations, so the coordinates of each point on a straight line can be calculated relatively quickly.
In the drawing process of drawing a point at the (x, y) position in FIG. 10, as shown in steps 1001 to 1004 in FIG. It is necessary to rewrite only the bits and write them into the graphic memory again, and the above-mentioned process from generating the (x, y) coordinates to updating the data in the graphic memory must be repeated Δχ times. If all of these processes are executed by the CPU, high-speed processing cannot be expected.

Another conventional method for generating straight lines is a method called the Run Length method. The flow of a program for straight line drawing processing using the Run Length method is shown as a program 700 in FIG.

In this method, when drawing a straight line as shown in FIG. 12, first the starting point coordinates (x+y) and length t of the horizontal line segment 900 are calculated, and then, in step 90 of FIG. Draw a point.

The details of the point drawing process seen in step 90 are explained in the first section.
This is shown in subroutine 800 in FIG. Step 1 in Figure 8
The processing of step 00 is exactly the same as the processing of step 80 in FIG.
This is the process shown in 0.

Above, we have briefly explained two methods of generating (drawing) straight lines using software that have been known in the past.
As explained above, in either method, many steps are required to draw the coordinates of each point on the straight line (pit processing), and as long as these steps are executed by the CPU, it is possible to draw the coordinates of each point on the straight line at high speed. The drawback was that the drawing quality was unpredictable.

In addition, previously proposed inventions that use hardware to improve the slowness of straight line drawing by software and speed it up are applicable to high-end equipment (expensive equipment
As previously explained, it is difficult to apply this method to low-cost equipment such as word processors and intermediate-level personal computers due to cost considerations.

[Purpose of the invention]

In view of the conventional technical circumstances as described above, the present invention
Therefore, the object of the present invention is to provide a display using hardware that is low in cost enough to be applied to low-cost equipment such as word processors and intermediate-level personal computers, and that can be expected to perform high-speed straight line drawing. The purpose of this invention is to provide a straight line drawing method for

[Summary of the invention]

In the present invention, the maximum length that can be written to the graphic memory at once is 16 bits per word, which is the line segment obtained by the Run Length method (that is, the starting point BAA x t y and the length from there). The conventional Run Le
In addition to utilizing the advantages of the NGTH method, the writing operation to the memory is made more efficient, and as a result, a high-speed straight line drawing method is realized.

Add some explanation. What is the algorithm for straight line generation?
There is one type, but the one based on DDA described above is particularly famous and is implemented in many systems. Other algorithms include Run Len, which was also explained earlier.
There is one that uses gth, and this Run Lengt
The h method is a horizontal line that makes up a straight line.

Since the length of the vertical line is generated one after another, the number of repeated calculations is often smaller than the DDA method, which generates one dot at a time, and is particularly advantageous when straight lines are generated by software.

However, currently, in order to expand the line segment determined by Run Length into the actual graphic memory, it is necessary to use the CP
Bit processing (drawing processing) by U is essential, but C
As mentioned above, bit processing by the PU takes time, so the advantages of the Run Length method cannot be effectively utilized.

Therefore, in order to solve this problem, the present invention provides a means for rapidly expanding a given line segment into a graphic memory.
It can be said that we have developed and proposed hardware that has a relatively small circuit scale and low cost.

[Embodiments of the invention]

The present invention will now be described in detail with reference to the drawings.

First, assuming that the present invention is applied to a word processor, an outline of the configuration of the word processor will be explained with reference to FIG.

That is, FIG. 2 is a block diagram showing an example of the hardware configuration of a word processor to which the present invention is implemented. 25 within the broken line in the figure shows a block diagram of the control section of the word processor.

This control unit 25 includes a host CPU (central processing unit) 25
1. Boot R has a program that runs when the power is turned on.
OM 252, a memory 253 (hereinafter referred to as RAM) that can be read and written at any time to store programs and information for executing functions such as a word processor;
A C that generates a screen display pattern according to instructions from the host CPU 251 and sends a video signal to the CELT monitor 23.
RT display device 254, host) A floppy disk controller (FDC) 255, which controls the floppy disk drive (FDD) 24 according to commands from the CPU 251, sends signals to control the printer 22 and print signals to the printer 22 according to commands from the CPU 25f. The host CPU also receives the status signals of the printer 22 from the printer 22.
The keyboard 21 is controlled according to the commands from the printer controller 256 and the host CPU 251, which are sent to the printer controller 251.
A key controller 257 that sends input signals from the keyboard 21 to the host CPU 251, the host CPU 251, the boot ROM 252, the program memory 255, the CRT display device 254, the disk controller FDC 255, and the printer controller 256.
, and an internal wiring path connecting the key controller 257.

In the word processor configuration described above, the present invention is applied to the CFLTfi display device 254.

Therefore, as an embodiment of the present invention, the CRTff display device 25
A detailed block diagram of this is shown in FIG.

The CRT display device 254 shown in FIG. 1 includes a CPU 111 that controls the entire device, a clock generator 112 that supplies necessary lock signals to the CPU 111, and an address signal that sequentially reads out the contents of the graphic memory VRAM 117. A CRT controller 113 that generates a synchronizing signal to control the CELT monitor 23, a shift register that converts data read from the graphics memory VRAM 117 into a serial video signal, and a CR
Synchronizing signal from T control 4-2113 to CRT monitor 2
Peripheral control circuit 114 consisting of a driver etc. supplied to
, a CRT that displays a screen by receiving video signals and synchronization signals
The monitor 23, the memory peripheral control circuit 116 that controls access to the graphics memory VRAM 117, the graphics memory VRAM 117 that exists as a bitmap corresponding to one image bit on the screen and is composed of dynamic RAM, and that controls access to the graphics memory VRAM 117 in response to external events. CPU
An interrupt controller 118 that gives an interrupt signal to I11 and branches the program, a control register 119 that holds control information such as shift read and write control dots, and a controller for the memory 122 and character generator CG123.
'Access from PU111 and host CPU in Figure 2
251, a dynamic RAM controller 121 that controls generation of multiplexed address signals to the memory 122 and refresh operations, a dynamic RAM 122 that holds programs and data, kanji characters, A character generator CG125 consisting of a ROM that stores kana, alphanumeric characters, etc. in a dot matrix pattern, and a CPU 111
and a bit logic circuit 124 (hereinafter abbreviated as BLU) located between the same-side memory control circuit 1160 and the same-side memory control circuit 1160.

This BLU 124 is hardware added according to the present invention.

The host CPU 251 in FIG. 2 and the OCaT display device 254 in FIG.
CPU 111 of RT display device 254, CELT controller 113, memory peripheral control circuit 116, interrupt controller 118, control register 119, collision control circuit 120
CPU bus b interconnects the signals 11 and 11.
Access signals from Ja and bus b are multiplexed to create a DRAM.
Controller 121 and character generator CG12
The memory path C given to 3 is 6.

d*e*g are signal lines consisting of control signals, addresses, and data, and f is a data line.

Next, BL, which is the software added according to the present invention,
The configuration of U 124 will be explained using FIG. 3.

FIG. 3 is a block diagram showing details of the BLU 124 in FIG. 1, and is also a diagram for explaining the flow of data from the CPU 111 to the graphic memory VRAM 117.

See Figure 3. The BLU 124 includes a CPU 11, registers 61 and 68 that latch data from the graphic memory 117, and an arithmetic circuit 62. Specify the shift circuit 63, selection circuit 64, shift amount and type of operation, and select the selection circuit 6.
The control signal generation circuit 65 supplies a selection signal to the circuit 4.

Inside the control signal generation circuit 65, there is a register that holds control information given from the CPU 11.
In the figure, these registers and transfer paths for transferring information to the registers are omitted.

66 is an address line from CPU bus b, and 67 is a data line. In this figure, the signal lines d, e, and H in FIG. 1 are divided into data lines and address and control lines.

CPUt j 12>! /97(ツ/Memo!jVRAM
When data is written to 117 in the read-modify-write mode, the write data is latched in the register 61, and the output A of the register 61 is determined by the shift amount (CPU1
11 through a transfer path (not shown) to the control signal generation circuit 65, the data is shifted by a predetermined amount in the shift circuit 63 according to the shift amount determined by this information. The output becomes C.

On the other hand, prior to including data 8I, graphic memory V
The data read from the RAM 117 is sent to the arithmetic circuit 62.
is applied to the selection circuit 64 (B in the figure).

The arithmetic circuit 62 performs bit operations on the outputs C and B, and outputs the result as D. A selection circuit 64 replaces a specific number of bits of data B read from the graphic memory 117 with corresponding bits of the operation result, and the result E becomes an input to the graphic memory 117 via the memory peripheral control circuit 116.

Furthermore, the flow of data within the BLUI 24 in FIG. 3 will be explained in detail using diagram M4. A- in Figure 4
Ei[3 shows the contents of data of input/output lines A to H of each block in FIG.

A is source data given from the CPU 111,
It is assumed that only the WNN pits from the beginning of one word (for example, 16 bits) are valid data.

Here, the bit position information indicating where the first bit position is is the same (separately given from the CPU 111. This source data WN bit and the WN bits starting from the DNth bit of data B read from the graphic memory An operation is performed with the content (b2), and b2 in data B is replaced with the result of the operation to obtain data E.

Therefore, the contents of bl and b3 of data B must remain unchanged. First, source data A given by the CPU 111 is latched into the register 61. Thereafter, the shift circuit 63 determines the DN determined by the bit position information mentioned above.
The output of the shift circuit 63 is shifted to the right by one bit, and the output of the shift circuit 63 is C.
It will look like this.

An operation is performed between data C and data B to obtain data D, but the data to be written into the graphic memory 117 must be E. Therefore, the selection circuit 64
Is required.

The control signal generation circuit 65 generates mask data indicated by M based on the information of DN and WN given from CPtJll, and this generates a selection instruction signal (
@Figure 3 signal! M).

Data D and B are input to the selection circuit 64. When the bit of mask data M is 00, the contents of B are input as the corresponding bits of the graphic memory, and when the bit of M is 1, the contents of D are input. The selection circuit 64 selects each of them, and creates and outputs data E as a result.

The following processing is performed by the graphic memory 1 of the CPU 111.
17 during memory access in read-modify-write mode.

FIG. 5 is a circuit diagram showing a specific example of the arithmetic circuit 62 in FIG. 3. In the same figure, 91.92 is a selector,
93 is an AND element, 94 is an EOR (exclusive OR) element,
99 is a NOT R child.

With such a simple circuit configuration, data C from CPU111
16 types of binary logical operations as shown in FIG. 5A can be performed between the data B read from the graphic memory 117 and the data B read from the graphic memory 117.

95 and 96 are operation designation control signals (each consisting of 4 bits).
At F) in Figure 3, you can select 16 different types of Pi.

Further, DI represents the output C from the shift circuit 66 in FIG. 3, and DSi is data B (B in FIG. 3) read from the graphic memory 117.

The selectors 91 and 92 select I)t*Di, a signal 98 which is always at a high level, and a signal 97 which is always at a low level.
One of the signals of the 1il class is selected.

The outputs Ri and DRi of selectors 91 and 92 are set to 1 by 95°96, each of which is a 4-bit operation designation control signal.
6s types of combinations are possible, thereby making possible the 16 types of calculations shown in FIG. 5A. The calculation result OPi becomes an input to the selection circuit 64 (D in FIG. 6).

In normal memory transfer, that is, when data from the CPU 111 is written directly to the graphic memory 117,
DNt-DN- as control information given from the CPU 111 via a route not shown.

It is sufficient to specify the bit length of 1 word (or 1 byte) in WN as , and specify the operation so that the operation result OPi becomes Di.

When the CPU 111 reads data from the graphic memory 117, it does so without going through the BLU 124, and the data read from the graphic memory is directly loaded onto the data bus b of the CPU 111 in the same way as in a normal read operation.

The hardware configuration of a word processor embodying the present invention has been described above with reference to FIGS. 1 to 5 and 5A.

In a word processor with such a configuration, as shown in FIG. 2, based on instructions from the host CPU 251,
The CPU 111 in the CRTfi display device 254 generates straight lines, arcs, characters, etc., and develops them in the graphic memory 117 as bit images. Programs for generating figures and characters are stored in the memory 122, and the CPU 2 (host)
Commands from 51 are also written into memory 122.

The hardware configuration as shown in Fig. 1, that is, CPU1
In the hardware configuration in which the BLIJ 124 is installed in the data transfer path between the graphics memory 117 and the graphics memory 117, there is no need to generate the coordinates of each point on the straight line when drawing a straight line. Run
By utilizing the advantages of the Length method, it becomes possible to draw straight lines at high speed. The straight line drawing method will be explained below.

FIG. 6 is a flowchart showing a subroutine (corresponding to the process of step 90 in FIG. 11) made possible by implementing the present invention.

In the same subroutine 1100, first step 111
0, the word address of the graphic memory VRAM 117 and the pit position within the word are calculated from the given starting point coordinates (x*y). If the straight line segment to be generated does not fit within one word length (16 dots), this is determined in step 1120, and the process proceeds to step 1150; if it does, the process proceeds to step 1130.

In step 1130, the pit position (B
ST) and bit length (dot length) 1/.

In FIG. 4, they are WN-1' and DN-BST.

At step 1140, the graphics memory (VRAM) 1
When the CPU 111 writes the pattern data (A in FIG. 4) to i7, the BLU 124 actually writes the data E (dot length WN in the D1 part) in FIG.
is written, and as a result, a straight horizontal line segment (dot length) that should have been written is written in one memory write operation.

Now, the line segment (dot length) t' is 1 word long (16 dots)
If the length is longer than
Write to AM117.

That is, in step 1150, the bit position of BLU 124 is set to BST, and the bit length is set to (t'-88
T) Set K and write the pattern data into the graphic memory VRAM 117 (step 11).
50.1160).

Next, the length of the newly written line segment is subtracted from the length of the line segment to obtain the length of the line segment for which writing has not yet been completed (step 1170).

Since writing of subsequent line segments always starts from the first bit position, the pit position of BLU 124 is set to 0, and the maximum length is 16 (as mentioned again, it is assumed that one word is 16 bits). Set to bit length. t'
If is larger than 16, the loop from step 1190 to step 1220 is divided into line segments each having a length of 16 dots and written into the graphic memory 117.

Updating the address in step 1200 corresponds to updating the X coordinate. When t' reaches 16, step 1230~
Through the process 1250, the remaining line segments are written into the graphic memory 117, and the process ends. At this time, in step 1230, the bit length of the BLU 124 is set to t'.

As explained above, in the straight line drawing method according to the present invention, the CP
U111 does not need to be conscious of all bit processing; it only needs to perform the same operation as writing data to the graphic memory VRAM117.

For a straight line (typically a vertical line) that satisfies the condition of Δy>ΔX as shown in Figure 7, by slightly modifying the program 700\ in Figure 11, the black-filled vertical line 910 in Figure 7 can be obtained. Starting point of the line segment (x.

y) and the length t can be calculated.

In this case, this vertical line segment cannot be written all at once, but by replacing the processing in step 90 of the program 700 in FIG. 11 with the subroutine 1300 shown in FIG. 8, high-speed drawing is still possible.

In step 1320, the bit position and length t' are set to BLU1.
Set it to 24. Graphic memory VR in this state
CPU1 performs the operation of writing pattern data to AM117.
If 11 is performed, only one dot will be written at the position of bit BST, and if this pattern data is written 27 times while updating the address, the writing of the vertical line segment will be completed.

If the addresses of the graphic memory VIIAM 117 are assigned consecutively in the y direction, and the CPU 111 has instructions like the string manipulation instructions of the Intel 8086, the string manipulation instructions can be effectively used for straight line drawing, resulting in faster speeds. processing can be performed.

〔Effect of the invention〕

According to the present invention, whereas conventionally a straight line was generated by calculating the coordinates of each point and writing them into a graphic memory, the straight line is generated in minute line segment units (one word length unit). Because it is now possible to calculate the length of a line segment to be written to the graphic memory and to draw the calculated unit length line segment in a single access operation to the graphic memory, straight lines can be drawn extremely quickly.

For example, when generating a straight line as shown in FIG. 9, in the conventional method, the number of times the coordinates are generated and the number of times the graphic memory is accessed are Δχ and 2Δχ, respectively. The number of occurrences is 31, and the number of accesses to the graphic memory is Δy+(Δx/(16
*Δy)] *Δγ times ([X] is the largest integer that does not exceed As a result, straight lines can be drawn faster.

Moreover, the hardware necessary to realize the present invention is
An LSI (BL
U), and the present invention can be implemented at almost the same cost as conventional devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an outline of the configuration of a word processor to which the present invention is applied, and FIG. 3 is a block diagram showing the configuration of a word processor to which the present invention is applied. Block diagram showing details of
4 is an explanatory diagram of the circuit operation of the BLU 124 in FIG. 5, FIG. 5 is a circuit diagram showing a specific example of the arithmetic circuit 62 in FIG. Fig. 6 is a flowchart showing a subroutine (corresponding to step 90 in Fig. 11) made possible by the implementation of the present invention, and Fig. 7 shows an example of a straight line that should be generated. 8 is a flowchart showing an example of a subroutine that can be taken as step 90 in FIG. 11, FIG. 9 is a flowchart showing a conventional straight line drawing program, and FIG. Flowchart showing details, 1st
FIG. 1 is a flowchart showing another conventional program for drawing straight lines, FIG. 12 is an explanatory diagram showing an example of a straight line to be drawn, and FIG. 13 is a flowchart showing details of step 90 in FIG. 11. Explanation of symbols 254... (4T display device, 111...
・CPU. 124...Pit logic circuit (BLU), 1
17...Graphic memory VRAM, 700
, 1100.1300... An example of a program that implements the present invention. Agent Patent Attorney Akira Namiki Fusuki 2 Figure b 114 Figure 5 Figure 6 Figure 117 Figure gs Figure 1@0 Figure (Fukuyama finished) Figure 10

Claims (1)

[Scope of Claims] 1) A graphic memory for storing an image to be displayed as a dot image, and each pixel being set as a bright point or a vanishing point corresponding to the dot image stored in the graphic memory. a bit map display for displaying the image, and a CPU (central processing unit) as a transfer means for specifying an image to be displayed in the graphics memory and transferring the image data to the graphics memory. In the display device, the C
A bit logic circuit consisting of the following elements is installed in the image data transfer path from the PU to the graphics memory.
When the image to be displayed is a straight line, a straight line drawing method for a display is characterized by making it possible to draw the straight line at high speed. (b) holding means for capturing and holding the straight line data transferred from the CPU together with the write address of the starting point coordinates in the graphic memory and information representing the bit position in the word of the address; means for reading data from the graphic memory using the transferred address as a read address; (c) means for reading data from the graphic memory using the transferred address as a read address; (d) means for transmitting the result of the logical operation for writing into the original address location of the graphics memory;