JPH0721757B2 - Information processing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to information processing suitable for realizing high-speed updating of data in a graphic memory forming a display device such as a word processor or a personal computer. Regarding the device.

[Background of the Invention] Conventionally, CAD (Computer Aidesd Desig)
In the world of abbreviation, CPU (Central Processing Unit = Central
An apparatus for performing a logical operation between data from an abbreviation of Processing Unit) and data in an image memory and writing the result in the image memory is used. JP-A-59-101696 discloses such an example. The invention described in Japanese Patent Application Laid-Open No. 59-101696 can speed up the operation in word units, but requires CPU processing for bit unit processing. With the recent spread of bitmap displays, it is necessary to rewrite memory in bit units. In Japanese Patent Laid-Open No. 59-90156, a CPU for rewriting data in bit units using a shift register or a mask resist is disclosed. The invention that alleviates the burden of the above is described, and it is shown that the speeding up of bit processing greatly affects the efficiency of the processing speed.

[Object of the Invention] An object of the present invention is to use a general-purpose microprocessor and a data select type bit shift to instantaneously update data stored in a graphic memory to perform copy and move processing at high speed. It is intended.

[Summary of the Invention] Due to the remarkable development of LSI technology in recent years, the degree of integration of storage elements has been dramatically improved, and the price has been very low. Along with that, one of the display devices such as CRT disc play
Allocate some storage elements for dot information,
Bitmap display is also being actively developed. The display figure is changed by rewriting the information stored in the storage element corresponding to the dot to be changed. Normally, the amount of information corresponding to one dot is 1 byte which is a unit for reading or writing the storage element. Therefore, it is necessary to perform an operation of reading information from the storage device in units of 1 byte or 1 word, rewriting only necessary bits, and writing again in the storage device. In the graphic processing required for a personal computer or a word processor, the processing applied to the graphic is often simple such as copying, moving, and overwriting of two graphics, and logical product, logical sum, exclusive logical sum, etc. In many cases, simple operations are repeatedly performed on many pieces of data. Therefore, if a device for performing these logical operations is placed on the data paths of the central processing unit and the storage device and a dispute operation is performed in the process of transferring data from the central processing unit to the storage device, it is considered that the processing speed will be dramatically improved. .

Focusing on the fact that many storage devices have a read-modify-write function in addition to the simple write and read modes, the data read from the storage device is read and written between the read-modify-write and the write. By performing the data operation given from the central processing unit and writing the result, the memory can be rewritten by only one write operation from the viewpoint of the central processing unit. It is absorbed in the access time to the storage device, and rewriting of graphic information can be performed very quickly.

The present invention is based on the present situation and concept, and the first means for transferring data, the second means for storing data, and the second half of the data writing cycle to the second means by the first means In an information processing device having read-modify-write control means for reading data from two means and writing this data to the second means in the latter half of the data write cycle, in the data transfer path of the first means and the second means, A data select type bit shift means for shifting the data from the first means in bit units, a bit conversion means for converting only designated bits of the data read from the second means, and a control signal generation for controlling these. Means for writing data from the read-modify-write mode to the second means when the first means writes data from the first means in the first half of the write cycle. Data is shifted by a predetermined amount by the data select type bit shift means, only predetermined bits of the data read from the second means are converted based on the shifted write data, and the converted data is the latter half of the write cycle. The information processing apparatus is characterized by writing to the second means.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example in which the present invention is applied to a word processor will be described in detail with reference to the drawings.

As shown in FIG. 2, a word processor using an embodiment of the present invention includes a main body 20 having a temporary storage unit and a control unit, a keyboard 21 as an input unit, a printer 22 as a printing unit, and a CRT monitor as a display unit. It is composed of 23, these main body 20, printer 22, keyboard 21 and CRT monitor 2
3 indicates the cables 201 to 203, respectively, as shown in FIG.
The control signal or the information signal is transmitted and received through the. In FIG. 2, reference numeral 24 is a flexible disk drive device (hereinafter referred to as FDD).

In the main body 20, a control unit 25 within a broken line in the control circuit shown in the block diagram of FIG. 3 is installed. That is, the control unit 25 includes a host CPU 251 including a central processing unit (hereinafter, referred to as CPU), a non-volatile memory (hereinafter, referred to as ROM), a put ROM 22 having a program to be executed at power-on, and a function as a word processor. A memory that can be read and written at any time to store programs and information for executing
Called RAM. ) Consisting of program memory 253, host CP
A CRT display device 254 that generates a screen display pattern according to a command from U251 and sends a video signal to the CRT monitor 23, a host
Flexible disk control circuit (hereinafter referred to as FDC) 255 for controlling FDD 24 according to a command from CPU 251 and host CPU 251
The printer controller 256, which sends a signal for controlling the printer 22 or a print signal to the printer 22 according to the command of, or receives the status signal of the printer 22 from the printer 22 and sends to the host CPU 251, controls the keyboard 21 according to the command of the host 251, A key input controller 257 for sending an input signal from the keyboard 21 to the host CPU 251 and the Hoist C
The internal wiring path d connects the PU 251, the put ROM 252, the program memory 253, the CRT display device 254, the FDC 255, the printer controller 256, and the key input controller 257.

Here, the FDD 24 drives a flexible disk of a magnetic storage medium to record information from the flexible disk and read out the information from the flexible disk. Section is provided.

Next, the overall operation of the word processor will be described with reference to FIG. That is, when the power is turned on in the above-described configuration, this device operates as a word processor having the flow as shown in FIG. 4 stored in the flexible disk set in the FDD 24 according to the program in the boot ROM 252. Is moved to the program memory 253, and after the screen is turned off, the operation as a word processor is started according to the program moved to the program memory 253. Furthermore, it will be described later at the same time.
A program for the CPU 111 that controls the CRT display circuit 254 to perform the CRT display operation is also transferred from the flexible disk stored in the FDD 24 to the memory 122 described later.

In the data processing flow in FIG. 4, a processing start message as a word processor and an executable processing work menu are displayed in the processing step 401 by the CRT monitor 2.
3, the work menu selection input designated by the keyboard operation by the operator is read in at step 402. In processing step 403, it is determined whether the designated work is an input processing work, in processing step 404 it is determined whether the designated work is an edit processing work, and in processing step 405 it is determined whether it is a print processing work. In step 406, it is determined whether or not it is an auxiliary function processing work, and the processing branches from each processing step to the corresponding processing work 407 to 410, and if none of them, the processing returns to processing step 401. The auxiliary function is a general term for functions in which document data in a flexible disk is copied to another flexible disk.

When the input processing 407 is selected by the work menu selection input, the host CPU 251 executes the input processing program having the data processing flow as shown in FIG. The document data during the input process is sent as a command or data through the CRT display circuit 254 signal line a according to the program for executing the input data process shown in FIG. The circuit 254 creates an image pattern, converts it into a video signal, and outputs it to the CRT monitor 23.
And display an image on the tube surface of the CRT monitor 23. The command for processing accompanying the input of data to the document data is performed according to the data or function instruction input from the e-board 21.

In the data processing flow shown in FIG. 5, a processing step 501 displays the format setting items of the input document on the CRT monitor 23, and a processing step 502 reads the setting input inputted by the operator from the keyboard. In processing step 503, the input according to the above settings displays a surface. Processing step 50
At 4, the data input from the keyboard 21 is read and displayed at process step 505. In processing step 506, it is judged whether or not there is an input to finish the data input work. If it is not finished, the processing returns to processing step 504, and if it is finished, the processing proceeds to processing step 507 to execute the termination processing and the fourth data processing. Return to flow. The end process 507 is a process of writing the input data to the flexible disk and storing it.

When only displaying characters on the CRT display device 254, the unit of data given to the CRT display numerical value 254 by the host CPU 251 is one line on the screen according to the instruction of the program stored in the program memory 253. This is the data for displaying the minutes. That is, host CPU2
The numeral 51 is for sending one line of data with a new display character added to the end of the line to the CRT display device 254 through the signal line a in response to character input for each character input from the keyboard 21.

The operator inputs characters one by one, but the host
Since the CPU 251 and the CRT display device 254 have to perform the display process of one line of data, the input process in the host CPU 251 and the drawing process on the screen in the CRT display device 254 are instantaneous to the operator. Must be done.

After that, by repeating this operation until the end of data input is instructed, the input data will be displayed on the CRT monitor 23.
Is displayed in.

When an instruction to end data input is input from the keyboard 21, the host CPU 251 detects this and executes end processing to end the input processing as shown in the flow of FIG. 5, and as shown in the flow of FIG. It prepares for the next processing.

The end in FIG. 5 is a process of writing the input data to the flexible disk and temporarily storing it.

In the editing process 408 of FIG. 4, the screen display data is rewritten according to the function key input from the keyboard 21. Even in other processing, work instructions, progress, etc. are displayed on the CRT monitor 23.

Next, a CRT display device 254 according to an embodiment of the present invention will be described.

FIG. 1 shows a block diagram of a CRT display device 254 which is an embodiment of the present invention. The CRT display device 254 shown in FIG. 1 is a CPU 111 that performs overall control (for example, an Intel 8086 or 8088 is suitable), and a clock generator 11 that supplies signals such as a clock necessary for the CPU 111.
2. A CRT controller 113 that generates an address signal that sequentially reads the contents of the graphic memory 117 and that generates a synchronization signal that controls the CRT monitor 23. A shift that converts parallel data from the graphic memory 117 into a serial video signal. A peripheral control circuit 114 including a register and a driver that supplies a synchronization signal from the CRT controller 113 to the CRT monitor 23, a CRT that receives a video signal and displays a screen
The time-division control circuit 116 that sends out the data from the monitor 23, the access signal from the CPU 111 and the access signal from the CRT controller 113 to the graphic memory 117 by time-divisionally controlling them, and the image bit of the screen. Storage element exists as 1 bit map of 12
8 kilobytes (64 kilobits x 16 bit words, but CPU
Are accessed in 8-bit byte units. ) Graphic memory consisting of dynamic RAM 1
17, the host shown in FIG. 2, which is the upper level of the CRT display device 254
An interrupt controller 118 that gives an interrupt signal to the CPU 111 and branches the program in response to an event from the CPU 251 or the outside,
An access signal from the CPU 111 to the control register 119, which holds control information such as shift read and write control bits, a memory 122, and a character generator unit (hereinafter referred to as CG) 123, which will be described later, and an access signal from the host CPU 251 in FIG. Collision prevention control circuit 12 designed for multiple control
0, a DRAM controller 121 that controls the generation of a multiplexed address signal to the memory 122 and a refresh operation, a dynamic RAM 122 (hereinafter referred to as DRAM) that dynamically retains memory, kanji, kana and alphanumeric characters, etc. CG123 consisting of ROM to store in, bit logic circuit 124 located between CPU111 and memory peripheral control circuit 116
(Hereinafter referred to as BLU).

The host CPU 251 and the CRT display device 254 in FIG. 3 are connected by a control signal and a data signal line a, and the CPUs 111 and C of the CRT display circuit are connected.
The CPU path b interconnects the RT controller 113, the time division control circuit 116, the interrupt controller 118, the control register 119, and the collision control circuit 120, and further multiplexes the access signal of the signal line a and the bus b. DRAM controller 121
There is a memory bus c that gives to CG123.

Next, the configuration and function of the BLU 124 will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram for explaining the flow of data from the CPU 111 to the graphic memory 117, and the data bus, address, etc. from the memory peripheral control circuit 116 and the peripheral control circuit 114 are omitted. BLU124 is CPU111
Register 61 for latching data from the processor, arithmetic circuit 62, barrel shift circuit 63 using a data selector, selection circuit 64
And a control signal generation circuit that supplies a selection signal to the selection circuit 64 by designating the shift amount, the data width to be converted, and the type of operation.
It consists of 65. Inside the control signal generation circuit 65, there are registers for holding control information given from the CPU 111, but in FIG. 6, those registers and the transfer history for transferring information to the registers are omitted. The control information is
The bit constant method DN for controlling the shift amount and the data width to be converted, the bit width information WN, and the operation information for specifying the type of operation for conversion. 66 is CPU1
An address bus from 11 and a data bus from the CPU 111.

When the CPU 111 writes data to the graphic memory 117 in the read modify write mode, the write data is latched in the register 61, and the output data A of the register 61 is shifted according to the shift amount determined by the control signal generating circuit 65. The output data C is shifted by a predetermined amount by the circuit 63. While graphic memory
The data is read from 117, and the arithmetic circuit 6 is used as the data B.
2 and the selection circuit 64. The arithmetic circuit 62 performs a bit operation on the data C and B, and outputs the result as data D. Selector 64 for data D and graphic memory
The data read from 117 is selected bit by bit, and the resulting data E is input to the graphic memory 117.

The data flow in the BLU 124 will be described in detail with reference to FIG. The data A is the source data given from the CPU, and only the bit width information WN bits of one word are valid data. The specified type of operation is performed between the WN bit of the source data A and the WN bit content (b2) starting from the bit constant modal DN bit of the data B read from the graphic memory, and the operation result is b2. Replace. Therefore, the content of b1 in the figure must be unchanged.
For this processing, the data A is first latched in the register 61. After that, the shift circuit 63 shifts the DN bit, and the shift color of the shift color 63 becomes like the data C. An operation is performed between the data C and the data B to obtain the data D, but the data to be written in the graphic memory 117 must be E. Therefore, the selection circuit 64 is required. The control signal generation circuit 65 generates mask data M based on the information of DN and WN, and supplies this to the selection circuit 64 as a selection signal. The data D and B are given to the selection circuit 64 as input data, and the selection circuit 64 corresponds to the graphic memory 11 when a certain bit of the mask data M is "0".
If the content of data B is "1" for the 7th bit, the content of data D is selected and output.

As can be seen from the above description, the write operation of the CPU 111 to the graphic memory 117 is performed in the read modify write mode. An example of the read-modify-write timing will be given below. CLK is CPU111
System clock, ALE indicates an address buffer latch clock, and ADRESS and DATA indicate outputs of the CPU 111 address bus and data bus. BDL is a latch clock of the register 61 shown in FIG. If BDL can be generated only by a read / write control signal using a D-type flip-flop 81 as shown in FIG. 9, for example, the CPU111 will write regardless of the value of the address output by the CPU111. Data is set in the register 61 at any time.
Of course, the BDL can be generated only when the CPU 111 writes to the graphic memory 117. DRAMD
ATAO is output data from the graphic memory 117, and DRAMDATAI is input data to the graphic memory 117. Therefore, the calculation time allowed for the calculation circuit 62 is Tw, and after the data is set in the register 61, the BLU124
All processing in must be completed during Ts,
Normally Tw is about 100nSEC and Ts is about 300nSEC, so the processing time is sufficient. In the description of FIG. 8, the reading of the data of the Glaffic Memoro 117 from the CRT monitor 23 is not considered, but in actuality, the access conflict between the CPU 111 and the CRT monitor 23 is considered when controlling the memory. This is a very important issue.

FIG. 10 shows an example of the arithmetic circuit 62. 91 and 92 are selectors, 9
3 is an AND element 94 is an EOR element, and 99 is a NOT element. With such a simple circuit configuration, the data between the CPU 111 and the data read from the graphic memory 117 are shown in Table 1 below.
Realize a kind of binary logic operation. Reference numerals 95 and 96 are operation control signals indicated by the sixth arm that specify the type of operation of a total of 4 bits. Also, Di and Di are shift circuits 6 of FIG. 6, respectively.
Output data C of 3 and its negation, DSi is graphic memory
The data read from 117 (data B in FIG. 6). The selectors 91 and 92 select one of four types of signals, that is, the data Di, Di, the signal 98 which is always high level, and the signal 97 which is just low level. 16 types of outputs Ri and DRi of the selectors 91 and 92 can be combined by the control signals 95 and 96 which are operating bits, and thus 16 types of operations shown in Table 1 can be performed. The data CPi output as the calculation result becomes the input (data D in FIG. 6) of the selection circuit 64.

In normal data transfer, that is, when writing data from the CPU 111 to the graphic memory 117 as it is, DN = 0 and WN is used to specify the bit length of 1 word (or 1 byte), and the operation result OPi becomes Di. You can specify the operation in. The arithmetic circuit 62 can be composed of a normal ALU, but when it is applied to a display circuit of a word processor, it seems that a highly functional name arithmetic circuit is not necessary. CPU111
When reading data from the graphics memory 117,
The data read from the graphics memory 117 without passing through the data BLU124 is the same as the normal read operation.
Directly mounted on the data bus 67 of.

Although one embodiment of the present invention has been described above by taking the CRT display device 254 of the word processor as an example, the present invention is extremely effective not only for the word processor but also for a general data processing device. Particularly in a device supporting multi-window, a high-speed display device is required, so that the present invention can be effectively utilized.

In the present embodiment, the data transfer from the CPU has been described as an example, but when a large amount of data is subjected to the same arithmetic operation for transportation, DMA (Direct Memory Access) is used.
It is obvious that the above method can be applied to the present invention as it is.

As described above, bit processing, that is, shift operation, or bit operation between two data is performed by the CPU 111 and the memory 11.
Since the bit logic circuit 124 provided between 7 performs the data transfer in the middle of the data transportation, the CPU 111 can perform desired bit processing and arithmetic processing only by transferring the data. For example, several bits of data in one area of the memory correspond to data in another recording area. In the case of replacing with a bit and a logical sum, conventionally, the data processing shown in FIG. 11 (a) was required, but according to the present embodiment, only the data processing shown in FIG. 11 (b) is required. Good. Fig. 11 (b)
The above process is a mere data transfer process of the CPU, and for example, a string operation instruction of the microprocessor 8086 of Intel Corp. can be used and can be processed in about 1/3 to 1/5 of the conventional processing time. Furthermore, by performing the conventionally known DMA transfer without the CPU intervening in the data transfer,
This effect becomes more remarkable.

〔The invention's effect〕

As described above, according to the present invention, the read data position is set to the control unit that specifies the bit position of the read data read from the storage device provided in the data transfer path between the processing devices that perform data transfer. , The range of data to be replaced by the control means for generating the mask data that specifies the range of the data to be rewritten of the read data, the write data from the processing device based on the bit position specified by the control signal requires a shift clock Instead, the shift amount of the write data is set in the shift means before the data is transferred, and the data is transferred. Further, for specific data transfer, the storage device is accessed by a read-modify-write operation, and the write data read by the data shift means read in the read cycle is subjected to a predetermined calculation at a high speed by the calculation means to obtain the mask data. Based on the above, a part of the read data is replaced with the operation data, and the data in the storage device can be changed to the desired data only by writing the data in the write cycle storage device and transferring the data.

As a result, data processing can be performed at high speed, and it is possible to provide an information processing apparatus that performs high-speed copying and moving processing.

[Brief description of drawings]

The drawings show an embodiment of the present invention. FIG. 1 is a block diagram of a CRT display device, FIG. 2 is an external view of a word processor, FIG. 3 is a block diagram of a word processor, and FIG. Flowchart, FIG. 5 is an input processing flowchart, FIG. 6 is a block diagram of a bit logic circuit, FIG. 7 is a data conversion processing explanatory diagram, FIG. 8 is a data conversion processing timing chart, FIG. 9 is a latch clock generation circuit, and FIG. Figure 10 is a block diagram of the arithmetic circuit,
FIG. 11 (a) is a salting flow chart of the conventional apparatus, and FIG. 11 (b) is a calculation processing flow chart of the apparatus of this embodiment. 23 ... CRT monitor, 62 ... arithmetic circuit, 63 ... shift circuit, 64 ... selection circuit, 65 ... control signal generation circuit, 111 ...
... CPU, 117 ... graphic memory, 124 ... bit logic circuit, 254 ... CRT display device.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location G09G 5/36 9471-5G (72) Inventor Hiroaki Aozu 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Share Ceremony Company Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Hideki Sekiyama 1-1-1, Higashi Taga-cho, Hitachi City, Ibaraki Prefecture Incorporated Company Hitachi, Ltd. Taga Factory (72) Inventor Yasuo Sakai Higashi City, Ibaraki Prefecture 1-1-1 Tagamachi, Ltd. Hitachi Ltd. Taga factory (56) References JP-A-59-124372 (JP, A)

Claims (2)

[Claims] 1. A first means for transferring data, a second means for storing data, a second means for reading data from a second means in the latter half of a data writing cycle to the second means by the first means, In the latter half of the write cycle, the data from the first means is written bit by bit in the data transfer path of the first means and the second means in the information processing exercise by writing this data to the second means and the read modify write control means. The data selecting type bit shift means for shifting the data by means of the above, the bit converting means for converting only the designated bits of the data read from the second means, and the control signal generating means for controlling these are provided. When writing data to the second means in the read modify write mode, the write data from the first means is written in the data select type in the entire write cycle. Shifting a predetermined amount by the bit shift means, converting only predetermined bits of the data read from the second means based on the shifted write data D, and writing the converted data to the second means in the latter half of the write cycle. An information processing device characterized by: 2. The control signal generating means comprises means for designating a bit position of data read from the second means, means for designating a bit width of the data to be converted, and operation designating means. The shift means shifts the write data from the first means based on the designated bit position, and the bit conversion means starts from the designated bit position.
2. The data read from the second means by the designated bit width is replaced with the operation result designated by the operation designating means of the write data and the shifted write data. Information processing equipment.