JPH0346823B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to an image display device having a memory for storing character patterns such as Chinese characters for a graphic display method using a bitmap memory. [Background of the Invention] The code refresh method has traditionally been widely used in character display devices used in word processors and the like, but the demand for graph and graphic displays has made it necessary to use graphic displays. For graphical display, the bitmap refresh method is used, which is suitable for displaying graphs and figures, but even when displaying kanji, the kanji pattern must be developed on the bitmap memory, so the conventional code refresh method is suitable for displaying graphs and figures. The disadvantage was that the display processing speed was slower than that of conventional display devices. This problem is the same even in personal computers with BITMATSU pre-refresh type display devices, and in order to improve this point, a barrel shifter and a BIT mask controller are installed in the CRT interface section to improve speed. . However, in the conventional device, the pattern data arrangement in the character generator and the memory arrangement in the graphics memory are different, and the processing functions of the CPU cannot be used efficiently. Such a personal computer is disclosed in the "PC-100 Technical Manual" regarding the general-purpose personal computer PC-100 manufactured by NEC Corporation. [Object of the Invention] In view of the above, the present invention provides an image display device that can utilize the high-speed processing function of the CPU with a simple circuit configuration and obtain a high display speed even if the display method is the BITSUTOMATSU pre-refresh method. It is in the realization. [Summary of the Invention] The present invention provides a computer unit that reads dot data of an image pattern from a character generator section and writes the dot data into a bitmap graphics memory, and a computer unit that reads dot data from the graphics memory to generate an image. Make a signal and CRT
In an image display device equipped with a CRT controller for display on a monitor, the character generator unit divides a dot matrix of one character pattern in bytes in the raster direction, and divides the dot matrix into one non-volatile matrix in the raster direction. It is characterized by increasing the display speed by increasing the efficiency of controlling the reading of dot data from the character generator section by the computer unit. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 2, a word processor using an embodiment of the present invention includes a main body 20 equipped with a temporary storage section and a control section, a keyboard 21 as an input section, a printer 22 as a printing section, and a display section.
It consists of a CRT monitor 23, a main body 20, a printer 22, a keyboard 21, and
As shown in FIG. 3, the CRT monitor 23 sends and receives control signals or information signals through cables 201, 202, or 203, respectively. In Fig. 2, 24 is a flexible disk device (hereinafter referred to as FDD), and the main body 2
0 is integrally assembled. Inside the main body 20, there is a control section 2 within the broken line in the control circuit shown in the block diagram of FIG.
5 is installed. In other words, the control unit 25 includes a host CPU 251 consisting of a program storage type computer unit (hereinafter referred to as CPU), a boot board comprising a non-volatile memory (hereinafter referred to as ROM) and having a program executed when the power is turned on.
ROM 252, a memory that can be read and written at any time to store programs and information for executing functions as a word processor (hereinafter referred to as
It's called RAM. ) program memory 25 consisting of
3. A CRT display circuit 254 that generates a screen display pattern according to instructions from the host CPU 251 and sends a video signal to the CRT monitor 23, and a host CPU.
A flexible disk control circuit (FDC) 255 controls the FDD 24 according to instructions from the host CPU 251, and sends signals to control the printer 22 and print signals to the printer 22 according to instructions from the host CPU 251, and sends status signals of the printer 22 to the printer. The printer controller 256 receives from the printer controller 22 and sends it to the host CPU 251, controls the keyboard 21 according to the instructions from the host CPU 251, and
a key input controller 257 that sends input signals from the host CPU 251 to the host CPU 251;
CPU251, boot ROM252, program memory 253, CRT display circuit 254, FDC255,
It is composed of an internal wiring path d that connects the printer controller 256 and the key input controller 257. Here, the FDD 24 drives a flexible disk, which is a magnetic storage medium, and records information on the flexible disk and reads information from the flexible disk. An opening for the FDD 24 related to the storage section is provided substantially on the front surface of the main body 20. Next, the overall operation of this word processor will be explained. When the power is turned on in the above configuration, the host CPU 251 loads the boot ROM 2.
52 program, a program for operating this device as a word processor with the data processing flow shown in Fig. 4 is installed on the FDD 24.
The word processor is transferred from the flexible disk stored in the program memory 253 to the program memory 253, and then starts operating as a word processor in accordance with the program transferred to the program memory 253. Furthermore, at the same time, a program for the CPU 111, which controls a CRT display circuit 254, which will be described later, to perform a CRT display operation is also transferred from the flexible disk stored in the FDD 24 to the memory 122, which will be described later. In the data processing flow shown in FIG. 4, in processing step 401, a message to start processing as a word processor and a menu of executable processing tasks are displayed on the CRT monitor 23, and in processing step 402, the operator specifies the word processor by operating the keyboard. Reads the work menu selection input to be performed. In processing step 403, it is determined whether the specified operation is an input processing operation, in processing step 404, it is determined whether the specified operation is an editing processing operation, and in processing step 405, it is determined whether or not the specified operation is a printing processing operation.
In processing step 406, it is determined whether the task is an auxiliary function processing task or not, and each processing step branches to the corresponding processing task 407 to 410, and if it is neither, the process returns to processing step 401. The auxiliary function is a general term for a function that aggregates functions such as copying document data on a flexible disk to another flexible disk. When the input processing 407 is selected by the work menu selection input, the host CPU 251 starts executing an input processing program having a data processing flow as shown in FIG. The document data being inputted is sent as commands and data to the CRT display circuit 254 via the signal line a according to the program for executing the input data processing as shown in FIG. The display circuit 254 creates an image pattern, converts it into a video signal, and supplies it to the CRT monitor 23 to display the image on the surface of the CRT monitor 23. Processing instructions associated with data input to the document data are performed according to data and function instructions input from the keyboard 21. In the data processing flow shown in FIG.
The settings are displayed on the monitor 23, and in processing step 502, the setting input input by the operator from the keyboard is read. In processing step 503, an input screen according to the above settings is displayed. Processing step 504 reads data input from keyboard 21, and processing step 505 displays it. At processing step 506, it is determined whether an input indicating the end of the data input work has been received, and if the data entry work has not been completed, the process returns to processing step 504.
If the process is finished, the process advances to processing step 507 to execute the completion process and return to the data processing flow shown in FIG. 4. The termination process 507 is a process in which input data is written and stored on a flexible disk. If the CRT display circuit 254 is to display only characters, the program memory 2
According to instructions from the program stored in the CRT display circuit 53, the unit of data that the host CPU 251 provides to the CRT display circuit 254 is data corresponding to one line of display characters on the screen. i.e. host
In response to each character input from the keyboard 21, the CPU 251 outputs one line of data with a new display character added to the end of the line through the signal line a.
It is sent to the CRT display circuit 254. The operator inputs characters one by one, but the host CPU 251 and CRT display circuit 25
4 must display data for one line, so input processing within the host CPU 251 and further processing of drawing on the screen within the CRT display circuit 254 should be done so that the operator does not have to wait. High speed data processing is required. In the editing process 408 in FIG. 4, the screen is rewritten in accordance with function key inputs from the keyboard 21. Even during other processing, work instructions, progress, etc. are displayed on the CRT monitor 23. Next, the CRT display circuit 254 will be explained. FIG. 1 shows a block diagram of one embodiment of CRT display circuit 254. Shown in Figure 1
The CRT display circuit 254 is connected to the CPU 111 (for example, Intel's 8086 or
8088 etc. are suitable. ), a clock generator 112 that supplies clocks and other signals necessary for the CPU 111, and a CRT that generates address signals for sequentially reading out the contents of the graphics memory 117 and a synchronization signal that controls the CRT monitor 23.
Controller 113, graphics memory 117
Shift register or CRT controller 1 that converts parallel data from
a peripheral control circuit 114 consisting of a driver etc. that supplies the synchronization signal from 13 to the CRT monitor 23;
Displays images by receiving video signals and synchronization signals
The CRT monitor 23 controls the access signal from the CPU 111 and the access signal from the CRT controller 113 in a time-sharing manner to
A time-division control circuit 116 sends out data from the memory by inputting data to each bit of the image on the screen, and a 128 kilobyte dynamic RAM (64 kilobits x 16 bit words,
However, it is accessed by the CPU in 8-bit byte units. ), a host CPU 251 shown in FIG. 2 which is located above the CRT display circuit 254, and an interrupt controller 11 which gives an interrupt signal to the CPU 111 and branches the program in response to an external event.
8. Control register 119 that holds control information such as shift read and write control bits, memory 122
a collision prevention control circuit 120 configured to multiplex control accesses from the CPU 111 to the CG 123 and access signals from the host CPU 251 shown in FIG. 3, and a DRAM controller that controls generation of multiplexed address signals to the memory 122 and refresh operation 121, a character generator section (hereinafter referred to as CG) 123 consisting of a dynamic RAM 122 (hereinafter referred to as DRAM) that dynamically stores memory, and a ROM that stores kanji, kana, alphanumeric characters, etc. in a dot matrix pattern;
It consists of Host CPU 251 and CRT display circuit 2 in Figure 3
54 is connected by a control signal and data signal line a, which interconnects the CPU 111 of the CRT display circuit 254, the CRT controller 113, the time division control circuit 116, the interrupt controller 118, the control register 119, and the collision prevention control circuit 120. The one who is there is
CPU bus b, which multiplexes access signals from signal lines a and b to connect DRAM controller 121 and CG.
There is a memory bus c that feeds 123. Next, details of the CG 123 are shown in FIG. CG123 is CGROM23 consisting of multiple ROMs.
1. A bus driver that supplies the contents of the CGROM 231 as is to the data line of the memory bus c, as a bus driver for supplying 1-byte data of the CGROM 231 specified by the address signal from the memory internal bus to the data line of the memory bus c. 23
2. A bus driver 23 that replaces the data in the CGROM 231 in units of 4 bits and supplies it to the bus c.
It is composed of 3 etc. Here, signal line e
is set in the control register 119 by the CPU 111 and transmits a signal given from the control register 119. Further, of the time division control circuit 116 and the graphic memory 117, circuit portions related to write control are shown in FIG. A control signal to the graphics memory 117 is given from a time division control signal generation circuit 161.
Address and CPU when reading from CRTC113
an address selector 163 for switching the address when accessed from CRTC 111; and a shift register 14 for converting parallel data read out when accessed from CRTC 113 into a serial video signal.
1.CPU bus b when accessing from CPU111
A bus driver 16 that exchanges data with
2. A data latch 191 that is part of the control register 119 that controls the masking of the signal WE that controls bit-by-bit writing of the graphics memory 117.
and data latch 1 when writing from CPU111.
A WE driver 164 for supplying a WE signal to the graphic memory 117 according to the contents of the graphic memory 117 is connected to the periphery of the graphic memory 117. Next, the configuration of the CGROM 231 will be explained in detail using figures. Figure 8 shows a character generator with a 24 x 24 bit configuration that has been commercially available.
ROM (for example, sold by Hitachi)
This includes HN613256PA10~PA18. ) is shown in the ROM using the kanji character ``Dou'' as an example. In this ROM, one character is divided into 8x to match the code refresh display circuit system.
Divided into 8 bit patterns for a total of 9 bits.
The ROM stores the dot pattern of one character. This has the advantage of requiring a minimum hardware configuration in order to obtain CG raster data from character numbers and raster addresses in the code refresh method.
In the bitmap display method in which the CPU 111 reads out the CG 123 and writes the display pattern to the graphics memory 117, when the CPU 111 reads out adjacent 8x8 bit patterns, the following steps are taken.
The address of the pattern stored in ROM is 32
Since they are spaced apart by kilobytes, the addressing register must be operated each time, which is not suitable for CG read processing. Therefore, in this example,
As shown in Figure 9, a CGROM structure suitable for CPU control is an aligned type CG in which a 24 x 24 bit pattern is divided into 8 x 24 bits in bytes and stored consecutively in one ROM. There is. The addresses are shown in hexadecimal when all ROMs are arranged in order. Next, the address structure of the graphics memory 117 will be explained using a diagram. A video signal is composed of a series of image bits in raster units. That is, it is performed in units of 16 bits from the beginning of the screen read from the CRTC 113 for refreshing the screen.
It is serially converted starting from the MSB, and after the LSB, the following
A series of 16-bit MSBs. FIG. 10 shows the address structure of a conventional graphic memory. Area 117a corresponds to the CRT screen display area. On the other hand, for the CPU, when handling a 24 x 24 bit character pattern, the depth is 3 bytes in the raster scan direction and 24 bytes in the raster order direction. For the Intel 8086 and 8088 used as the CPU 111, string instructions are provided for repeated processing of consecutive addresses. That is, data transfer of a specified number of bytes from a source address specified in a predetermined register to a destination address specified in a predetermined register is performed with the minimum number of instruction steps and the shortest processing time. In order to obtain the maximum effect in this processing method, it is effective to increase the number of bytes transferred at one time. Considering this point, the addresses of the graphics memory 117 viewed from the CPU 111 should be arranged in the forward raster direction. FIG. 11 shows the address structure of the graphics memory 117 in this embodiment. In order to realize this address configuration, the correspondence between the two groups of CRT addresses and CPU addresses input to the address selector 163 shown in FIG. 7 and the address output to the graphics memory 117 is as shown in Table 1.

【table】

〔Effect of the invention〕

As described above, according to the present invention, the CPU
It is possible to provide a character generator that is optimal for a kanji display circuit that can write character patterns such as kanji characters into a graphic memory at high speed by making full use of the characteristics of kanji characters, and can also display graphics. In particular, high-speed processing using string instructions is possible in single-character drawing processing, and it can be exemplified that by utilizing these string instructions, the speed can be increased by about three times compared to conventional devices. In this way, by speeding up memory rewriting, it becomes possible to shorten the response time in word processing processing performed interactively by the operator, and it becomes possible to shorten the response time in word processing processing performed interactively by the operator. Improves operability in editing processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display device according to the present invention, FIG. 2 is an external view of a word processor employing the image display device according to the present invention, and FIG. 3 is a block diagram of a circuit section of the word processor. Fig. 4 is a flowchart of the word processor operating program, Fig. 5 is a flowchart related to input processing in the word processor operating program, Fig. 6 is a detailed block diagram of CG, and Fig. 7 is a circuit section related to WE control. 8 is a diagram showing the pattern configuration and addresses of a conventional CGROM, FIG. 9 is a diagram showing the CG configuration of the present invention, and FIG. 10 is a diagram showing the address configuration of a conventional graphics memory. 11 is a diagram showing the address structure of the graphic memory according to the present invention, FIG. 12 is a flowchart of a one-line display program executed by the CPU for operating as an image display device according to the present invention, and FIG.
The figure is a timing chart showing time-sharing control between reading from the CRTC and access from the CPU.
Figure 4 is a diagram showing a graphic memory displaying the half-width character A, Figure 15 is a flowchart of writing processing to the graphic memory in a known example circuit, and Figure 1
FIG. 6 is a flowchart of the write process according to the present invention. 23...CRT monitor, 111...Program storage type computer unit, 113...CRT controller, 117...Graphic memory, 12
3...Character generator section, 231...
CGROM.

Claims (1)

[Claims] 1 A computer unit that reads dot data of an image pattern from a character generator section and writes this dot data to a bit map graphic memory, and a computer unit that reads dot data from the graphic memory to create a video signal and display it on a CRT monitor. In an image display device equipped with a CRT controller, the character generator section partitions a dot matrix of one character pattern in bytes in the raster direction and stores them in one nonvolatile memory in the raster direction. An image display device characterized in that it is provided with a storage means that continuously accommodates the information.