JPH02280316A - Pattern formation of integrated circuit - Google Patents

Abstract

PURPOSE:To omit a patterning process by depositing an intermediate layer consisting of the same material as a semiconductor substrate or a processing film and by carrying out patterning of the semiconductor substrate or the processing film and removal of a remaining part of the intermediate layer simultaneously. CONSTITUTION:A lower layer resist layer 3 is applied and formed on a processing film 2 which covers a semiconductor substrate 1, and an intermediate film 4 which consists of the same material as the processing film 2 is deposited on the lower layer resist layer 3. Thereafter, an upper side resist layer 5 is applied and formed on the intermediate layer 4. After the upper side resist layer 5 is patterned, the intermediate layer 4 is patterned using a remaining part 5a of the upper side resist layer 5 as a mask. Then, the lower side resist layer 3 is patterned using a remaining part 4a of the intermediate layer 4 as a mask and the remaining part 5a of the upper side resist layer 5 is removed at the same time. The processing film 2 is patterned using a remaining part 3a of the lower layer resist layer 3 as a mask and the remaining part 4a of the intermediate layer 4 is removed at the same time. A patterning process can be omitted in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. INDUSTRIAL APPLICATION FIELD This invention relates to a method for patterning integrated circuits such as VLSI.

[Conventional technology]

In recent years, as the miniaturization of integrated circuits has progressed, there has been a demand for forming narrower wiring patterns, and three-layer resist is one of the pattern forming methods that can meet these demands. A method called process is known.

In this three-layer resist process, first, as shown in FIG. 2(a), a lower resist layer 3 is applied and formed on a processed film 2 made of aluminum (A1) or the like that covers the semiconductor substrate 1). Then, after forming an intermediate layer 4 made of spin-on glass (SOG) or the like on this lower resist layer 3, an upper resist layer 5 is formed by coating on this intermediate layer 4. Then, as shown in FIG. 2(b), the upper resist layer 5 is patterned using an electron beam, light, X-rays, etc. or by lithography, and as shown in FIG. 2(c), the upper resist layer 5 is patterned. The intermediate layer 4 is patterned by reactive ion etching (hereinafter referred to as RYE) using the remaining portion 5a as a mask.

Next, as shown in FIG. 2(d), using the remaining portion 4a of the intermediate layer 4 as a mask, an R
At the same time as patterning the lower resist N3 by IF or the like, the remaining portion 5a of the upper resist layer 5 is removed. Furthermore, as shown in FIG. 2(e), the remaining portion 4a of the intermediate layer 4 deposited on the remaining portion 3a of the lower resist layer 3 is
After removing by TE etc., as shown in FIG. 2(f), R is applied using the remaining portion 3a of the lower resist layer 3 as a mask.
The film to be processed 2 is patterned by JE.

[Problem to be solved by the invention]

However, in the conventional pattern forming method, since there are many patterning steps, there are disadvantages in that it is time-consuming and increases costs.

The present invention was devised in view of the above-mentioned disadvantages, and an object of the present invention is to provide a method for forming a pattern for an integrated circuit, which allows the patterning process to be omitted.

[Means to solve the problem]

The method of the present invention is a method for patterning an integrated circuit using a 3N resist process, in which a lower resist layer is coated on a semiconductor substrate or a film to be processed covering the semiconductor substrate, and
Further, after depositing an intermediate layer made of the same material as the semiconductor substrate or the film to be processed on the lower resist layer, coating and forming an upper resist layer on the intermediate layer, and patterning the upper resist layer. , patterning the intermediate layer using the remaining portion as a mask, patterning the lower resist layer using the remaining portion as a mask, and simultaneously removing the remaining portion of the upper resist layer; At the same time, patterning the semiconductor substrate or the film to be processed using the mask as a mask,
The method is characterized in that it includes a step of removing a remaining portion of the intermediate layer.

[Effect]

According to the above method, since the intermediate layer made of the same material as the semiconductor substrate or the film to be processed is deposited in advance, the half-quad substrate or the film to be processed is patterned and the remaining portion of the previously patterned intermediate layer is removed. will be done at the same time.

〔Example〕

An embodiment of the method of this invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(e) are process cross-sectional views showing the pattern forming procedure of the 4J#1 circuit according to the method of the present invention.

The procedure in this example is the same as the conventional example described above, except that the film to be processed and the intermediate layer are made of the same material. 2 [The same or corresponding parts as in (a) to (f) are given the same reference numerals.

In the 3N resist process according to this example,
First, as shown in FIG. 1(a), a lower resist layer 3 is coated and formed on a film to be processed 2 made of aluminum (A1) or the like that covers a semiconductor substrate 1, and a lower resist layer 3 is formed on the lower resist layer 3. After depositing an intermediate N4 made of the same material as the film to be processed, ie, aluminum (Afi) or the like by sputtering or leather coating, an upper resist layer 5 is formed on the intermediate layer 4 by coating.

Then, as shown in FIG. 1(b), after patterning the upper resist layer 5 using an electron beam, light, etc. or by lithography, the first resist layer 5 is patterned as shown in FIG. 1(c).
RIE using the remaining portion 5a of the upper resist WI5 as a mask
The intermediate layer 4 is patterned by et al. Next, as shown in FIG. 1(d), the lower resist layer 3 is patterned by RTE using oxygen (02) plasma using the remaining portion 4a of the intermediate layer 4 as a mask, and at the same time, the remaining portion 4a of the upper resist layer 5 is patterned. Remove portion 5a. Note that the steps up to this point are similar to those of the conventional example described above.

Furthermore, as shown in FIG. 1(c), the film to be processed 2 is patterned by RIE using the remaining portion 3a of the lower resist layer 3 as a mask. However, at this time, since the intermediate layer 4 is made of the same material as the film to be processed 2, that is, aluminum (AN), the remaining portion 4a of the intermediate layer 4 that has been patterned earlier is not included in the patterning of the film to be processed 2. It will be removed at the same time. Therefore, as shown in FIG. 2(e) in the conventional example, there is no need to remove the remaining portion 4a of the intermediate N4 deposited on the remaining portion 3a of the lower resist layer 3 by RIE or the like.

In addition, in the above explanation, the processed film 2 and the intermediate layer 4
is assumed to be aluminum (Aj), but the material for forming these is not limited to 1M, for example, the material to be processed 11
When 92 is an oxide film or the like, the intermediate layer 4 is also formed of an oxide film or the like. Further, although this embodiment has been described as patterning the film to be processed 2 of the semiconductor substrate l, the invention is not limited to this, and for example,
It goes without saying that the method of the present invention can also be applied to cases where grooves for element isolation, so-called trenches, are formed in the semiconductor substrate l.

〔Effect of the invention〕

As explained above, according to the method of the present invention, an intermediate layer made of the same material as the semiconductor substrate or the film to be processed covering it is deposited in advance, and then the semiconductor substrate or the film to be processed is patterned. Since the remaining portion of the layer is removed at the same time, there is no need to remove only the remaining portion of the intermediate layer as in the conventional example, and as a result, the patterning step can be omitted. Therefore, it is possible to reduce the time and effort required for this and also to reduce costs.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are process cross-sectional views showing the steps of patterning an integrated circuit according to the method of the present invention, and FIG. 2(a)
-(f) are process cross-sectional views showing the steps for forming a pattern of an integrated circuit according to a conventional method. In the figure, 1 is a semiconductor substrate, 2 is a film to be processed, 3 is a lower resist layer, 3a is its remaining part, 4 is an intermediate layer, 4a is its remaining part, 5 is an upper resist 1-Fl, 5a is its remaining part Department. Note that the same reference numerals in the drawings indicate parts and portions that are the same or correspond to each other. Figure 2 (a) (b)

Claims (1)

[Claims] (1) A method for forming an integrated circuit pattern using a three-layer resist process, in which a lower resist layer is coated on a semiconductor substrate or a processed film covering the semiconductor substrate, and the above-mentioned After depositing an intermediate layer made of the same material as the semiconductor substrate or the film to be processed, a step of coating and forming an upper resist layer on the intermediate layer, and patterning the upper resist layer and using the remaining portion as a mask to form the intermediate layer. patterning, and then patterning the lower resist layer using the remaining portion as a mask, and simultaneously removing the remaining portion of the upper resist layer; and using the remaining portion of the lower resist layer as a mask, patterning the semiconductor substrate or the workpiece. A method for patterning an integrated circuit, comprising the step of patterning a film and simultaneously removing a remaining portion of the intermediate layer.