JPH02277336A - Faulty processor detection system - Google Patents

Abstract

PURPOSE:To avoid a transmission destination processor from being regarded as a fault when the processor is in a single congestion state by providing a 2nd count means counting the pause state to each processor being the transmission destination to a sender processor, monitoring the pause state for a prescribed period and regarding it as a fault when the level is larger than a prescribed 2nd threshold level. CONSTITUTION:When a processor 22 cannot receive a transmission data due to any cause although a processor 1 sends a data to the processor 22, a transmission control processing section 53 of the processor 21 registers a transmission data to a transmission queue 72 corresponding to the processor 22, regards the processor 22 to be in the pause state to stop the transmission of a data for a prescribed time and restarts the transmission processing after a prescribed time. A pause state check processing regarding it to be a fault when number of times of the pause state exceeds a prescribed number of times within a prescribed time, and a processing regarding it to be a fault when a transmission queue length counter exceeds a prescribed value in a conventional system are used in common to reduce the possibility of misjudging the transmission destination processor congestion state is precluded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a faulty processor detection method used between processors in a multiprocessor system configured by connecting a plurality of processors via a bus.

[Conventional technology]

Conventionally, in a faulty processor detection method in communication between multiple processors, there is a transmission waiting queue in which the sending processor that sends data registers the waiting data for each destination processor, and a sending waiting queue in which the length of the waiting data is counted. A queue length counter is provided, and when the destination processor that should receive the transmitted data does not receive the transmitted data, the transmitted data is registered in the transmission waiting queue, the transmission waiting queue length counter is incremented one step, and the processing is performed periodically. Monitor the send queue length and set a predetermined threshold, e.g.
If the value is set to 20, a processor failure is detected through queue length check processing that treats a destination processor exceeding this value as a failure.

[Problem to be solved by the invention]

As mentioned above, conventional faulty processor detection methods
A destination processor whose transmission queue length exceeds a predetermined threshold is immediately regarded as a failure. Therefore,
Even when the destination processor is simply in a congestion state, such as receiving data from another processor, and is unable to receive the transmitted data and is stuck in the transmission queue of the source processor. , such a destination processor is considered to be a failure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a faulty processor detection method that prevents a destination processor from being considered faulty when it is simply in a congested state.

[Means to solve the problem]

The faulty processor detection method of the present invention is a storage system in which a sending processor that sends data in a multiprocessor system configured by connecting a plurality of processors via a bus registers data waiting to be sent for each destination processor. The first step is to count the length of the data waiting to be sent.
counting means is provided, and when the destination processor that should receive the transmitted data does not receive the transmitted data, the transmitted data is registered in the storage means, the first counting means is incremented, and the first counting means is periodically counted. monitor the length of data waiting to be sent,
In a faulty processor detection method in which a faulty processor is detected by a queue length check process in which a processor that exceeds a predetermined first threshold is considered to be faulty, the number of idle states of the transmission destination processor is counted for each destination processor. and when the destination processor does not receive the transmitted data, the destination processor is deemed to be in a dormant state, and the data transmission is suspended and the second counting means is incremented. the inactive state is monitored at regular intervals, and if the value is smaller than a predetermined second threshold value, the value of the second counting means is returned to 0; if the value is larger than the inactive state, the inactive state is regarded as a failure; The system is configured to detect a faulty processor using long check processing in combination.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 1 shows a multiprocessor system in which n processors 21 to 2n are connected via a bus 10 and processing is performed while communicating among the processors 21 to 2n. The processor 21 has a central processing unit 50 and a bus 1.
a receiving section 30 that takes in data on 0 and transmits it to the central processing unit 50, a transmitting section 40 that sends data from the central processing unit 50 onto the bus 10, and a storage device 60 connected to the central processing unit 50. The other processors 22 to 2n are similarly configured. Central processing bag N
50 includes a queue length check processing section 51, an inactive check processing section 52, and a transmission control processing section 53, and a storage device 6.
0 has transmission waiting queues 72 to 7n, transmission waiting queue length counters 82 to 8n, and idle counters 92 to 9n, which correspond to transmission destination processors other than the own processor.

The operation of this embodiment will be described below assuming that the processor 21 is a source processor that transmits data, and the processor 22 is a destination processor that receives data.

If the processor 21 transmits data to the processor 22 but the processor 22 is unable to receive the transmitted data for some reason, the transmission control processing unit 53 of the processor 21 transmits the data to the transmission waiting queue 72 corresponding to the processor 22. The data is registered, the transmission waiting queue length counter 82 and the inactive counter 92 are each incremented by one step, the processor 22 is considered to be in an inactive state, data transmission is stopped for a certain period of time, and the transmission process is resumed after a predetermined period of time.

On the other hand, the queue length check processing unit 51 checks the transmission waiting queue length counter 82 corresponding to each processor at regular intervals.
The value of ~8n is compared with a predetermined threshold value to search for any value exceeding the threshold value. This threshold is
Since the congestion state of the destination processor is taken into consideration, for example, the conventional value of 2 degrees is now set to 200, which is larger than the conventional value. If processor 2
If the transmission queue length counter 72 corresponding to 2 exceeds its threshold value, it is determined that a failure has occurred in the processor 22.

The inactivity check processing unit 52 compares the values of the inactivity counters 92 to 9n corresponding to each processor with a predetermined threshold value at regular intervals, and searches for any that exceeds the threshold value. For example, if it is within 2 within 50m5, it is considered to be within the range of normal congestion and is considered to be operating normally, and the value of the corresponding idle counter is reset to 0.
The value of the inactive counter 92 corresponding to the processor 22 is 3.
If so, it is determined that a failure has occurred in the processor 22.

〔Effect of the invention〕

As explained above, the present invention provides a new idle counter in addition to the transmission waiting queue length counter corresponding to the destination processor, which is conventionally provided in the source processor, so that the destination processor receives data. If the destination processor is not in the dormant state, it is counted as a dormant state and data transmission is stopped, and if the number of times the destination processor is in the dormant state exceeds a predetermined number within a fixed period of time, the destination processor is considered to be at fault. By using a queue length check process that treats the destination processor as a failure when the waiting queue length counter exceeds a predetermined threshold, it is possible to prevent the destination processor from erroneously failing when the destination processor is simply congested and unable to perform reception processing. This has the effect of reducing the possibility of being judged as a disability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10... bus, 21-2n... processor, 30... receiving section, 40... transmitting section, 50... central processing unit , 51...
Queue length check processing unit, 52...Suspension check processing unit, 53...Transmission control processing unit, 60.
...Storage device, 72-7n...Transmission waiting queue, 82-8n...Sending waiting queue length counter, 92-9n...Sleeping counter.

Claims (1)

[Claims] In a multiprocessor system configured by connecting multiple processors via a bus, a storage means for registering data waiting to be sent for each destination processor in a sending processor that sends data, and counting the length of the data waiting to be sent. and registering the transmitted data in the storage means and incrementing the first counting means when the destination processor that should receive the transmitted data does not receive the transmitted data. , a faulty processor detection method detects a faulty processor through a queue length check process that periodically monitors the length of data waiting to be sent and considers a processor exceeding a predetermined first threshold as a fault; The processor is provided with a second counting means for counting the inactive state for each destination processor, and when the destination processor does not receive the transmitted data, the destination processor is deemed to be in the inactive state and the data is counted. suspending transmission and incrementing the second counting means, monitoring the inactive state at regular intervals, and returning the value of the second counting means to 0 if it is smaller than a predetermined second threshold; A method for detecting a faulty processor, characterized in that a faulty processor is detected by using a combination of the queue length check processing and an inactive check processing in which the queue length is considered to be faulty if the size is large.