JPH04367061A - Faulty processor detection system - Google Patents

Abstract

PURPOSE:To accurately detect the fault of a processor by setting the receiving operation of a transmission destination processor at a transmittable flag and utilizing the state of this flag in a queue length check processing state. CONSTITUTION:A processor 21 connected via a bus 10 is used as the transmission destination processor, and the processors 22-2n are used as the transmission destination processors respectively. Then the processor 21 is provided with the transmission queues 72-7n corresponding to other processors, the transmission queue length counters 82-8n, and the transmittable flags 92-9n. A communication control processing part 51 of a CPU 50 registers the transmission data to the queues 72-7n and counts down the counters 82-8n. When the data sent from a transmission part 40 are received by the processors 22-2n, the corresponding flags 92-9n are set and those data are not registered into the queues 72-7n. Then the fault of a processor is decided only when the count values of the counters 82-8n exceed the threshold value and at the same time the flags 92-9n are cleared.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a faulty processor, and more particularly to a method for detecting a faulty processor for detecting a fault in a destination processor in communication between processors in a multiprocessor system configured by connecting a plurality of processors via a bus. .

0002

2. Description of the Related Art Conventionally, in a multiprocessor system including a plurality of processors, there is a transmission waiting queue corresponding to a destination processor, and there is a system in which the number of transmission waiting queues exceeds a predetermined threshold. In other cases, the destination processor was considered to be a failure.

0003

[Problems to be Solved by the Invention] The conventional faulty processor detection method described above takes into account only the number of queues waiting for transmission, so the destination processor is simply congested and reception processing cannot catch up, and transmission is not performed normally. However, even if the destination processor ends up being accumulated in the transmission waiting queue, the destination processor becomes a failure, and a normally operating processor is disconnected from the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a faulty processor detection method that eliminates the above-mentioned drawbacks and greatly suppresses the possibility of a destination processor being mistakenly recognized as faulty when it is simply in a state of congestion.

[0005]

[Means for Solving the Problems] The method of the present invention is a faulty processor detection method for detecting a faulty processor in a multiprocessor system in which a plurality of processors are connected to a bus. a transmission waiting queue set for each transmission destination processor and a transmission enable flag indicating that the transmission operation is possible, and registering the transmission data in the transmission waiting queue when the transmission destination processor does not receive the transmission data; When the transmission destination processor receives the transmission data, it sets the transmission ready flag, transmits and purges the transmission data accumulated in the transmission waiting queue in the first cycle, and also flushes the transmission data accumulated in the transmission waiting queue in the first cycle. The number of the queues waiting for transmission is checked at intervals of , and only when the check value exceeds a predetermined threshold and the transmittable flag is cleared, the destination processor is considered to be faulty; otherwise, the destination processor is faulty. The apparatus further comprises a failure determining means for determining that there is no such thing and clearing the transmittable flag.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the embodiment shown in FIG. 1, n processors 21 to 2n are connected via a bus 10.
A multiprocessor system is shown in which processing is performed while communicating between ~2n.

[0008] The processor 21 includes a central processing unit 50;
A receiving unit 30 that takes in data on the bus 10 and transmits it to the central processing unit 50, a transmitting unit 40 that sends data from the central processing unit 50 onto the bus 10, and a storage device 60 connected to the central processing unit 50. The other processors 22 to 2n also have similar configurations.

The central processing unit 50 includes a transmission control processing section 51
, a waiting queue purging processing section 52 , and a queue length checking processing section 53 , and the storage device 60 stores the transmission waiting queue 7 corresponding to the transmission destination processor other than the own processor.
2 to 7n, and a transmission waiting queue length counter 8 that counts the number of data accumulated in the transmission waiting queues 72 to 7n.
2 to 8n, and transmittable flags 92 to 9n.

[0010] In the following, processor 21 transmits data to a source processor, processor 22, and processor 2.
The operation of this embodiment will be explained assuming that 3 is a destination processor that receives data.

[0011] If the transmission control processing section 51 of the central processing unit 50 transmits data to, for example, the processors 22 and 23, but for some reason neither the processors 22 nor the processors 23 are able to receive the transmitted data, The transmission control processing unit 51 sends transmission data to the processor 22 to a transmission waiting queue 7 corresponding to the processor 22.
2 and causes the transmission waiting queue length counter 82 to count down. Similarly, it is registered in the transmission waiting queue 73 corresponding to the processor 23, and the transmission waiting queue length counter 83 is also counted down.

Conversely, when the processor 23 receives the transmission data, the processor 2 of the processor 21
The transmittable flag 93 for No. 3 is set, and it is not registered in the transmission waiting queue 83.

The waiting queue purging unit 52 of the central processing unit 50 checks the count values of the transmission waiting queue length counters 82 to 8n for each processor in the first cycle, and removes any data accumulated in the transmission waiting queues 72 to 7n. If so, a request is issued to the transmission control unit 51 to transmit it to the corresponding processor. The transmission queue for one processor is flushed out until the transmission queue length counter becomes 0 or transmission fails, and then the process moves to flushing the transmission queue for the next processor.

The queue length check processing section 53 of the central processing unit 50 checks the transmission waiting queue length counters 82 to 8n corresponding to each processor every second period which is longer than the first period.
is compared with a predetermined threshold, and the transmittable flags 92 to 9n corresponding to each processor are cleared. in this case,
A processor that exceeds the threshold indicates that the destination processor is congested or failing. Therefore, in order to determine which state it is in, the transmittable flag for the processor in question is checked. If the transmittable flag of the relevant processor is cleared, it is determined that a failure has occurred since no transmission data has been received since the previous queue length check process.

For example, processor 22 and processor 2
Transmission queue length counters 82 and 83 for both
Suppose that both exceed a predetermined threshold. At this time, if the transmittable flag 92 for the processor 22 is cleared and the transmittable flag 93 for the processor 23 is set, it is determined that the processor 23 is in a congested state that is making it difficult to receive the transmitted data for some reason. The processor 22 is determined to be at fault.

[0016]

As described above, the present invention provides a new transmission enable flag for a transmission source processor in a multiprocessor system in addition to the conventional transmission waiting queue length counter corresponding to a destination processor.
By setting the transmission ready flag to indicate whether the destination processor is performing reception operations, and using the status of the transmission availability flag in conjunction with the queue length check process, you can use This has the effect of significantly suppressing the possibility of erroneously determining the destination processor as faulty.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

10 Buses 21 to 2n Processor 30 Receiving unit 40 Transmitting unit 50 Central processing unit 51 Transmission control processing unit 52 Waiting queue purging processing unit 53 Queue length check processing unit 60 Storage devices 71 to 7n Waiting for transmission queue 82 to 8n Waiting for transmission queue length counter 92-9
n Sendable flag

Claims (1)

[Claims] Claim 1: In a faulty processor detection method for detecting a faulty processor in a multiprocessor system in which a plurality of processors are connected to a bus, a faulty processor is set for each destination processor in a source processor that sends data. It is equipped with a transmission waiting queue and a transmission enable flag indicating that transmission operation is possible, and when the transmission destination processor does not receive the transmission data, the transmission data is registered in the transmission waiting queue, and when the transmission destination processor receives the transmission data, the transmission data is registered in the transmission waiting queue. sets the transmit ready flag, transmits and flushes out the transmission data accumulated in the transmission queue in a first cycle, and increases the number of transmission data in the transmission queue in a second cycle, which is longer than the first cycle. Only when the check value exceeds a predetermined threshold and the transmittable flag is cleared, the destination processor is considered to be faulty; otherwise, it is determined that there is no failure and the transmittable flag is cleared. A failure processor detection method characterized by having a failure determination means for clearing the failure.