JPH0227467A - Synchronizing method between arithmetic units - Google Patents

Abstract

PURPOSE:To obtain synchronization between two arithmetic units without providing a special synchronizing device by falling the logical level of each synchronous signal line when a wait condition has passed and an operation starts. CONSTITUTION:When the operation preparation of a first arithmetic unit 10 is completed, the first arithmetic unit 10 raises the logical level of a first synchronous signal line 21 to enter the wait condition, it starts to supervise a second signal line 22, and when the operation preparation of a second arithmetic unit 11 is completed, it raises the logical level of a second synchronous signal line 22. The first arithmetic unit 10 detects it, it passes through the wait condition to start the operation, the second arithmetic unit 11 passes through the wait condition from the rise point of the first synchronous signal line 21, and it starts the operation. At such a time point, by dropping the logical level of the respective synchronous signal line, the synchronization is obtained at the section of the second arithmetic unit 11. Thus, the synchronization can be obtained between the two arithmetic units without the special synchronizing device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a method for controlling calculation timing and input between first and second arithmetic units each consisting of a one-chip microcomputer equipped with a digital input/output port. This invention relates to a synchronization method for synchronizing output timing and the like.

[Conventional technology]

FIG. 4 is a block diagram for explaining a conventional method for synchronizing two arithmetic units. In the same figure, 1.2
are arithmetic units, 3 is a synchronization device from a flip-flop, and 4 is a sensor.

It is assumed that arithmetic device t sends a command to sensor 4, and a response is returned from sensor 4 to both arithmetic devices 1 and 2.

The arithmetic device 1 can take in the answer because it knows the timing when the answer will come back because it is a command output by itself, but the arithmetic device 2 cannot take in the answer because it does not know the timing. Therefore, it is necessary to let the arithmetic unit 2 know the timing and synchronize it.

Therefore, the arithmetic device 1 sets the flip-flops constituting the synchronizer 3 at the start of its operation to take the lead control. As a result, a signal for synchronization can be sent from the arithmetic device to the arithmetic device 2 via the synchronizer 3, but it cannot be sent from the arithmetic device 2 to the arithmetic device 1. Therefore, the arithmetic device 1 sends a command to the sensor 4, and notifies the arithmetic device 2 of the timing at which the response is returned from the sensor 4 via the synchronizer 3, so that the arithmetic devices 1 and 2 can be synchronized. .

[Problems to be Solved by the Invention] As mentioned above, in order to synchronize between two arithmetic units, it has conventionally been necessary to provide a special synchronizing device externally (or it is necessary to provide a synchronizing device separately for each arithmetic unit). (In some cases, the device is built-in), which increases the cost and makes the entire device bulky.

An object of the present invention is to synchronize two arithmetic units without the need to provide a special synchronization device, thereby reducing costs and eliminating bulky devices. The objective is to provide a synchronization method between devices.

[Means to solve the problem]

In each of the first and second arithmetic units each consisting of a one-chip microcomputer equipped with a digital input/output board,
from a certain digital input/output port of the first arithmetic unit to the second
A first synchronization signal line leading to a certain digital input/output port of the arithmetic unit, and a second synchronizing signal line leading from another digital input/output port of the second arithmetic unit to another digital input/output port of the first arithmetic unit. A synchronization signal line is provided.

[Effect]

When the first arithmetic unit is ready for operation, the first arithmetic unit raises the logic level of the first synchronization signal line and enters a standby state, and starts monitoring the second synchronization signal line. When the second arithmetic unit is ready for operation and raises the logic level of the second synchronization signal line, the first arithmetic unit detects this and exits from the standby state and starts operation; In the second arithmetic unit,
Immediately exits the standby state and starts operation from the point where the logic level of the first synchronization signal line has already risen,
By lowering the logic level of each synchronizing signal line at the time of starting the operation, synchronization is achieved between the first arithmetic device and the second arithmetic device.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. In the same figure, 10 is a unit equipped with a digital input/output board.
A calculation device (A) consisting of a chip microcomputer, 11 a calculation device (B) consisting of a one-chip microcomputer equipped with a digital input/output board, 21 a calculation value f(B) from the digital input/output port P2 of the calculation device (A) 10; ) 11, and 22 is a synchronization signal line from the digital input/output port P2 of the arithmetic unit (B) 11 to the digital input/output port P1 of the arithmetic unit (A) 10.

FIG. 2 is a timing diagram showing the signal timing on the synchronization signal line of FIG. 1.

The operation leading to synchronization will be explained with reference to FIGS. 1 and 2.

First, in the arithmetic device (A) 10, timing t.

When synchronization preparation is completed, the logic level of the synchronization signal line 21 changes from O (Low) to 1 (High).
h) and enters the standby state, and the synchronization signal 'f
When the arithmetic unit (B) 11 becomes ready for synchronization at timing 11 after the 0th TO time has elapsed to start monitoring the IA 22, the arithmetic unit (B) 11 changes the logic level of the synchronization signal line 22 to 0. (Low) to 1 (High)
When the processing unit (A) 10 detects this, it exits the standby state and resumes calculation.

On the other hand, when the arithmetic unit (B) 11 also looks at the synchronization signal line 21, the signal level there is already 1 (High), so it immediately exits the standby state and restarts the arithmetic operation.

The signal level of each synchronization signal line is 0 when the calculation is restarted.
(Low). As a result, arithmetic device (A) 1
0 and (B)11 can start calculations at the same timing, and synchronization can be obtained.

Figure 3 shows each CPU in the arithmetic units (A) and (B).
Please refer to this flowchart showing the flow of operations performed by the central processing unit (central processing unit) regarding synchronization.

〔Effect of the invention〕

As explained above, according to the present invention, in order to synchronize two arithmetic units, it is only necessary to connect the existing digital input/output ports using a dedicated digital line to create a synchronization signal line. Since no synchronizer is required, there are advantages in that the cost can be reduced and the volume is not bulky. Furthermore, since handshaking between two arithmetic units can be easily performed, the present invention is easy to implement.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram showing the signal timing on the synchronization signal line in Fig. 1, and Fig. 3 is the flow of operations performed by the CPU in the arithmetic unit regarding synchronization. FIG. 4 is a block diagram for explaining a conventional method of synchronizing two arithmetic units. Explanation of symbols 10.11... Arithmetic unit consisting of a 1-chip microcomputer equipped with digital input/output ports, 21.22... Synchronization signal line agent Patent attorney Akio Namiki

Claims (1)

[Scope of Claims] 1) A method for synchronizing first and second arithmetic units, each of which is a one-chip microcomputer with a digital input/output port, comprising: a certain digital input/output of the first arithmetic unit; 2nd from port
A first synchronization signal line leading to a certain digital input/output port of the arithmetic unit, and a second synchronizing signal line leading from another digital input/output port of the second arithmetic unit to another digital input/output port of the first arithmetic unit. A synchronization signal line is provided, and when the first arithmetic unit is ready for operation, the first arithmetic unit raises the logic level of the first synchronization signal line and enters a standby state, and the second arithmetic unit When the second arithmetic unit starts monitoring the synchronization signal line and raises the logic level of the second synchronization signal line when it becomes ready for operation, the first arithmetic unit detects this and The second arithmetic unit exits from the standby state and starts operating.
Immediately exits the standby state and starts operation from the point where the logic level of the first synchronization signal line has already risen,
A method for synchronizing arithmetic units, characterized in that synchronization is achieved between a first arithmetic unit and a second arithmetic unit by lowering the logic level of each synchronizing signal line at the time of starting operation.