JPH0227233U - - Google Patents
Info
- Publication number
- JPH0227233U JPH0227233U JP10506788U JP10506788U JPH0227233U JP H0227233 U JPH0227233 U JP H0227233U JP 10506788 U JP10506788 U JP 10506788U JP 10506788 U JP10506788 U JP 10506788U JP H0227233 U JPH0227233 U JP H0227233U
- Authority
- JP
- Japan
- Prior art keywords
- task
- memory
- processing unit
- central processing
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 11
- 230000010365 information processing Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
Description
第１図はこの考案の実施例を示す図、第２図は
この考案の実施例を構成するタスクメモリを示す
図、第３図は従来の情報処理装置を示す図、第４
図は従来の情報処理装置を構成するメモリページ
ング装置を示す図である。
図において１は中央処理装置、２はタスクメモ
リ、３はタスク識別信号、４は論理アドレス、５
はレジスタ、６は比較器、７はメモリ、８はメモ
リページング装置、９は物理アドレス、１０は読
み出し書きこみメモリである。なお、図中同一符
号は同一または相当部分を示す。
Fig. 1 is a diagram showing an embodiment of this invention, Fig. 2 is a diagram showing a task memory constituting an embodiment of this invention, Fig. 3 is a diagram showing a conventional information processing device, and Fig. 4 is a diagram showing a conventional information processing device.
The figure shows a memory paging device that constitutes a conventional information processing device. In the figure, 1 is the central processing unit, 2 is the task memory, 3 is the task identification signal, 4 is the logical address, and 5 is the task identification signal.
is a register, 6 is a comparator, 7 is a memory, 8 is a memory paging device, 9 is a physical address, and 10 is a read/write memory. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
おいて、タスク識別信号と論理アドレスを出力す
る中央処理装置と、タスク番号を保持するレジス
タ、前記タスク識別信号と前記タスク番号を保持
するレジスタの出力との値を比較し一致した時メ
モリ選択信号を出力する比較器、前記比較器から
出力されるメモリ選択信号と前記中央処理装置の
論理アドレスを入力しデータを出力するメモリか
らなるタスクメモリを複数備えたことを特徴とす
る情報処理装置。 In an information processing device having a central processing unit and a memory, a central processing unit that outputs a task identification signal and a logical address, a register that holds a task number, and a value of the output of the task identification signal and the register that holds the task number. a comparator that compares and outputs a memory selection signal when they match, and a plurality of task memories each including a memory that inputs the memory selection signal output from the comparator and a logical address of the central processing unit and outputs data. An information processing device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10506788U JPH0227233U (en) | 1988-08-09 | 1988-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10506788U JPH0227233U (en) | 1988-08-09 | 1988-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227233U true JPH0227233U (en) | 1990-02-22 |
Family
ID=31337352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10506788U Pending JPH0227233U (en) | 1988-08-09 | 1988-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227233U (en) |
-
1988
- 1988-08-09 JP JP10506788U patent/JPH0227233U/ja active Pending
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