JPH022710A - Noise reduction circuit - Google Patents
Noise reduction circuitInfo
- Publication number
- JPH022710A JPH022710A JP63150496A JP15049688A JPH022710A JP H022710 A JPH022710 A JP H022710A JP 63150496 A JP63150496 A JP 63150496A JP 15049688 A JP15049688 A JP 15049688A JP H022710 A JPH022710 A JP H022710A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- current
- circuit
- output
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 abstract description 3
- 101150015217 FET4 gene Proteins 0.000 abstract 4
- 101150073536 FET3 gene Proteins 0.000 abstract 1
- 101150079361 fet5 gene Proteins 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はIC設計における内部ノイズを低減するノイ
ズ低減回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise reduction circuit that reduces internal noise in IC design.
第2図は従来の出力回路の回路図で、図において、(1
)、(2)はそれぞれデータ信号及び出力制御用信号端
子、(3)は1Hルベル出力用バッフ1トランジスタ、
(4)は1Lルベル出力用バッファトランジスタである
。これらの回路が出力ピン(6)の数C図においてはn
組)だけ1源パッド(7)とGNDパッド(8a)の間
に接続されている。Figure 2 is a circuit diagram of a conventional output circuit.
), (2) are data signal and output control signal terminals, respectively, (3) is a buffer 1 transistor for 1H level output,
(4) is a buffer transistor for 1L level output. These circuits have the number of output pins (6).
1) is connected between the source pad (7) and the GND pad (8a).
次に動作について説明する。センス・アンプにより増幅
されたデータは入力端子(1)又は(2)よりの信号に
よって、出力用バッファトランジスタ(3)、(4)の
1方をON状態に、他方をOFF状態にする。Next, the operation will be explained. The data amplified by the sense amplifier turns on one of the output buffer transistors (3) and (4) and turns the other one off in response to a signal from the input terminal (1) or (2).
この事によって出力データが5H′又は1L′と判定さ
れる。This determines that the output data is 5H' or 1L'.
従来の出力回路は以上のように構成されていたので、出
力データが1L′から4)(#、又は% H1から%L
′に反転する時、降圧時間(tf)、昇圧時間(tr)
によりトランジスタ(3)、(4)に貫通電流が流石、
この貫通電流は出力ピン数が多くなればなるほど総ヱ流
は増加する。瞬時に流れる電流に対し出力回路の9流供
給能力が不充分であったカ、又瞬時の配線抵抗等により
、電圧の変動が発生する。この電圧変動により内部の見
掛は上のしきい値が変化し、誤動作を起こすという問題
点があった。Since the conventional output circuit is configured as above, the output data is 1L' to 4) (#, or %H1 to %L).
’, step-down time (tf), step-up time (tr)
As expected, a through current flows through transistors (3) and (4).
The total through current increases as the number of output pins increases. Voltage fluctuations occur because the output circuit's ability to supply 9 currents is insufficient for the instantaneous current flowing, or because of instantaneous wiring resistance. This voltage fluctuation causes the apparent internal threshold value to change, causing a problem of malfunction.
この発明は上記のような間閥点を解決するためになされ
たもので、瞬時に流れる貫通電流を制御する事1ζより
、電圧の変動を抑制し誤動作の原因を取り除くことを目
的とする。This invention was made to solve the above-mentioned problem, and aims to suppress voltage fluctuations and eliminate causes of malfunction by controlling instantaneous through-current.
この発明に係るノイズ低減回路は1圧変動を感知して出
力バッファトランジスタのゲート電圧を制御し、貫通電
流を制御することにより電圧変動を抑制するもσ)であ
る。The noise reduction circuit according to the present invention senses voltage fluctuations, controls the gate voltage of the output buffer transistor, and suppresses voltage fluctuations by controlling through current.
この発明における貫通電流の制御回路は微小な電圧変動
を感知することにより動作を開始し以後の電圧変動を抑
制してノイズの低減をする。The through current control circuit according to the present invention starts operation by sensing minute voltage fluctuations, suppresses subsequent voltage fluctuations, and reduces noise.
以下、この発明の一実施例を図について説明する。第1
図において、符号(1)〜(4)および((3)〜(8
a)は前記従来び)ものと同じである。(5)は出力バ
ッファトランジスタ(2)のソースをゲート信号とし、
ゲート信号をドレインとし、別GNDパッド(8b)を
ソースとした9流制御トランジスタである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, symbols (1) to (4) and ((3) to (8)
A) is the same as the conventional method and). (5) uses the source of the output buffer transistor (2) as a gate signal,
It is a 9-flow control transistor with the gate signal as the drain and another GND pad (8b) as the source.
次に動作について説明する。前記従来の出力回路で説明
した様に貫通電流により、バッファトランジスタ(4)
のソース電圧が一瞬持ち上げられる。Next, the operation will be explained. As explained in the conventional output circuit, the buffer transistor (4)
The source voltage of is momentarily raised.
電流制御トランジスタ(5)は低しきい値N型トランジ
スタにし、ゲート電圧の微小上昇にも反応する様設定し
ておくと、バッファトランジスタ(4)のソース電圧の
上昇により電流制御トランジスタ(5)はターン・オン
し、バッファトランジスタ(4)のゲート電圧を供給し
ているNOR回路のPiバッファトランジスタ(3]と
の間で抵抗を介した状態のパスができ、第2図における
0点はトランジスタ(9)、α0及び(5)の抵抗比に
よって電源常圧レベルより降下する。この事はバッファ
トランジスタ(4)のゲートとソース間電圧の降下を意
味し、バッファトランジスタ(4)の電流を抑制する方
向に鋤六%畢圧変動をも抑制する。If the current control transistor (5) is a low-threshold N-type transistor and is set to respond to a slight increase in gate voltage, the current control transistor (5) will When it is turned on, a path is created via a resistor between the Pi buffer transistor (3) of the NOR circuit that supplies the gate voltage of the buffer transistor (4), and the 0 point in Fig. 2 is the transistor (3). 9), α0, and the resistance ratio of (5) causes the voltage to drop below the normal voltage level of the power supply.This means that the voltage between the gate and source of the buffer transistor (4) drops, suppressing the current in the buffer transistor (4). It also suppresses the plow pressure fluctuation by 6% in the direction.
第3図及び第4図はこの発明の回路のシミュレーション
に使用した回路及び出力波形を示す。このシミュレーシ
ョンでは模擬的にGNDの上昇を作るためコイル成分を
使用した。第4図のうミュレーシぢン結果からもこの手
段によって常圧の変動を抑制できる事がわかる。3 and 4 show the circuit and output waveforms used in the simulation of the circuit of the present invention. In this simulation, a coil component was used to simulate a rise in GND. The simulation results shown in Figure 4 also show that fluctuations in normal pressure can be suppressed by this means.
以上のようにこの発明によれば、常圧の変動を感知する
手段により、S’ff圧変動を抑制でき、この電圧変動
の抑制にともなうノイズの防止及び、ノイズマージンを
あげる効果がある。As described above, according to the present invention, S'ff pressure fluctuations can be suppressed by means of sensing fluctuations in normal pressure, and noise accompanying the suppression of voltage fluctuations can be prevented and the noise margin can be increased.
第1図はこの発明の一実施例を示す出力回路の回路図、
第2図はこの発明の動作時の電流パスを示す説明回路図
、第3図は第1図の回路のシミュレーションに使用した
回路図、第4図はシミュレーションによ−て得られた貫
通電流の波形図、第5図は従来の出力回路の回路図であ
る。
図において、(1)(2)は入力信号及び出力制御信号
端子、(3)はP型バッファトランジスタ、(4)はN
型バッファトランジスタ、(5]は電流制御トランジス
タ、 (6a)〜(6n)は出力パッド、(7)は電源
パッド、(8a) 、(8b)はGNDパッド、(91
,QdはP型トランジスタ、α力は出力データ、υは従
来回路の出力バッファゲート¥α圧、(至)はこの発明
の出力バッファゲートで圧、α4は従来回路のGNDレ
ベル、(至)はこの発明のGNDレベルを示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a circuit diagram of an output circuit showing an embodiment of the present invention;
Fig. 2 is an explanatory circuit diagram showing the current path during operation of the present invention, Fig. 3 is a circuit diagram used for simulating the circuit of Fig. 1, and Fig. 4 shows the through current obtained by the simulation. The waveform diagram in FIG. 5 is a circuit diagram of a conventional output circuit. In the figure, (1) and (2) are input signal and output control signal terminals, (3) is a P-type buffer transistor, and (4) is an N
type buffer transistor, (5) is a current control transistor, (6a) to (6n) are output pads, (7) is a power supply pad, (8a) and (8b) are GND pads, (91)
, Qd is a P-type transistor, α power is output data, υ is the output buffer gate of the conventional circuit ¥ α pressure, (to) is the output buffer gate of this invention and is the voltage, α4 is the GND level of the conventional circuit, (to) is The GND level of this invention is shown. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
も抑制する機能を備えたノイズ低減回路Noise reduction circuit that suppresses through current that causes voltage fluctuations and also suppresses voltage fluctuations.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63150496A JPH022710A (en) | 1988-06-17 | 1988-06-17 | Noise reduction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63150496A JPH022710A (en) | 1988-06-17 | 1988-06-17 | Noise reduction circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH022710A true JPH022710A (en) | 1990-01-08 |
Family
ID=15498136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63150496A Pending JPH022710A (en) | 1988-06-17 | 1988-06-17 | Noise reduction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH022710A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221646A (en) * | 1988-07-08 | 1990-01-24 | Fujitsu Ltd | Semiconductor device |
JPH02264518A (en) * | 1989-04-03 | 1990-10-29 | Nec Ic Microcomput Syst Ltd | Output circuit for semiconductor integrated circuit element |
JPH0541655A (en) * | 1991-08-06 | 1993-02-19 | Nec Ic Microcomput Syst Ltd | Output buffer circuit |
JPH11202970A (en) * | 1998-01-19 | 1999-07-30 | Toshiba Microelectronics Corp | Clock skew preventing circuit |
US9000810B2 (en) | 2012-12-18 | 2015-04-07 | Fujitsu Limited | Quantizer, comparator circuit, and semiconductor integrated circuit |
-
1988
- 1988-06-17 JP JP63150496A patent/JPH022710A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221646A (en) * | 1988-07-08 | 1990-01-24 | Fujitsu Ltd | Semiconductor device |
JPH02264518A (en) * | 1989-04-03 | 1990-10-29 | Nec Ic Microcomput Syst Ltd | Output circuit for semiconductor integrated circuit element |
JPH0541655A (en) * | 1991-08-06 | 1993-02-19 | Nec Ic Microcomput Syst Ltd | Output buffer circuit |
JPH11202970A (en) * | 1998-01-19 | 1999-07-30 | Toshiba Microelectronics Corp | Clock skew preventing circuit |
US9000810B2 (en) | 2012-12-18 | 2015-04-07 | Fujitsu Limited | Quantizer, comparator circuit, and semiconductor integrated circuit |
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