JPH0221646A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the voltage of the VSS pad of a semiconductor chip from becoming higher than 0V when the output of a semiconductor device changes from an 'H' level to an 'L' level, by a method wherein, according to a transistor capability detection signal, a gate voltage controlling circuit changes the gate voltages of transistors. CONSTITUTION:When a detecting transistor in a transistor capability detection circuit 34 detects that the power supply voltage from a VCC pad 16-1 is high, or that the environmental temperature is low, the detection circuit 34 supplies a detection signal 36 indicating the above facts to a gate voltage controlling circuit 38, which supplies gate voltage controlling signals 40, 40 to transistors 22, 24, according to the detection signal 36. Thereby the gate voltages of the transistors 22, 24 are decreased, so that the conductances of the transistors 22, 24 become small. As a result, the capability to drive a power supply decreases and therefore the peak current of the transistors 22, 24 are decreased.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device, and particularly to an output circuit for suppressing malfunction due to noise that occurs when the output of the semiconductor device changes. To provide a semiconductor device which can prevent the voltage of a vss pad of a semiconductor chip from becoming higher than OV when changing from to "L" level, prevent malfunction of the device, and improve reliability. A transistor capability detection circuit having a detection transistor and outputting a signal corresponding to the transistor capability; and an output transistor in the output circuit based on the detection signal. and a gate voltage control circuit that changes the gate voltage of the gate voltage.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to an output circuit for suppressing malfunction due to noise that occurs when the output of a semiconductor device changes.

In recent years, digital semiconductor devices such as memory elements and logic elements are required to operate at high speed. For this reason, in semiconductor devices, the current suction ability and current supply ability of the output circuit are increased in order to drive the load at high speed. However, when a load is driven at high speed, a capacitive component (stray capacitance) included in the load is charged and discharged at high speed, and a large peak current is generated as a result of this charging and discharging. This peak current is
When a current is applied to a semiconductor chip (a), it acts on various inductance components existing in the wiring paths that supply it, and causes large fluctuations in the power supply voltage and ground voltage, which are the reference voltage of the chip. This fluctuating voltage acts as noise. However, semiconductor devices may malfunction, and countermeasures are required.

[Conventional technology]

FIG. 7 shows the appearance of a conventional semiconductor device.

In FIG. 7, there is a semiconductor chip 1 in the package 10.
2 is stored and the terminals 14.14.14 of the package 10
... are connected to a plurality of pads 16 of the semiconductor chip 12 via a plurality of bonding wires 18.

. FIG. 8 shows a circuit of the semiconductor device of FIG. 7.

In FIG. 8, ■cc terminal 14-1 of package 10
, V, terminal 14-2. The output terminal 14-3 is connected to the ■cc pad 16-1, Vss pad 16-2, and output pad 16-3 of the semiconductor chip 12 through bonding wires 18-1, 18=2, and 18-3. The connected "cc" terminal 14-1 is connected to a power supply voltage of 5V, and the V3311'di terminal 14-2 is connected to the OV node 14-1.
The ground (cran F) is connected to the voltage, and the output terminal 14-3
is grounded to 0 via a capacitor 20 serving as a load capacitance. The circuit inside the semiconductor chip 12 will be explained below. The semiconductor chip 12 includes a P-channel transistor 22 and an N-channel transistor 24 connected in series. One end of the P-channel transistor 22 is connected to the Vcc pad 16-1, and one end of the N-channel transistor 24 is connected to the Vcc pad 16-1. S S Hara l-1
6-2, and the curved ends of both transistors 22 and 24 are connected to each other and to the output pad 16-3.
It is connected to the.

The gate of P-channel transistor 22 is NAND26
The gate of N-channel transistor 24 is connected to the output terminal of N0R28. NAN
The internal control signal A and internal data signal DATA are supplied as they are to the input terminal of D26, and the internal data signal DATA is supplied as they are to the input terminal of N0R28.
Internal control No. 12 A is inverted by an inverter (inverting circuit) 30 and then supplied.

Next, the operation of the circuit will be explained.

In normal use, the internal control signal A is at the “1■” level, and at this time, the internal data signal DATA is at the “H” level.
If the level is high, the NAND 26 becomes the "HI" level and the N0R28 becomes the "L" level. Therefore, the gates of both transistors 22 and 24 are both at the "high" level, the P channel transistor 22 is turned on, and the N
Channel transistor 24 is turned off. Therefore, the current of 5■ is: ■CO terminal 14-1 bonding wire 18-1, ■CC pad 16-1, P channel transistor 22, output pad 16-3, bonding wire 18-3, output terminal 14- 3, the voltage flows to the capacitor 20, and the capacitor 2° is charged to reach the "1 level".

Next, when the internal data signal D A T'A goes to the "S" level, the NAND26 goes to the "T" level, and the N0R
28 becomes "1B level. Therefore, the gates of both transistors 22 and 211 become 'H' level,
P-channel transistor 22 is turned off, and N-channel transistor 24 is turned on. Therefore,
Current flows from the capacitor 20 to the output terminal 14-3, the bonding wire 18-3, the output pad 16-3, the N-channel transistor 24, the Vss pad 16-2, the bonding wire 18-2, and the SS terminal 14-2. The capacitor 2o is discharged and becomes the ``I2 level''.

In addition, internal control No. 18A is "I-" under normal usage conditions.
It is F level, and at "L" level it becomes a special mode. In this special mode, the internal data signal DATA
Regardless of whether it is at the F level or the "L" level, the output of the NAND26, that is, the gate of the P channel transistor 22, goes to the H level, and the output of the N0R28, that is, the N channel 24 gates are L
Therefore, both transistors 22 and 24 are turned off, and the output signal to the capacitor 20 is in an electrically floating state called high impedance.

[Problem to be solved by the invention]

In the circuit shown in FIG. 8 above, V CCP6'H child 14-
1 and ■ a bonding wire 18-1 that connects the cc pad 16-1, and ■ a bonding wire 18- that connects the terminal 14-2 and the ssS pad 16-2.
2, there is an inductance component of the wiring, L2, respectively, and these inductance components, L2, cause problems as described below.

The capacitor 20 is charged and the capacitor 20 becomes “L”
When the level changes from level to “),” the current of 5■ becomes,
■cc terminal 14-1. Bonding wire 18-1,
Vcc pad 16-1, P channel transistor 22,
The current flows to the capacitor 20 via the output pad 16-3, the bonding wire 18-3, and the output terminal 14-3. At this time, current flows through the bonding wire 18-1, but due to the inductance component L1 of the bonding wire 18-1, both ends of the bonding wire 18-1, that is, the "cc terminal 14-1" and the "cc pad 16-1" 1, a potential difference occurs. Please refer to the following equation.

(2) -; -L (d i / d t ) Here, (2) is the potential difference, L is the inductance, 1 is the current, and 1 is the time.

Therefore, since there is a potential difference between both ends of the bonding wire 18-1, the voltage of the cc pad 16-1 becomes lower than 5V instead of 5V.

Further, when the capacitor 20 is discharged and the capacitor 20 changes from the "H" level to the "L" level, the current from the =1 capacitor 20 flows to the output terminal 14-3, the bonding wire 183, the output pad 16-3, the N It flows to ground via the channel transistor 24, the Vss pad 16-2, the bonding wire 18-2, and the "SS" lead 14-2. At this time, the bonding wire 18-2
Although current flows through the bonding wire 18-2 due to the inductance component L2 of the lead wire 18-2.
Both ends of VSS pad 16-2 and V33 terminal 14
-2. Therefore, the voltage at ■ss pad 16-2 is not 0■ but higher than Ov.

As described above, when the output of the semiconductor chip 12 changes from the "L" level to the "F" level or from the "H" level to the "L" level due to the charging and discharging of the capacitor 20, the voltage of the Vcc pad 16-1 changes. The voltage fluctuates from 5■, or the voltage of the ss pad 16-2 fluctuates from 0■.

Since the semiconductor device is given an input signal based on the external OV, the Vss of the semiconductor chip 12 is
If the voltage of the pad 16-2 becomes higher than 0■, the semiconductor device will not operate normally, and the (8II performance) will decrease.
The fact that the voltage of 1 becomes lower than 5■ does not pose a problem in the operation and reliability of the semiconductor.

Note that both transistors 2 are required for high-speed operation of the semiconductor device.
When the current drive capacity of 2 and 24 is increased, the peak current becomes larger, and the inductance component L1゜L of the bonding wire 18-1.
-1, ■ Voltage fluctuation of ss pad 16-2 increases (
(see formula above).

Although the above description assumes that malfunctions are caused by fluctuations in the power supply voltage, fluctuations in ambient temperature are also a factor in malfunctions, and the driving ability of the transistor may be affected by these fluctuations in ambient temperature.

An object of the present invention is to reduce the Vss of the semiconductor nap when the output of the semiconductor device changes from the ") level" to the "°L" level.
It is an object of the present invention to provide a semiconductor device that can prevent the voltage of a pad from becoming higher than Ov, prevent malfunction of the device, and improve condylarity.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the present invention.

In FIG. 1, the output circuit 32 includes a P-channel transistor 22 and an N-channel transistor 24. When the transistor 22 is in the ON state and the transistor 24 is in the OFF state, the current from the vcc pad 16-1 passes through the transistor 22. flows to the output pad 16-3, and
Transistor 22 is OFF and transistor 24 is OFF.
In the N state, current from output pad 16-3 flows through transistor 24 to Vss pad 16-2.

The transistor capability detection circuit 34 includes a detection transistor, and outputs a detection signal 36 based on the power supply voltage from the CC pad 16-1 and the ambient temperature applied to the detection transistor.

This detection signal 36 is sent to the gate voltage control circuit 38.
Based on the detection signal 36, the control circuit 38
Outputs gate voltage control signal 40.40. As a result, in the output circuit 32, the output transistor 22.2
The gate voltage of transistor 4 is controlled, the current driving capability of transistors 22 and 24 is changed, and the current flowing through transistor 22 and the current flowing through transistor 24 are changed.

[Function] 1- The conductance of a transistor changes depending on the gate voltage or ambient temperature. For example, in an N-channel transistor, the higher the gate voltage or the lower the ambient temperature, the greater the conductance. Note that the usage conditions of the semiconductor device are, for example, a power supply voltage of 5V±10% and an ambient temperature of 0 to 70°C. When the conductance of the output 1-transistor increases, the current 1-current driving capacity of the output transistor increases, and the current flowing through the output transistor increases, so that the operating speed IX of the output transistor increases. However, the peak current of the output transistor increases, and as described above, this acts on the inductance component of the bonding wire, causing a potential difference between both ends of the bonding wire, resulting in voltage fluctuations at the (1) pad and (2) ss pad.

C Therefore, when the power supply voltage ■co is high, the gate voltage is lowered to decrease the conductance of the output transistor, and the current drive capability of the output 1 transistor is decreased.
Reduces the current flowing through the output transistor. This reduces the peak current of the output transistor, and therefore does not act on the inductance component of the bonding wire and create a potential difference across the bonding wire, thereby preventing voltage fluctuations at the ■ pad and ■ ss pad. In this case, although the operating speed of the output transistor is slow, the operating speed of other parts of the semiconductor device other than the output circuit is fast, so the peak current can be reduced without reducing the overall operating speed. can achieve a reduction in

The above will be explained with reference to FIG.

When the detection transistor in the transistor capability detection circuit 34 detects that the power supply voltage from the VCC pad 16-1 is high or that the ambient temperature is low, the detection circuit 34 outputs a detection signal 36 to that effect. The control circuit 38 supplies the gate voltage control ν signal 40.40 to the transistor 2 based on the detection signal 36.
Supply on 2.24. This causes transistor 22.
Since the gate voltage of transistor 24 is lowered, the conductance of transistor 22.24 becomes smaller and its current resource capability becomes smaller, hence transistor 22.24
peak current is reduced.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 2 shows a circuit of a semiconductor device according to an embodiment of the present invention, and in the circuit of FIG. 2, the same or overlapping parts as the circuit of FIG. 8 are given the same reference numerals and explained. omitted.

In FIG. 2, the transistor capability detection circuit 34 includes a resistor 42 as a load and an N-channel transistor 44 for detection connected in series with the resistor 42. One end of the resistor 42 is connected to a vcc pad 16- 1, one end of transistor 44 is connected to vss pad 16-2, the gate of transistor 44 is connected to Vcc pad, and resistor 42 and transistor 4
The output from the connection with 4 becomes the detection signal 36. Note that the resistor 42 is made of polysilicon, for example.
Its resistance value is the power supply voltage ■. 0 and ambient temperature.

In the detection circuit 34, when the power supply voltage Vcc is low, the gate voltage of the transistor 44 is low, so the conductance of the transistor 44 is small and the voltage of the detection signal 36 is high. 0 is high, the gate voltage of transistor 44 is high, so transistor 4
The conductance of the transistor 44 is large and the voltage of the detection signal 36 is low. FIG. 3 shows the relationship between the conductance of such a transistor 44 and the voltage of the detection signal 36.

Next, in the gate voltage control circuit 38, the NAND 26
, N0R28, and inverter 30 are the same as the corresponding parts in FIG. 8 above. And, Fig. 4(a)(b)(
c) inverter 30, NAND26, and N0R2
The internal circuits of 8 are shown in FIGS. 5(a), (b), and (c), respectively.
) are shown correspondingly.

In FIG. 2, NAND26. The power supply side of the inverter 30 is connected to the CC pad 16-1 and has a power supply voltage of ■.

0 is supplied as is, but note that the power supply side of N0R 28 is connected to a detection circuit 34 and a detection signal 36 is supplied.

Therefore, the NAND 26 is supplied with the power supply voltage Vcc as it is (j), so if the voltage TA voltage V.0 is high, the NAND 26 transmits a high
Supply to 2. Therefore, the conductance of the transistor 22 increases, the current driving ability increases, and a peak current flows through the transistor 22.

On the other hand, the detection signal 36 is supplied to the N0R28, and the power supply voltage ■. When 0 is high, the voltage of the detection signal 36 is low, as described above, so the N0R 26 supplies a low gate voltage to the transistor 24. Therefore, the conductance of the transistor 24 is reduced, the current driving capability is reduced, and the peak current flowing through the transistor 24 is reduced.

The above will be explained with reference to the timing chart of FIG.

When the power supply voltage V is low, for example, V cc” 4,5
In the case of C ■, the level of the output signal changes from “G ■” level to “
When changing to the L'' level, it is performed over time 1 to t, and is performed for a long time 1.

Therefore, a large peak current does not occur in the output signal current.

On the other hand, if the power supply voltage ■co is high, for example ■. 0=5.
In the case of 5V, when the L level of the output signal changes from the "H" level to the "L" level, conventionally, as shown by the broken line, this is done over time t1 to t2, and is done in a short time T2. As a result, the output signal current is
As shown by the broken line, a large peak current would occur.

However, in the embodiment of the present invention, when the power supply voltage oo is high, that is, 5.5V, the voltage of the detection signal 36 is low, so the change from the "H" level to the "L" level is indicated by a solid line. As shown in FIG. Therefore, the current of the output signal does not have a large peak current, as shown by the solid line.

As described above, according to the embodiment of the present invention, when the level of the output signal changes from the "1" level to the "L" level, when the power supply voltage V.0 is a high value, that is, 5.5" , since the voltage of detection No. 18 36 from the power supply voltage detection circuit 34 is low, N0R28 in the gate voltage control circuit 38
provides a low gate voltage to transistor 24. This reduces the conductance of the transistor 24, reduces the current driving ability, and increases the
Because it will take a long time to change the level! - This means that the peak current flowing through the lamp stand 24 can be reduced.

Therefore, by applying 114 to the inductance component L2 of the bonding wire 18-2, a large potential difference is not generated between the ends of the bonding wires 18-2, and the voltage fluctuation of the pad 16-2, that is, rising from OV, is prevented. can do. Note that in this case, since circuits other than the output circuit operate at high speed, the operating speed of the semiconductor device as a whole does not slow down.

In the above embodiment, the gate voltage of the transistor 24 is controlled, but the NA in the gate voltage i control circuit 38
Power supply voltage ■ to ND26. It is also possible to control the gate voltage of the transistor 22 by applying the detection signal 36 from the detection circuit 311 instead of applying 0.

〔Effect of the invention〕

As explained above, according to the present invention, the gate voltage control circuit changes the gate voltage of the output transistor based on the transistor capability detection signal, and when the power supply voltage is high, the gate voltage of the output transistor changes. Since the gate voltage is lowered, the conductance of the output transistor is reduced, the current drive capability is reduced, and the peak current is reduced. Therefore, when the output of the semiconductor device changes from the "H" level to the "L" level, the voltage of the ss pad changes to OV due to the interface component of the bonding wire.
This prevents the semiconductor device from becoming more expensive, and prevents the semiconductor device from becoming unstable, thereby improving reliability.

Note that in the present invention, when the conductance of the output transistor is small due to a low power supply voltage or high ambient temperature, it is also possible to drive the output transistor at high speed by increasing the gate voltage of the output transistor.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, and Fig. 3 is a diagram showing the conductance of the detection transistor and the detection f.
A graph showing the relationship with the voltage of No. a, No. i f21
(a), (b), and (c) are symbol diagrams that do not show inverters, NAND, and NOR, respectively, and Fig. 5 (a)
(b) and (c) are respectively shown in Figure 4 (a) (IJ)
(c) A circuit diagram of the inverter, NAND, and N0fl; Figure 6 is a timing chart diagram of the circuit in Figure 2; Figure 7 is an external view of the semiconductor device; Figure 8 is a circuit diagram of the semiconductor device in Figure 7; It is a road map. 22.24... Output transistor, 32... Output circuit, 34... Transistor ability detection circuit, 36... Detection signal, 38... Gate voltage control circuit, 40.40... Gate voltage control Signal, 44...detection transistor. 341 “Contactors and 4 resistances of sliding door transisisters”
No. 1 and DzY system Fig. 3 inverter AND (b) Fig. 4 Fig. 5 OR (C) (C)

Claims (1)

[Claims] An output circuit (3) having output transistors (22, 24)
2), which includes a detection transistor (44) and a detection transistor (44);
4) a transistor ability detection circuit (34) that outputs a signal corresponding to the ability; and a gate voltage control that changes the gate voltage of the output transistor (22, 24) in the output circuit (32) based on the detection signal. A semiconductor device comprising: a circuit (38).