JP2682725B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a substrate potential generator for generating a substrate potential of a semiconductor integrated circuit, the substrate for maintaining the generated substrate potential at a set potential. The present invention relates to improvement of a potential detection circuit.

(Prior Art) A conventional substrate potential detector is shown in FIG. In the figure, Qp47, Qn46 and Qn47 are MOS transistors, 45 is an external power supply voltage Vcc, and 46 is a ground potential Vss. Also, 41 is a contact point, 44
Is a substrate potential, and 43 is an output terminal of a substrate potential detection signal. MOS transistors Qp47 and Qn46 whose gates are connected to the ground potential Vss46 and MOS whose gates and drains are short-circuited
Connect three with transistor Qn47 in series, and
The diode of the MOS transistor is connected in series between the external power supply voltage Vcc45 and the substrate potential 44.

The operation of the substrate potential detector having the above configuration will be described. First, in the MOS transistor Qp47, the gate potential is the ground potential Vss46, the source potential is the external power supply voltage Vcc45, and the gate-source voltage is lower than the threshold voltage. Idp47 is playing.

Now, if the substrate potential 44 is lowered below the set potential lower than the ground potential Vss46, the transistor Qn47 is turned on, and the on-state causes the potential of the contact 41 (that is, the source potential of the transistor Qn46) to change to the MOS transistor Qn46.
Since the voltage is lowered by a voltage higher than the threshold voltage of n46, this transistor Qn46 is also turned on.
As a result, the drain potential of the MOS transistors Qp47 and Qn46, that is, the output terminal, depends on the on state of the three transistors.
The substrate potential detection signal 43 has a potential low enough to stop the operation of the substrate potential generator 1.

On the other hand, when the substrate potential 44 rises to a potential higher than the above-mentioned set potential, the MOS transistor Qn47 reduces the potential of the contact 41 to a lesser extent, so that the gate-source voltage of the MOS transistor Qn46 decreases. Since the voltage stays below the threshold voltage or slightly above the threshold voltage, the MO
The S-transistor Qn46 can only turn off or pass a very small current. Therefore, the substrate potential detection signal of the output terminal 43 is
The drain current Idp47 of the transistor Qp47 provides a sufficiently high potential for operating the substrate potential generator 1.

Therefore, when the substrate potential 44 drops below the above-mentioned set potential, the operation of the substrate potential generator 1 is stopped by the low-potential substrate potential detection signal output from the output terminal 43, while the substrate potential 44 is above the set potential. When the voltage rises to 1, the substrate potential 44 can be maintained at the set potential by operating the substrate potential generator 1 by the high potential substrate potential detection signal of the output terminal 43.

(Problems to be Solved by the Invention) However, it has been found that the substrate potential 44 cannot be maintained at the set potential due to the fluctuation of the external power supply potential Vcc45 in the above-described conventional configuration. In other words, the external power supply potential Vcc45
When the voltage rises, the MOS transistor Qp47 has a constant gate potential (ground potential Vss46), so
The gate-source voltage of Qp47 increases, and its drain current Idp47 increases. Therefore, even if the substrate potential 44 is lowered below the set potential, the potential of the substrate potential detection signal of the output terminal 43, which is the drain potential of the MOS transistor Qp47, continues to rise, and the operation of the substrate potential generator 1 continues. Since the voltage does not drop until it is stopped, a malfunction occurs in which the substrate potential 44 drops too much below the set potential.
On the contrary, when the external power supply potential Vcc drops, the gate-source voltage of the MOS transistor Qp47 drops and its drain current Idp47 decreases, so that before the substrate potential 44 is lowered below the set voltage. , The potential of the substrate potential detection signal of the output terminal 43, which is the drain potential of the MOS transistor Qp47, drops significantly.
There is a problem in that there is a possibility of causing a malfunction that the operation of the substrate potential generator 1 is stopped even when 44 is not good above the set potential. The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of satisfactorily holding a substrate potential generated from a substrate potential generator at a set potential even when the external power supply voltage varies. To do.

(Means for Solving the Problem) In order to achieve the above-mentioned object, in the present invention, an internal voltage having a small dependency of the external power supply voltage Vcc is generated in an internal circuit, and based on this internal voltage and the actual substrate potential. Then, the substrate potential detection signal is generated to make the substrate potential detection signal less dependent on the external power supply voltage Vcc, and the operation of the substrate potential generator is controlled by the substrate potential detection signal.

That is, a specific solution of the present invention is, as a semiconductor device, a substrate potential generator that generates a substrate potential, and an internal voltage generation that generates an internal voltage that is less dependent on an external power supply voltage at least within an operating voltage of a DRAM. And a substrate potential detector that detects whether the substrate potential generated by the substrate potential generator is above or below a set potential based on the internal voltage generated by the internal voltage generator and the actual substrate potential. The substrate potential generator is provided and controlled by the output of the substrate potential detector.

(Operation) According to the present invention, due to the above-described configuration, the internal voltage generator generates an internal voltage having less dependence on the external power supply voltage, and the substrate potential detector operates based on this internal voltage and the actual substrate potential. . As a result, even if the external power supply voltage fluctuates, when the actual substrate potential is less than the set potential, the substrate potential detector always outputs a low-potential substrate potential detection signal. In this case, the substrate potential detection signal of high potential is always output, so when the operation of the substrate potential generator is controlled by this substrate potential detection signal having a small dependency on the external power supply voltage, the substrate potential is below the set potential. At times, the operation of the potential generator is always stopped, and the substrate potential is held at the set potential regardless of the fluctuation of the external power supply voltage Vcc.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a semiconductor device according to a first embodiment of the present invention. In the figure, Qp11 to Qp17 are P
Type MOS transistors, Qn11 to Qn17 are N type MOS transistors, 15 is an external power supply voltage Vcc, 16 is a ground potential Vss, 11 is an internal voltage, 12 is a reference voltage, 13 is a substrate potential detection signal, 14 is a substrate potential, 111, 112, 121, 122, 131 are contact points.

Reference numeral 2 denotes an internal voltage generator for generating an internal voltage 11 having less dependence on the external power supply voltage Vcc15. The internal voltage generator 2 is an internal voltage generator for generating a voltage for operating internal elements. It consists of a step-down device. The internal voltage down converter 2 is composed of a reference voltage generator 3 and a supply device 4. First, the operation of the reference voltage generator 3 will be described. The reference voltage generator 3 includes two transistors Qp11 and
Qn11 and two transistors Qp12 and Qn12 are connected in series, and both are connected in parallel to the external power supply voltage Vcc15, and a transistor is connected between the source and drain of the MOS transistor Qp12. Qp13
The diode is connected.

The transistors Qp11 to Qp13 and the transistors Qn11 to
All Qn12 operates in the saturation region.

In this reference voltage generator 3, the reference potential 12, that is, the contact 1
The potential of 12 is configured to have little dependence on the external power supply voltage Vcc15. Hereinafter, this configuration will be specifically described. When the potential of the contact 112 is almost constant, the transistor Qn11 operates in the saturation region because its gate potential is a constant potential of the contact 112, and its source potential is the ground potential Vss16, and its gate and source are Since the voltage between them is almost constant, the drain current Idn11 is almost constant. Further, when the drain currents Idp11 and Idn11 of the transistors Qp11 and Qn11 are equal to each other, the transistor Qp1
The drain potential and the gate potential of 1 are the potential of the contact 111 in the steady state. Therefore, the drain current Idp11 of the transistor Qp11 in the steady state is almost constant. On the other hand, the drain current Idp11 of the transistor Qp11 is almost determined by the voltage between the gate and the source due to the operation in the saturation region. Therefore, if the drain current Idp11 is almost constant as described above, the gate and the source thereof are The voltage between them is almost constant. From the above, the contact 111, which is the gate-source voltage of the transistor Qp11, and the external power supply voltage Vcc.
The potential difference between 15 and 15 is almost constant.

The gate-source voltage of the transistor Qp12 is
Since the potential difference between the contact 111 and the external power supply voltage Vcc15 is almost constant as described above, this transistor Qp12
The drain current Idp12 is almost constant due to the operation in the saturation region. Further, the drain potential and the gate potential of the transistor Qn12 when the drain currents Idp12 and Idn12 of the transistors Qp12 and Qn12 are equal to each other are the potential of the contact 112 in the steady state (that is, the reference potential 12). Therefore, the drain current of transistor Qn12 in the steady state
Idn12 is almost constant. On the other hand, this transistor Qn12
Since the drain current Idn12 of is substantially determined by the gate-source voltage due to the operation in the saturation region, if the drain current Idn12 is almost constant as described above,
The gate-source voltage is also almost constant. From the above, the potential difference between the contact 112, which is the gate-source voltage of the transistor Qn12, and the ground potential Vss16 is substantially constant.

As described above, since the reference voltage generator 3 is the feedback circuit having the above-mentioned configuration, the contact 11
It can be seen that the potential of 1 becomes a constant voltage lower by a predetermined potential than the external power supply voltage Vcc15, and the potential of the contact 112 becomes a reference potential of a constant potential higher by a predetermined potential than the ground potential Vss16.

In the semiconductor device of the present invention, the reference potential 12, that is, the ground potential Vss, is set as the voltage having little dependence on the external power supply voltage Vcc15.
The potential of the contact 112 which is higher than 16 by a constant potential is used.

Next, the operation of the feeder 4 will be described. This feeder 4 comprises a differential amplifier 5 composed of two p-type MOS transistors Qp14 and Qp15, three n-type MOS transistors Qn13 to Qn15, and one p-type MOS transistor Qp16. It is composed of an output circuit section 6 that is configured.

Describing from the differential amplifier 5, the two MOS transistors Qp14 and Qp15 are configured such that their sources and drains have a common potential. Therefore, the drain currents Idp14 and Idp15 of the both transistors Qp14 and Qp15 are equal to each other and form a current mirror. The gate potential of the MOS transistor Qn13 is the external power supply voltage described above.
The reference potential 12 is less dependent on Vcc15, while the gate potential of the MOS transistor Qn14 is the internal voltage 11 for operating the internal elements. This internal voltage 11 is set to a voltage value at least within the operating voltage of the DRAM. Then, by comparing the reference voltage 12 and the internal voltage 11, the potential of the contact 121, that is, the gate potential of the MOS transistor Qp16 is changed, and a circuit system for controlling the output current from the output circuit unit 6 is adopted.

The operation of the supplier 4 will be described in comparison with the case where the reference voltage 12 and the internal voltage 11 are equal. First, the internal voltage 11 (gate potential of the MOS transistor Qn14) is the reference voltage 1
When it is lower than 2 (gate potential of the MOS transistor Qn13), the drain current Idn14 of the MOS transistor Qn14 decreases, so the drain potential of the MOS transistor Qp15 and the potential of the contact 122 (that is, the gate potentials of the MOS transistors Qp14, Qp15). ) Rises. Therefore, the MOS transistor Qp14
Between the gate and source of the
Since p14 decreases, the drain potentials of the MOS transistors Qp14 and Qn13, that is, the potential of the contact 121 drops. As a result, the gate potential of the MOS transistor Qp16, which is the potential of the contact 121, drops,
The source-to-source voltage increases, and the drain current Idn16 increases.

On the other hand, when the internal voltage 11 is higher than the reference voltage 12, the drain current Idn14 of the MOS transistor Qn14 increases conversely to the above, and the potential of the contact 122 drops, so that the MO
The gate-source voltage of the S transistor Qp14 increases,
Its drain current Idp14 increases. Therefore, contact 121
Since the potential of the MOS transistor Qp16 rises, the gate-source voltage of the MOS transistor Qp16 decreases and its drain current Idn16 decreases. In particular, when the internal voltage 11 reaches the preset voltage, the potential of the contact 121 is changed to the MOS transistor Qp16.
Is raised until it is turned off, and the rise exceeding the set voltage is blocked, so that the internal voltage 11 can be maintained at the set voltage.

Here, the feeder 4 is the external power supply voltage Vcc1 as described above.
Since the internal voltage 11 is generated in comparison with the reference voltage 12 having a small dependency of 5, the internal voltage 11 is changed to the external power supply voltage Vcc1.
It is possible to maintain a predetermined set voltage that is less dependent on the fluctuation of 5.

Then, the internal element is operated by the internal voltage 11 internally stepped down by the supplier 4 of the internal step-down device 2, and
HIGH is written in the memory cell 7 with this internal voltage 11. This is because after the advent of 16M DRAM, the size of internal elements of semiconductor devices has decreased, and the external power supply voltage has become too high to ensure the reliability of internal element withstand voltage, or to reduce power consumption. This is because it may not be possible to achieve high speed, and from the viewpoint of speed, it is desirable to adopt a method in which the external power supply voltage is reduced and the internal voltage is used.

Further, in FIG. 1, 8 is a substrate potential generator that generates a substrate potential 14, and 9 is a substrate potential detector that detects whether the substrate potential 14 generated by the substrate potential generator 8 is above or below a set potential. Is.

The substrate potential detector 9 is a p-type MOS transistor Qp1.
7 and an n-type MOS transistor Qn16, and an n-type MOS transistor Qn17 whose gate and drain are short-circuited are connected in series, and both gates of the transistors Qp17 and Qn16 are connected to the ground potential Vss16. Together with the transistor Qp1
The source potential of 7 is an internal voltage 11 having a small dependence on the external power supply voltage Vcc15 from the output circuit section 6 of the supplier 4, and the source potential of the transistor Qn17 is a substrate potential 14. The source potential of the MOS transistor Qn16 is output to the substrate potential generator 8 as the substrate potential detection signal 13, and the substrate potential generator 8 is controlled by the substrate potential detection signal 13.

The operation of the substrate potential detector 9 will be described. First, as described above, in the MOS transistor Qp17, the gate potential is the ground potential Vss16, the source potential is the internal voltage 11, and the gate-source voltage is a constant voltage lower than the threshold voltage. , Drain current I that is almost constant value independent of external power supply voltage Vcc15
dp17 is flowing.

Now, assuming that the substrate potential 14 is lowered below the set potential lower than the ground potential Vss16, the transistor Qn17 turns on.
As soon as this state is turned on, the potential of the contact 131 (that is, the source potential of the MOS transistor Qn16) is changed to this MOS by this on state.
Since it can be pulled down by a voltage higher than the threshold voltage of the transistor Qn16, this transistor Qn16 is also turned on.
State. As a result, the drain potentials of the MOS transistors Qp17 and Qn16, that is, the substrate potential detection signal 13 becomes a potential low enough to stop the operation of the substrate potential generator 8 due to the on state of the three transistors. Where MO
Since the drain current of each of the S transistors Qp17, Qn16, Qn17 is a substantially constant value without depending on the external power supply voltage Vcc15, the substrate potential detection signal 13 has a small dependence on the fluctuation of the external power supply voltage Vcc15. Become.

On the other hand, when the substrate potential 14 rises to a potential higher than the above set potential, the MOS transistor Qn17 reduces the potential of the contact 131 to a small extent, so that the gate-source voltage of the MOS transistor Qn16 is reduced to that threshold. Since it remains at a voltage lower than or slightly higher than the voltage, the MOS transistor Qn16 can only pass an off state or a minute current. Therefore, the substrate potential detection signal 13, which is the drain potential of the MOS transistors Qp17 and Qn16, is used to operate the substrate potential generator 1 with the drain current Idp47 having a substantially constant value (independent of the external power supply voltage Vcc15 of the MOS transistor Qp17). It has a sufficiently high constant potential.

From the above description, the substrate potential detector 9 is the internal voltage down converter 2
Based on the internal voltage 11 having a small dependency on the external power supply voltage Vcc15 and the actual substrate potential 14 generated from the supplier 4, the actual substrate potential 14 is less than the set potential regardless of the fluctuation of the external power supply voltage Vcc15. In this case, the substrate potential detection signal of the low potential is always output, and when the actual substrate potential 14 is equal to or more than the set potential, the substrate potential detection signal of the high potential is always output to generate the substrate potential generated by the substrate potential generator 8. 14
It is detected whether or not is a set potential. With this configuration, the operation of the substrate potential generator 8 can be controlled with a small dependency on the external power supply voltage Vcc15.

Therefore, the external power supply voltage Vcc1 for the operation of the substrate potential generator 8 is
Since the dependence on 5 can be made small, the substrate potential 14 generated by the substrate potential generator 8 is set to the external power supply voltage.
The set potential can be maintained regardless of the fluctuation of Vcc15.

Example 2 Next, a second example of the present invention will be described. In the block circuit diagram of the semiconductor device shown in FIG. 2, Qp20 to Qp29 are P-type MOS transistors, Qn20 to Qn29 are N-type MOS transistors, 25 is a power supply potential Vcc, 26 is a ground potential Vss, and 27 is an internal voltage a. , 21 is an internal voltage b, 22 is a reference voltage, 23 is a substrate potential detection signal, and 24 is a substrate potential. Also, 211, 212, 221,
222 and 241 are contact points.

The internal step-down device 2'of FIG. 2 comprises a reference voltage generator 3'and a supply device 4 '. First, the operation of the reference voltage generator 3'is as described in the first embodiment. That is, the reference voltage generator 3'includes the transistors Qp21 and Qn2.
1, and the transistors Qp22 and Qn22 are connected in series, respectively, and are in parallel with each other with respect to the external power supply voltage Vcc25. Furthermore, the diode of the transistor Qp23 is connected between the source and drain of the transistor Qp22.

Therefore, since the reference voltage generator 3'has a feedback circuit having the same structure as the reference voltage generator 3 of the first embodiment, the contact point 211 outputs a voltage lower than the external power supply voltage Vcc25 by a predetermined potential. The contact 212 outputs the reference voltage 22 which is higher than the ground potential Vss26 by a predetermined potential.

In the semiconductor device of this embodiment, the contact 212 is used as the reference voltage.
Potential that is higher than the ground potential Vss26 by a predetermined potential and less dependent on the external power supply potential Vcc25 is used.

The operation of the feeder 4'is also as described in the first embodiment. That is, the feeder 4'includes two p-type MOS transistors Qp24, Qp25 and three n-type MOS transistors Qn23.
~ Qn25 and a differential amplifier 5 ', and one p
Type output MOS transistor Qp26 composed of output circuit 6 '
And consists of

Two MOS transistors Qp24, Qp of the differential amplifier 5 '.
25 has a configuration in which the source and drain have a common potential, so both transistors Qp24, Q
The drain currents Idp24 and Idp25 of p25 are equal to each other and form a current mirror. Further, the gate potential of the MOS transistor Qn23 is the reference potential 22 which is less dependent on the external power supply voltage Vcc25 described above, while the MOS transistor Qn2 is
The gate potential of 4 is the internal voltage 27. Then, by comparing the reference voltage 22 and the internal voltage 27, the potential of the contact 221 which is the gate potential of the MOS transistor Qp26 is changed, and the circuit method is for controlling the output current from the output circuit section 6 '. .

Therefore, since the feeder 4'has a feedback circuit having the same structure as the feeder 4 of the first embodiment, as described in the first embodiment, the gate potential of the MOS transistor Qn24 (internal voltage 27 ) Is lower than the gate potential of the MOS transistor Qn23 (reference potential 22), the drain current Idn26 of the MOS transistor Qp26 increases, while conversely, when the internal voltage 27 is higher than the reference voltage 22, The drain current Idn26 of the transistor Qp26 decreases. Especially,
When the internal voltage 27 reaches the preset voltage,
The potential of the contact 221 (the drain potentials of the MOS transistors Qp24 and Qn23) rises until the MOS transistor Qp26 is turned off, and the rise exceeding the set voltage is prevented, so that the internal voltage 27 can be maintained at the set voltage.

Since the supplier 4'generates the internal voltage 27 based on the reference voltage 22 having a small dependency on the external power supply voltage Vcc25, the internal voltage 27 has a small dependency on the external power supply voltage Vcc25. It can be maintained at a predetermined set voltage.

Further, the other feeder 4 ″ shown in FIG. 2 has two p-type MOS transistors Qp28 and Qp29, like the above-mentioned feeder 4 ′.
And a differential amplifier 5 "composed of three n-type MOS transistors Qn20, Qn28 and Qn29 and an output circuit section 6" composed of one p-type MOS transistor Qp20.

Two MOS transistors Qp28, Qp of the differential amplifier 5 "
Since 29 has a configuration in which the source and the drain have a common potential, the drain currents Idp28, Id28
p29 is equally a current mirror. The gate potential of the MOS transistor Qn28 is the external power supply voltage described above.
While the reference voltage 22 has less dependence on Vcc25, M
The gate potential of the OS transistor Qn29 is the internal voltage 21 (output voltage to the substrate potential detector 9 '). Then, by comparing the reference voltage 22 with the internal voltage 21, the potential of the contact 241 which is the gate potential of the MOS transistor Qp20 is changed, and a circuit system for controlling the output current from the output circuit section 6 ″ is adopted. .

Therefore, since the feeder 4 ″ is a feedback circuit having the same configuration as the feeder 4 ′, the gate potential (internal voltage 21) of the MOS transistor Qn29 is higher than the gate potential (reference voltage 22) of the MOS transistor Qn28. When the internal voltage 21 is higher than the reference voltage 22, the drain current Idp20 of the MOS transistor Qp20 increases when
The drain current Idp20 of the MOS transistor Qp20 decreases.
In particular, when the internal voltage 21 reaches a preset setting voltage, the potential of the contact 241 rises until the MOS transistor Qp20 is turned off and prevents the rise above the preset voltage. The output potential to the device 9 ') can be maintained at the set voltage.

Therefore, since the internal voltage 21 is generated based on the reference voltage 22 having a small dependency on the external power supply voltage Vcc25, this internal voltage 21 (output voltage to the substrate potential detector 9 ') is dependent on the external power supply voltage Vcc25. It can be a small voltage.

Then, the internal element is operated by the internal voltage 27 generated by the above-mentioned first supplier 4 ', and HIGH is written in the memory cell 7.

In addition, the structure of the substrate potential detector 9'of FIG. 2 is similar to that of the substrate potential detector 9 of the first embodiment. That is, the substrate potential detector 9'includes a p-type MOS transistor Qp27, an n-type MOS transistor Qn26, a gate,
3 with n-type MOS transistor Qn27 with shorted drain
The transistors Qp27 and Qn26 have both gates connected to the ground potential Vss26, and the source potential of the transistor Qp27 is the internal potential 21 generated from the supplier 4 ″. The source potential of the MOS transistor Qn2 is the substrate potential 24.
The source potential of 6 is output to the substrate potential generator 8 as a substrate potential detection signal 23, and the substrate potential generator 8 is controlled by the substrate potential detection signal 23.

Therefore, since the substrate potential detector 9'has the same circuit configuration as that of the first embodiment, as described above, when the substrate potential 24 is lowered below the set potential lower than the ground potential Vss26, the three potentials are reduced. All the transistors are on,
The drain current of each of them is almost constant without depending on the external power supply voltage Vcc25.
23 (that is, the drain potentials of the MOS transistors Qp27 and Qn26) is a signal having a small dependency on the external power supply voltage Vcc25. On the other hand, when the substrate potential 24 rises to a potential higher than the set potential, the substrate potential detection signal 23 becomes a high potential of a substantially constant value that does not depend on the external power supply voltage Vcc25. Therefore, the substrate potential detector 9 ′ is connected to the external power supply voltage Vcc2.
The substrate potential detection signal 23 having a voltage irrelevant to the fluctuation of 5 is output.

From the above description, in addition to the HIGH write internal voltage 27 generated from the supply device 4 ′, another internal supply voltage 21 having a small dependency of the external power supply voltage Vcc25 is generated by the other supply device 4 ″. Based on the above, the substrate potential detector 9'outputs a substrate potential detection signal which is hardly influenced by the variation of the external power supply voltage Vcc25 to control the substrate potential generator 8. Therefore, the substrate potential 24 is changed to the variation of the external power supply voltage Vcc25. Can be maintained at the set voltage almost regardless of.
During reading and writing, even if the internal voltage 27 of the feeder 4'changes when operating the internal elements, the internal voltage 21 output to the substrate potential detector 9'does not change, so the substrate potential is detected. The substrate potential can be reliably maintained at the set potential without fluctuation of the signal.

(Embodiment 3) Next, an embodiment of the invention described in claim (4) will be described with reference to FIG. In this embodiment, the reference voltage generator itself is used as an internal voltage generator without providing the feeders 4 and 4'in the internal step-down devices 2 and 2'of the first and second embodiments.
The generated reference voltage is used as it is as an internal voltage having a small dependency on the external power supply voltage.

That is, in the block circuit of the semiconductor device shown in the figure, Qp31 to Qp35 and Qp37 are P-type MOS transistors, Qn3.
1, Qn36 and Qn37 are N-type MOS transistors, 35 is an external power supply potential Vcc, 36 is a ground potential Vss, 31 is an internal voltage, 33 is a substrate potential detection signal, 34 is a substrate potential, and 311 is a contact.

The internal voltage generator 3 ″ shown in FIG. 1 includes first and second MOS transistors Qp35 and Qp31 whose gate and drain are short-circuited,
The third MOS transistor Qn31 is connected in series
And a fourth MOS transistor Qp32 and a fifth MOS in which the gate and the drain are short-circuited with each other.
The transistor Qp34 is connected in series to form a second series body. The first and second series bodies are connected in parallel with each other between the external power supply voltage Vcc35 and the ground potential Vss36.

Further, the gate of the second MOS transistor Qp31 is short-circuited and connected to the gate of the fourth MOS transistor Qp32, and the gate of the third MOS transistor Qn31 is short-circuited to the drain of the fourth MOS transistor Qp32. Connected. In addition, the fourth MOS transistor Qp3
A sixth MOS transistor Qp33, whose gate and drain are short-circuited, is connected between the source and drain of 2.
The connection position of the sixth MOS transistor Qp33 is the fourth M
The source / drain of the OS transistor QP32 may be replaced with the source / drain of the third MOS transistor Qn31.

All the six transistors are operated in the saturation region.

The reference voltage generator 3 ″ is similar to the reference voltage generators 3 and 3 ′ of the first and second embodiments so that the dependency of the internal voltage 31 on the potential pressure external power supply potential Vcc35 is reduced. The configuration will be specifically described below: If the internal voltage 31 is substantially constant, the transistor Qn31 is formed.
Operates in the saturation region because its gate potential is a constant potential at the above-mentioned internal voltage 31, and its source potential is ground potential.
Since it is Vss36 and the voltage between the gate and the source is almost constant, its drain current Idn31 is almost constant. In addition, the drain currents Idp31, of both transistors Qp31 and Qn31,
The drain potential and the gate potential of the transistor Qp31 when Idn31 is the same are the potential of the contact 311 in the steady state. Therefore, the drain current Idp31 of the transistor Qp31 in the steady state is almost constant. On the other hand, the drain current Idp31 of the transistor Qp31 is almost determined by the gate-source voltage due to the operation in the saturation region. Therefore, if the drain current Idp31 is almost constant as described above, the gate-source The voltage between them is almost constant. From the above, the potential difference between the potential of the contact 311 which is the gate-source voltage of the transistor Qp31 and the external power supply voltage Vcc35 is substantially constant.

Further, the potential difference between the gate-source voltage of the transistor Qp32, which is the potential of the contact 311 and the external power supply voltage Vcc35, is substantially constant as described above, and therefore the drain current Idp32 of the transistor Qp32 is in the saturation region. It is almost constant by the operation in. In addition, transistors Qp32 and Qp34
The source potential of the transistor Qp34 when both drain currents Idp32 and Idp34 are equal to each other is the internal voltage 31 in the steady state. Therefore, the transistor Qp in the steady state
The drain current Idp34 of 34 is almost constant. On the other hand, since the drain current Idp34 of the transistor Qp34 is almost determined by the gate-source voltage due to the operation in the saturation region, if the drain current Idp34 is substantially constant as described above, the gate-source The voltage between them is almost constant. From the above, the potential difference between the internal voltage 31 which is the gate-source voltage of the transistor Qp34 and the ground potential Vss36 is substantially constant.

As described above, since the reference voltage generator 3 ″ is the feedback circuit having the above-mentioned configuration, the potential of the contact 311 becomes a constant voltage lower than the external power supply voltage Vcc35 by a predetermined potential and the internal potential 31 It can be seen that is a constant voltage higher than the ground potential Vss36 by a predetermined potential.

Therefore, the internal voltage 31 used in the semiconductor device of this embodiment is
Is a voltage that is higher than the ground potential Vss36 by a certain potential and that is less dependent on the external power supply potential Vcc35.

The configuration of the substrate potential detector 9 ″ in FIG. 3 is similar to that of the substrate potential detector 9 of the first embodiment described above.
The substrate potential detector 9 ″ is a p-type MOS transistor Qp37.
And an n-type MOS transistor Qn36 and an n-type MOS transistor Qn37 whose gate and drain are short-circuited are connected in series. Both gates of the transistors Qp37 and Qn36 are connected to the ground potential Vss36. , Transistor Qp3
The source potential of 7 is the internal voltage 31 generated by the reference voltage generator 3 ″, and the source potential of the transistor Qn37 is the substrate potential 34. Also, the MOS transistor Qn3.
The source potential of 6 is output to the substrate potential generator 8 as the substrate potential detection signal 33, and the substrate potential generator 8 is controlled by the substrate potential detection signal 33.

Therefore, since the substrate potential detector 9 ″ of this embodiment has the same circuit configuration as that of the first embodiment, as already described, when the substrate potential 34 is lowered below the set potential lower than the ground potential Vss36. All three transistors
In the on state, the drain current of each of them is almost constant without depending on the external power supply voltage Vcc35. Therefore, the substrate potential detection signal 33 (that is, the drain potentials of the MOS transistors Qp37 and Qn36) is the external power supply voltage Vcc35. The signal has a small dependence on. On the other hand, when the substrate potential 34 rises to a potential higher than the set potential, the substrate potential detection signal 33
Is a high potential of a substantially constant value that does not depend on the external power supply voltage Vcc35. Therefore, the substrate potential detector 9 ″ outputs the substrate potential detection signal 33 irrelevant to the fluctuation of the external power supply voltage Vcc35. From the above description, the substrate potential detector 9 ″ depends on the external power supply voltage Vcc35. Based on the internal voltage 31 and the actual substrate potential 34, which have a small property, even if the external power supply voltage Vcc35 changes, the substrate potential detection signal of the low potential is always output when the actual substrate potential 34 is less than the set potential, On the contrary, when the actual substrate potential 34 is equal to or higher than the set potential, the high substrate potential detection signal is always output. Therefore, the external power supply voltage Vc
It is possible to control the operation of the substrate potential generator 8 with little dependence on the fluctuation of c35.

Therefore, the operation of the substrate potential generator 8 is controlled by the external power supply voltage Vcc3.
The substrate potential 34 generated by the substrate potential generator 8 can be reduced to the external power supply voltage Vcc3 because the dependency of 5 can be reduced.
The set potential can be maintained regardless of the fluctuation of 5. Moreover, since the current consumption by the feeders 4, 4 ″ of the first and second embodiments is not generated, there is an advantage that the power consumption is not increased.

The present invention has been described above based on the respective embodiments, but it is obvious that the present invention is not limited to the respective embodiments and various modifications can be made.

(Effects of the Invention) As described above, according to the semiconductor device of the present invention,
Even if the external power supply voltage fluctuates, by generating an internal voltage with little dependency on the external power supply voltage and detecting whether the actual substrate potential is above or below the set potential based on this internal voltage, Since the operation of the substrate potential generator can be controlled without being greatly affected by the voltage fluctuation, the substrate potential can be held at the set potential regardless of the fluctuation of the external power supply voltage.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a circuit block diagram of a semiconductor device showing a second embodiment, and FIG. 3 is a third embodiment. FIG. 4 is a circuit block diagram of a semiconductor device, and FIG. 4 is an electric circuit diagram showing a conventional substrate potential detector. Qp11, Qp12 ... p-type MOS transistor, Qn11, Qn12 ... n
Type MOS transistor, 2,2 '... Internal step-down converter, 3,3', 3 "
...... Reference voltage generator, 4,4 ′, 4 ″ …… Supplier, 5,5 ′, 5 ″
...... Differential amplifier, 6,6 ′, 6 ″ …… Output circuit part, 8 …… Board potential generator, 9,9 ′, 9 ″ …… Board potential detector, 11,21,3
1 …… Internal potential, 13,23,33 …… Substrate potential detection signal, 14,2
4,34 …… Board potential, 16,26,36 …… Ground potential.

Claims (4)

(57) [Claims] 1. A substrate potential generator for generating a substrate potential, an internal voltage generator for generating an internal voltage having less dependence of an external power supply voltage within at least an operating voltage of a DRAM, and an internal voltage generator for generating the internal voltage. A substrate potential detector that detects whether the substrate potential generated by the substrate potential generator is above or below a set potential based on the internal voltage and the actual substrate potential, and the substrate potential generator is the substrate A semiconductor device characterized by being controlled by the output of a potential detector. 2. The semiconductor device according to claim 1, wherein the internal voltage generator is an internal voltage down converter used for generating an internal element operating voltage. 3. The internal voltage down converter comprises a reference voltage generator and a supply device for generating an internal voltage based on the reference voltage generated by the reference voltage generator. Semiconductor device. 4. An internal voltage generator comprises: a first series body composed of a series connection of first and second MOS transistors having a gate and a drain short-circuited and a third MOS transistor; and a fourth MOS transistor. And a second series body including a fifth MOS transistor in which a gate and a drain are short-circuited and connected in series between a power supply voltage and a ground potential, and a gate of the second MOS transistor and the second MOS transistor. Short-circuiting between the gate of the fourth MOS transistor and the gate of the third MOS transistor and the drain of the fourth MOS transistor, and the third MOS transistor or the fourth MOS The semiconductor device according to claim 1, wherein a sixth MOS transistor having a gate and a drain short-circuited is connected between the source and the drain of the transistor.