JPH02270334A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the short channel phenomenon and the penetration of a wiring from occurring neither increasing the processes as little as possible nor making the alignment allowance at all by a method wherein the second deep diffused layer formed by leading-in the second impurity through a contact hole is provided by overlapping with the first shallow diffused layer formed by leading-in the first impurity. CONSTITUTION:The title semiconductor integrated circuit device is provided with a gate electrode 34 formed on the first conductivity type semiconductor substrate 31, the first shallow diffused layer 35 to be a source or drain formed by leading the second conductivity type first impurity into the substrate 31 through the intermediary of the first thin insulating film formed on the gate electrode 34 and the gate electrode 34 itself whereon the insulating film is formed, the second insulating film 36 having an impurity and formed so as to make a contact hole on the part to be the source or the drain, the second deep diffused layer 39 to be another source or drain formed by leading the second conductivity type second impurity into the substrate 31 so as to be laminated on the first diffused layer 35 deeper than the layer 35 through the intermediary of the said contact hole as well as a metallic wiring 37 formed so as to be connected to the source or drain through the intermediary of the said contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a source in a semiconductor integrated circuit device in which a MOB field effect transistor is used as a VS component.

Regarding the drain diffusion layer.

In the technological development of semiconductor integrated circuit devices that use MOB field effect transistors as constituent elements, the most focused efforts are toward high integration and miniaturization. The biggest bottleneck in the process of miniaturization is channel length. Currently, prototype transistors or integrated circuits with a channel length of around 1μ have been manufactured, but at the FFI production stage, integrated circuit devices with a channel length of around 5μ have only been manufactured, which is unprecedented. Which integrated circuit device is 5μ
Manufactured with channel lengths of approximately

As the channel length is shortened, short channel development (poor withstand voltage between the source and drain and decrease in threshold voltage) occurs, leading to defects, but the following are the main countermeasures (1). ) Reduce the gate film thickness.

(2) Increase the concentration of the substrate.

(3) Shallow the diffusion depth sej of the source and drain.

Among these methods, the diffusion method using ion implantation is generally used to reduce the diffusion depth xj of the source and drain, and furthermore, as a diffusion source, a material with a small diffusion coefficient such as As or Sb is used, or a diffusion source such as B or P is used. However, this can be countered by reducing the impact energy and the amount of impact.

If xj is made shallower or the implantation amount is reduced, the penetration of the metal diffusion layer at the connection portion will still occur (poor junction breakdown voltage). An example of this is shown in FIG. 1, and examples of conventional countermeasures are shown in FIGS. 2 and 3.

As shown in FIG. 1, a field oxide film 2. Gay) M, membrane 3. Gate Chikoku 4. M+
Diffusion layer 5, P9G film 6. FIG. 2 is a schematic cross-sectional view of the vicinity of the drain of an N-channel uos% field effect transistor formed with an At wiring of 7°. A of the contact part as shown in the figure.
An alloy pit 8 protruding around the contact hole is generated at the part A4A between T and At enters to the tip of the alloy pit 8. From there, At is diffused into the 81 single crystal. If the N+ diffusion layer 5 is shallow, the distance from the tip of the alloy pit 8 or the tip where the particles are diffused to the bottom of the N+ diffusion layer 5 is short, causing a breakdown voltage failure. The main countermeasures are to form the N1 expansion 19 deep in advance so as to match the contact area, as shown in Figure 2, and to form the At wiring as shown in Figure 3. A barrier, such as a platinum layer 30, is provided underneath to prevent penetration. However, if a deep diffusion layer is formed in advance as shown in FIG. 2, there is a drawback that an allowance must be made for mask misalignment and that steps such as photo-etching and diffusion steps must be increased.

Further, when a barrier layer is formed as shown in FIG. 3, poor adhesion between the barrier layer and the 81 single crystal substrate, PSG, etc. tends to occur, and the number of steps such as vapor deposition and etching of the barrier layer is increased. Moreover, breakthrough is not completely preventable.

Further, penetration is prevented by mixing 31, O, etc. into At, but this is not perfect when the diffusion becomes shallow as Q, 2 to α5μ.

The present invention is an improvement in consideration of the above-mentioned drawbacks, and aims to prevent punch-through without increasing the number of steps as much as possible and without taking any margin for positioning.

The present invention will be explained below with reference to FIGS. 4 to 7 showing schematic cross-sectional views showing the mounting process.

As shown in FIG. 4, a field acid, yJX52, is formed by selective oxidation on a P-sheared single crystal 81 substrate 31, and a gate oxide film 33 is formed on the portion where the field oxide film is not formed. A gate electrode 34 is formed, a thin oxide film is formed on it, and A with a small diffusion coefficient is formed on top of it.
@N+ diffusion layer 35 that becomes a drain by ion implantation
Form shallowly. As shown in Figure 5, PSG
, [36] to form a contact hole.

As shown in FIG. 6, the reaction between POO2 and 0° causes P, 0. Detub, P thermally diffuse 1 diffusion layer 3
form 9. At this time, due to the difference in diffusion coefficients between P and As, it is possible to deepen the diffusion layer 39 made of P without deepening xj of the diffusion layer 35 made of As.

In this case, the predetermined xj can be obtained only by the N+ predeposition process, or the predetermined sej can be obtained by performing N annealing after the N+ predeposition process. Also, by combining N+ pre-devo and PSG film glue flow, the shape of the step part can be changed without increasing the process.
The shape of the contact part can be improved.

Further, as shown in FIG. 7, after light etching, a layer is deposited and photoetched to form the wiring 37.

As described above, according to the method of the present invention, it was possible to create a structure that prevents penetration by deepening the diffusion only in the contact area without increasing the number of processes and without taking any extra margin for alignment. . 'In the present invention, P and As are shown, but the same effect can be achieved even if other elements are used, and the same effect can be obtained even if three or more types of elements are used.

Furthermore, in the example of the present invention, an N-channel MOB integrated circuit is shown, but a P-channel MO9 integrated circuit, a complementary MOF
The same applies to the 9 integrated circuits.

Incidentally, in the example of the present invention, a manufacturing method in which deep diffusion is formed later is shown, but the same applies even if the order is changed.

[Brief explanation of drawings]

Figures 1 to 3 show N-channel MOI in the conventional method.
9 [Figures 4 to 7 which are schematic cross-sectional views of field effect transistors]
The figure is a schematic cross-sectional view showing the manufacturing process of an N-channel MOSg field effect transistor according to the method of the present invention. The details are as follows. 1.11, 21.31... P-o single crystal 81 substrate 2.12, 22.32... Field oxide film 3
．． 13,23.33...Gate oxide film 4.14
,24,34...Gate I! ! pole 5.15,1
9, 25, 55.35'...N+ diffusion layer 6.16, 26.56...PSG film 7.17,
27.37...At wiring 9.18.38...
・・・・・・・・・・・・Alloy bit 30・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
Platinum layer Figure 6

Claims (1)

[Claims] In a semiconductor integrated circuit device having a MOS field effect transistor using a Si single crystal substrate as a component, at least a part of the source and drain diffusion layers exhibits the same conductivity type, and A semiconductor integrated circuit device whose constituent elements are MOS field effect transistors formed by overlapping and diffusing different atoms having different diffusion coefficients.