JPH02265262A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH02265262A JPH02265262A JP8750289A JP8750289A JPH02265262A JP H02265262 A JPH02265262 A JP H02265262A JP 8750289 A JP8750289 A JP 8750289A JP 8750289 A JP8750289 A JP 8750289A JP H02265262 A JPH02265262 A JP H02265262A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- interlayer insulating
- insulating film
- forming
- wiring part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000011368 organic material Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 abstract description 26
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000004642 Polyimide Substances 0.000 description 18
- 229920001721 polyimide Polymers 0.000 description 18
- 238000007747 plating Methods 0.000 description 8
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の製造方法に関し、特に多層配
線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for forming multilayer wiring.
従来、有機樹脂材料を層間絶縁膜として用いる多層配線
の形成方法においては、第３ＵＡに示すように、半導体
基板１上に下層配線１６を形成したのち、有機樹脂Ｊ？
Ｗ １５を形成して層間絶縁膜としていた。Conventionally, in a method for forming multilayer wiring using an organic resin material as an interlayer insulating film, as shown in the third UA, after forming the lower layer wiring 16 on the semiconductor substrate 1, organic resin J?
W15 was formed as an interlayer insulating film.
上述した従来の多層配線の形成方法においては、下層配
線１６を形成したのちに有機樹脂層１５を形成するため
、下層配線１６の段差によっては層間絶縁膜を完全に平
坦化できないため、上層配線のカバレッジが悪くなると
いう欠点がある。さらに下層配線１６の間隔がせまく、
特に配線の厚さよりも間隔がせまいような場合は、配線
形成後に有機樹脂を塗布したときに、有機樹脂配線間に
はいりこみにくいため、空洞１７が発生するという欠点
がある。In the conventional multilayer wiring formation method described above, since the organic resin layer 15 is formed after the lower layer wiring 16 is formed, the interlayer insulating film cannot be completely flattened depending on the level difference of the lower layer wiring 16. This has the disadvantage of poor coverage. Furthermore, the spacing between the lower layer wiring 16 is narrower,
Particularly when the spacing is narrower than the thickness of the wiring, when the organic resin is applied after the wiring is formed, it is difficult to get between the organic resin wirings, resulting in the formation of cavities 17.
本発明の半導体集積回路の製造方法は、半導体基板上に
有機材料からなる第１の層間絶縁膜を形成したのち半導
体基板に達する配線形成用の溝を形成する工程と、前記
溝の内部に第１の配線を形成する工程と、前記第１の配
線表面を含む全面に有機材料からなる第２の層間絶縁膜
を形成する工程と、前記第２の層間絶縁膜に配線接続用
の開口部を形成し第１の配線の表面を露出させる工程と
、前記開口部を介して第１の配線に接続する第２の配線
を形成する工程とを含んで構成される。The method for manufacturing a semiconductor integrated circuit of the present invention includes the steps of: forming a first interlayer insulating film made of an organic material on a semiconductor substrate, and then forming a trench for forming wiring that reaches the semiconductor substrate; forming a second interlayer insulating film made of an organic material on the entire surface including the first wiring surface; and forming an opening for wiring connection in the second interlayer insulating film. The method includes a step of forming and exposing the surface of the first wire, and a step of forming a second wire connected to the first wire through the opening.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｈ）は本発明の第１の実施例を説明す
るための半導体チップの断面図である。FIGS. 1(a) to 1(h) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.
まず第１図（ａ＞に示すように、半導体基板１上に有機
樹脂としてポリイミド前駆体材料を塗布し、熱処理して
ポリイミド化し、厚さ３μｍの第１ポリイミド層２を形
成する。First, as shown in FIG. 1(a), a polyimide precursor material is applied as an organic resin onto a semiconductor substrate 1, and heat-treated to form a polyimide, thereby forming a first polyimide layer 2 having a thickness of 3 μm.
次に第１図（ｂ）に示すように、全面に０．５μｍ厚の
窒化膜３をプラズマＣＶＤ法により形成したのち、この
窒化ｙ４１Ａ３をフォトリソグラフィーとＣＦ４ガスを
用いたりアクティブイオンエツチング法によりパターニ
ングする。次でこの窒化膜３をマスクにし、酸素ガスを
用いたりアクティブイオンエツチング法により第１ポリ
イミド層２に深さ３μｍ、幅１．０μｍの溝１１を形成
する。Next, as shown in FIG. 1(b), a nitride film 3 with a thickness of 0.5 μm is formed on the entire surface by plasma CVD, and then this nitride film 3 is patterned by photolithography, CF4 gas, or active ion etching. do. Next, using this nitride film 3 as a mask, a groove 11 having a depth of 3 μm and a width of 1.0 μm is formed in the first polyimide layer 2 by using oxygen gas or active ion etching.
次に第１図（Ｃ）に示すように、窒化Ｍ３を除去したの
ちスパッタリング法を用いて０．０５μｍ厚の金からな
るメツキ用電極４を形成する。Next, as shown in FIG. 1C, after removing the nitride M3, a plating electrode 4 made of gold with a thickness of 0.05 μm is formed using a sputtering method.
次に第１図（ｄ）に示すように、全面にフォトレジスト
膜５を形成したのちパターニングし、溝１１部のメツキ
用電極４を露出させる。この際上層配線と接続をはかる
部分はスルーホールの広ろがりや目ずれを考慮し、溝１
１の幅より広いスルーホールを形成しておく。Next, as shown in FIG. 1(d), a photoresist film 5 is formed on the entire surface and then patterned to expose the plating electrode 4 in the groove 11 portion. At this time, the part where the connection with the upper layer wiring is made takes into account the width of the through hole and the misalignment of the groove.
A through hole wider than 1 is formed in advance.
次に第１図（ｅ）に示すように、フォトレジスト膜５を
マスクにして電解金メツキを行ない、厚さ３．５μｍの
第１の配線６を形成する。この第１の配線は、第１ポリ
イミド層２から約０．５μｍとびだした形状で形成する
のが望ましい。Next, as shown in FIG. 1(e), electrolytic gold plating is performed using the photoresist film 5 as a mask to form a first wiring 6 having a thickness of 3.5 μm. This first wiring is preferably formed in a shape protruding from the first polyimide layer 2 by about 0.5 μm.
次に第１ （：４ （ｆ ）に示すように、フォトレジ
スト膜５を！ＩＩ ｆａした後、イオンミリングにより
全面をエツチングし、第１の配線部以外の不要なメツキ
用電極４を除去したのち、第２ポリイミド層７を１μｍ
厚に形成する。第１の配線６による０、５μｍ程度の段
差は充分に千用化することができる。Next, as shown in the first (:4(f)), after the photoresist film 5 was subjected to !II fa, the entire surface was etched by ion milling to remove unnecessary plating electrodes 4 other than the first wiring part. Afterwards, the second polyimide layer 7 is formed to a thickness of 1 μm.
Form thickly. The level difference of about 0.5 μm caused by the first wiring 6 can be sufficiently increased.
次に第１Ｅ′￥ｌ（ｇ）に示すように、フォトレジスト
膜をマスクとしてこの第２ポリイミド屑７をパターニン
グし、第１の配線６を露出するスルーホール８を形成す
る。ポリイミド層のエツチング液としてヒドラジンを含
むウェットエツチング液を用いる。Next, as shown in 1E'\(g), the second polyimide scrap 7 is patterned using the photoresist film as a mask to form a through hole 8 exposing the first wiring 6. A wet etching solution containing hydrazine is used as an etching solution for the polyimide layer.
次に第１図（ｈ）に示すように、第１の配線６の形成工
程と同様に操作し、第２の配線用のメツキ用電極４Ａを
形成し、電解金メツキ法により第１の配線６に接続する
１μｍ厚の第２の配線１０を形成する。Next, as shown in FIG. 1(h), the plating electrode 4A for the second wiring is formed by the same operation as in the formation process of the first wiring 6, and the first wiring is formed by electrolytic gold plating. A second wiring 10 having a thickness of 1 μm is formed to be connected to the second wiring 6 .
このように第１の実施例によれば、層間絶縁膜の湧の中
に配線を形成するため、従来例に比較し、平坦でカバレ
ッジのよい多層配線を形成することができる。さらに配
線の厚さよりも配線間隔がせまい場合でも、層間絶縁膜
としてのポリイミド層に空洞が出来ることはなくなる。As described above, according to the first embodiment, since the wiring is formed in the groove of the interlayer insulating film, it is possible to form a multilayer wiring which is flat and has good coverage compared to the conventional example. Furthermore, even if the wiring interval is smaller than the wiring thickness, cavities will not be formed in the polyimide layer serving as an interlayer insulating film.
第２図（ａ）、（ｂ）は本発明の第２の実施例を説明す
るための半導体チップの断面図である。FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.
まず第２図（ａ）に示すように、半導体基板１上に酸化
膜１１を形成したのち、半導体基板１と電気的接続をは
かるためのコンタクト孔１２を形成する。次で配線に用
いる金が半導体基板１に拡散しないようにするためのバ
リアメタルとしてＴｉＷ膜１３を形成したのち、第１の
実施例と同様の形成方法を用いて第１ポリイミド層２、
メツキ用型ｉ４．３．５・μｍ厚の第１の配線６を形成
する。この際同時に第１ポリイミド層２にも０．５μｍ
厚の第１の配線６Ａを形成する。First, as shown in FIG. 2(a), an oxide film 11 is formed on a semiconductor substrate 1, and then a contact hole 12 for electrical connection with the semiconductor substrate 1 is formed. Next, after forming a TiW film 13 as a barrier metal to prevent gold used for wiring from diffusing into the semiconductor substrate 1, a first polyimide layer 2,
A first wiring 6 having a thickness of 4.3.5 μm is formed using a plating mold i4. At this time, the first polyimide layer 2 is also coated with a thickness of 0.5 μm.
A thick first wiring 6A is formed.
ポリイミド層上の平坦部に設けた第１の配線６Ａの配線
抵抗は、第１ポリイミイド層２の溝に設けた同一配線幅
をもつ第１の配線６の配線抵抗よりも大きくなるが、半
導体基板１との間の配線容量は小さくすることができる
。The wiring resistance of the first wiring 6A provided in the flat part on the polyimide layer is greater than the wiring resistance of the first wiring 6 having the same wiring width provided in the groove of the first polyimide layer 2. 1 can be made small.
次に第２図（ｂ）に示すように、第２ポリイミイドＮ７
を形成したのちスルーホールを形成し、第１の配線６と
同様の形成方法を用いて第２の配線１０を形成する。本
第２の実施例では、０．５μｍ厚で第１ポリイミド層２
上の平坦部に形成した配線６Ａと溝部に金を埋めこんで
形成した配線６の２種類の配線を使用することができる
。Next, as shown in FIG. 2(b), a second polyimide N7
After forming, through holes are formed, and the second wiring 10 is formed using the same formation method as the first wiring 6. In this second embodiment, the first polyimide layer 2 is formed with a thickness of 0.5 μm.
Two types of wiring can be used: the wiring 6A formed in the upper flat part and the wiring 6 formed by filling gold into the groove part.
すなわち、配線容量を減らしたい場合には第１ポリイミ
ド層上の平坦部に形成した０、５μｍ厚の配線を、また
配線抵抗を減らしない場合には溝部に形成した配線を用
いる。That is, when it is desired to reduce the wiring capacitance, a wiring having a thickness of 0.5 μm is used, which is formed in a flat part on the first polyimide layer, and when wiring resistance is not to be reduced, a wiring formed in a groove part is used.
以上説明したように本発明によれば、層間絶縁膜を平坦
化することができ下層配線の凹凸を考慮せずに上層配線
を形成することができる。さらに配線間の距離よりも配
線の厚さの方が大きい場合においても空洞が生じること
のない層間絶縁膜を形成することができるという効果が
ある。As explained above, according to the present invention, the interlayer insulating film can be planarized, and the upper layer wiring can be formed without considering the unevenness of the lower layer wiring. Furthermore, even when the thickness of the wiring is greater than the distance between the wirings, it is possible to form an interlayer insulating film in which no cavities are formed.
第１図及び第２図は本発明の第１及び第２の実施例を説
明するための半導体チップの断面図、第３図は従来例を
説明するための半導体チップの断面図である。
１・・・半導体基板、２・・・第１ポリイミド層、３・
・・窒化膜、４，４Ａ・・・メツキ用電極、５・・・フ
ォ１〜レジスト膜、６，６Ａ・・・第１の配線、７・・
・第２ポリイミイド層、８・・・スルーホール、１０・
・・第２の配線、１１・・・酸化膜、１２・・・コンタ
クト孔、１３・・・ＴｉＮ膜、１５・・・有機樹脂層、
１６・・・下層配線、１７・・・空洞。
代理人 弁理士 内 原 晋
Ｋｌ 図
元 １
図
図
〒
図1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First polyimide layer, 3...
... Nitride film, 4,4A... Electrode for plating, 5... Fo1 to resist film, 6,6A... First wiring, 7...
・Second polyimide layer, 8...Through hole, 10・
...Second wiring, 11...Oxide film, 12...Contact hole, 13...TiN film, 15...Organic resin layer,
16... Lower layer wiring, 17... Cavity. Agent Patent Attorney Susumu Uchihara Illustration Source 1 Illustration
Claims (1)
成したのち半導体基板に達する配線形成用の溝を形成す
る工程と、前記溝の内部に第１の配線を形成する工程と
、前記第１の配線表面を含む全面に有機材料からなる第
２の層間絶縁膜を形成する工程と、前記第２の層間絶縁
膜に配線接続用の開口部を形成し第１の配線の表面を露
出させる工程と、前記開口部を介して第１の配線に接続
する第２の配線を形成する工程とを含むことを特徴とす
る半導体集積回路の製造方法。a step of forming a first interlayer insulating film made of an organic material on a semiconductor substrate and then forming a trench for forming a wiring that reaches the semiconductor substrate; a step of forming a first wiring inside the trench; forming a second interlayer insulating film made of an organic material over the entire surface including the first wiring surface; and forming an opening for wiring connection in the second interlayer insulating film to expose the surface of the first wiring. 1. A method of manufacturing a semiconductor integrated circuit, the method comprising: forming a second wiring connected to the first wiring through the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8750289A JPH02265262A (en) | 1989-04-05 | 1989-04-05 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8750289A JPH02265262A (en) | 1989-04-05 | 1989-04-05 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02265262A true JPH02265262A (en) | 1990-10-30 |
Family
ID=13916758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8750289A Pending JPH02265262A (en) | 1989-04-05 | 1989-04-05 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02265262A (en) |
-
1989
- 1989-04-05 JP JP8750289A patent/JPH02265262A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0613470A (en) | Manufacture of semiconductor device | |
| JPH1117005A (en) | Semiconductor device and manufacture thereof | |
| JPH08335634A (en) | Manufacturing method for semiconductor device | |
| JP3504250B2 (en) | Method for manufacturing semiconductor device | |
| JPH10163198A (en) | Semiconductor device and its manufacture | |
| JPH02265262A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01289142A (en) | Vertical wiring structure | |
| JPH05226475A (en) | Manufacture of semiconductor device | |
| JPH036045A (en) | Manufacture of semiconductor device | |
| JPS6347952A (en) | Semiconductor device | |
| JPS62264642A (en) | Formation of through holes | |
| JPH0621240A (en) | Wiring connecting structure of semiconductor device and manufacture thereof | |
| JPH0661354A (en) | Manufacture of semiconductor device | |
| JPS63107043A (en) | Forming method of conductive line for semiconductor device | |
| JPH0936222A (en) | Semiconductor device and its manufacture | |
| JPS59148348A (en) | Semiconductor device and manufacture thereof | |
| JPH06244187A (en) | Manufacture of semiconductor device | |
| JPH09186232A (en) | Manufacture of semiconductor device | |
| JPH06236931A (en) | Wiring structure and its manufacture | |
| JPH08139185A (en) | Manufacture of semiconductor device | |
| JPS63108751A (en) | Manufacture of semiconductor device | |
| JPH04115535A (en) | Semiconductor device and its manufacture | |
| JPH04279031A (en) | Manufacture of semiconductor device | |
| JPH03248533A (en) | Semiconductor integrated circuit device | |
| JP2000031271A (en) | Manufacture of multi-layer interconnection semiconductor device |