JPS63108751A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield of a product in simple steps by forming a hole formed at an interlayer insulating layer in a state the opening is buried by a first by a first electrode layer. CONSTITUTION:A first interlayer insulating layer 22 is formed on a semiconductor substrate 21 formed with a circuit element. An opening 23 is formed corresponding to the terminal region of the element in the layer 22. A wiring layer 24 is formed on the whole surface of the layer 22, a photoresist film is formed on the layer 24, removed except the part corresponding to the opening 23, and a mask pattern 25 for masking only the part corresponding to the hole 23 is formed. The layer 24 is removed by etching by the pattern 25, and only a buried wiring layer 241 remains. Then, the pattern 25 is removed, and an electrode wiring layer 26 is formed on an interlayer insulating layer 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a method of manufacturing a semiconductor device constituting an integrated circuit device, etc., in which a means for leading out electrodes from an element portion formed on a semiconductor substrate is improved. .

[Prior Art] In a semiconductor device in which an integrated circuit device is incorporated,
An opening is formed in an interlayer insulating layer corresponding to a terminal region of an element formed on a semiconductor substrate, and a metal wiring layer is formed on the interlayer insulating layer in a state including the opening.

For example, as shown in FIG. 6, an interlayer insulating layer 12 is formed on a semiconductor substrate 11, an opening 13 is formed in this interlayer insulating layer 12 corresponding to a terminal area of an element formed on the substrate 11,
An electrode wiring layer 14 including this opening 13 is formed. Further, in the case of forming a multilayer wiring structure, a second interlayer insulating layer 15 having an opening corresponding to the opening 13 is formed on the electrode wiring layer 14,
A second electrode wiring layer 16 is formed on this second interlayer insulating layer 15.

However, in such an electrode lead-out structure, the level difference between the electrode wiring layers 14 and 1G and the contact portion of the substrate 11 becomes severe, and the step coverage of the electrode wiring layer deteriorates. That is, in the areas around the openings of interlayer insulating layers 12 and 15, the electrode wiring layers 14 and 16 become thinner, which not only increases wiring resistance but also may cause disconnection. Especially when it comes to a multilayer wiring structure,
A through hole is formed at the opening that serves as the second electrode lead-out portion, and the level difference in the through hole portion becomes even more severe, making the above problem more noticeable and becoming one of the causes of reduced product yield.

Means for improving these problems include, for example, etching back the interlayer insulating layer to planarize the opening for leading out the electrodes, burying the electrodes by bias sputtering, and using 5OG (spion glass). Flattening means etc. are being considered. However, such a planarization means not only requires a technically advanced one, but also increases the number of steps required for the planarization, and it is difficult to sufficiently improve the yield.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points. A semiconductor device that enables highly reliable semiconductor devices to be manufactured at a good yield by preventing the formation of thin parts in electrode wiring layers and reliably preventing increases in wiring resistance and occurrence of disconnection failures. The present invention attempts to provide a method for manufacturing the device.

[Means for Solving the Problems] That is, in the method of manufacturing a semiconductor device according to the present invention, first, an opening is formed on the surface of a semiconductor substrate on which an element is formed, corresponding to a terminal region of the element. A first electrode wiring layer is formed on this interlayer insulating layer in a state including the opening, and then this electrode wiring layer is formed so as to correspond to the opening. Remove all but the parts.

Then, a second electrode wiring layer is formed on the interlayer insulating layer so as to be connected to the first electrode wiring layer left in the opening.

[Function] In the manufacturing method described above, first, the opening corresponding to the terminal region formed in the interlayer insulating layer is filled with the first electrode wiring layer, and the The electrode wiring layer on the interlayer insulating layer is removed except for the electrode wiring layer. That is, the opening corresponding to the electrode lead-out portion formed in the interlayer insulating layer is
It is in a state where it is buried by the electrode wiring layer, and its surface almost coincides with the surface of the interlayer insulating layer. Therefore, the second electrode wiring layer is formed on a flat surface with no steps, and is reliably connected to the first electrode wiring layer in the opening, avoiding obstacles such as thin parts of the electrode layer. There are no factors that could cause this. In other words, it is possible to obtain a reliable electrode lead-out structure through a simple process that is almost the same as the normal electrode manufacturing process, and is particularly effective when manufacturing integrated circuit devices where high integration is desired. is significant.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The drawings sequentially show the manufacturing process of a semiconductor device with a multilayer wiring structure. First, as shown in FIG. 1, a first interlayer insulating layer 22 is formed on the surface of a semiconductor substrate 21 on which circuit elements such as transistors are formed. This interlayer insulating layer 22
An opening 23 is formed in the area corresponding to the terminal area of the element. Then, on the entire surface of this interlayer insulating layer 22,
The wiring layer 24 is formed by vapor deposition or the like. This wiring layer 24
is formed to include the opening 23, and the wiring layer 24 is connected to the terminal area of the element formed on the substrate 21 at the opening 23.

Once the wiring layer 24 is formed in this manner, a photoresist film is formed on the wiring layer 24, leaving only the portion of the resist film corresponding to the opening 23 and removing the other portion. As shown in FIG. 2, a mask pattern 25 is formed that masks only the portion corresponding to the opening 23. Then, as shown in FIG. Then, using this mask pattern 25, the wiring layer 24 is etched away, leaving only the buried wiring layer 241 buried in the opening 23, as shown in FIG. In this case, if the buried layer is selectively formed without using a photolithography process, there is no need to perform a photolithography process, for example, in the case of SOG.

It is also possible to coat only the buried layer by applying Pi Q, resist, etc., and use this as a mask to form the buried layer.

After the wiring layer 241 is buried in the opening 23 of the first interlayer insulating layer 22 in this way, the mask pattern 25 is removed and the first
A first electrode wiring layer 2B is formed on the interlayer insulating layer 23 by vapor deposition or the like, and a wiring pattern is formed by a photolithography process or the like.

Here, the buried wiring layer 241 and the first electrode wiring layer 26 are made of the same metal material, such as aluminum, or may be made of a combination of different materials. The part of the buried wiring layer 241 that is embedded in the opening 23 has a planar state substantially equal to that of the interlayer insulating layer 22 and is exposed. The electrode wiring layer 2G of No. 1 is now integrally combined with the buried wiring layer 241, and the terminal portion of the element formed on the semiconductor substrate 21 is led out to the electrode wiring layer 2G. .

The first wiring layer is formed in this way, but in order to form a second wiring layer that is further laminated thereon, as shown in FIG. A second interlayer insulating layer 27 is formed on the first electrode wiring layer 2G that is to form a pattern. An opening 28 is formed in this interlayer insulating layer 27 so as to be coaxial with the opening 23 constituting the terminal lead-out portion.

Once the second interlayer insulating layer 27 is formed in this manner, a buried wiring layer 291 is formed so as to be embedded in the opening 28 by the same means as shown in FIGS. 2 and 3. Once this buried wiring layer 29 has been formed, a second electrode wiring layer 30 including this wiring layer 291 portion is formed and patterned, for example, by a photolithography process, to form a second wiring layer. That's what I do.

That is, when the electrode lead-out portion is formed in the above process, the contact openings 23 and 28 formed in the first and second interlayer insulating layers 22 and 27 are filled with a wiring layer buried in the openings. Since the openings 241 and 291 are embedded, the peripheral surface of the opening may be set at a Taber angle 90', for example. therefore,
Even if the openings serving as through holes for contacts are miniaturized, highly reliable electrode wiring can be easily formed, and it is effective for constructing highly integrated circuit devices. be able to. Since the surface of the wiring layer embedded in the opening is formed in a state that almost matches the surface of the interlayer insulating layer, the electrode wiring layer can be aligned with sufficient margin, and the opening can be reflowed. There is no problem with alloy spikes, unlike in the case of other processing.

[Effects of the Invention] As described above, according to the manufacturing method of the present invention, thin portions that increase wiring resistance can be prevented from being formed by a simple means equivalent to a normal electrode wiring layer formation process. In this case, a contact portion of a circuit element such as a transistor formed on a semiconductor substrate can be easily and reliably led to an inter-electrode line portion. In particular, even in a semiconductor device with a multilayer wiring structure, electrodes can be reliably led out, and a great effect is exhibited when a highly integrated semiconductor integrated circuit device (14) is constructed.

[Brief explanation of the drawing]

1 to 5 are cross-sectional configuration diagrams sequentially illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention, particularly the electrode lead-out portion, and FIG. 6 is a cross-sectional view illustrating the electrode lead-out portion of a conventional semiconductor device. FIG. 21... Semiconductor substrate, 22.27... First and second interlayer insulating layer, 23.28... Opening, 241.29
1... Embedded wiring layer, 2B, 30... First and second electrode wiring layer. Applicant's agent Patent attorney Suzue Takehikofan 4

Claims (1)

[Claims] A step of forming an interlayer insulating layer on a semiconductor surface so as to open a terminal region of an element formed in the semiconductor, and forming a wiring layer including the opening on the interlayer insulating layer. A step of forming a mask pattern on the wiring layer formed in this step so that the mask is set corresponding to the opening of the interlayer insulating layer, and a mask pattern formed in this step. a step of removing the wiring layer leaving an embedded wiring layer in a portion corresponding to the opening set in the mask; and removing the mask pattern and leaving the embedded wiring layer corresponding to the opening. A method for manufacturing a semiconductor device, comprising: forming an electrode wiring layer on the interlayer insulating layer so as to be connected to the interlayer insulating layer.