JPH02264448A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive the improvement of the accuracy of pattern arrangement and a pattern defect detection efficiency by a method wherein the L-type patterns are arranged at the four corners of each chip and apart 1mum or more from the end of a scribing region to the side of a circuit pattern. CONSTITUTION:A scribing region 102 is provided for dividing a semiconductor integrated circuit into chips. Marks 103 for pattern arrangement accuracy measurement use which are used in combination as position detecting marks for pattern defect detection use are formed into an L-type pattern configuration, are provided at the 4 corners of each chip and are arranged apart at least 1mum or more from the end of the region 102 to the side of a circuit pattern part 101. In such a way, the accuracy of the pattern arrangement and the pattern defect detection efficiency can be improved without increasing the size of the chip and a manhour for the creation of data.

Description

[Detailed description of the invention]

[Industrial Application Field J] The present invention relates to the placement accuracy of semiconductor integrated circuit patterns and the detection of pattern defects. [Prior Art] In a conventional semiconductor integrated circuit, a position detection mark for pattern defect detection and a mark for measuring pattern placement accuracy are arranged in different positions with patterns having different shapes. [Problems to be Solved by the Invention] ] However, in the above-mentioned conventional technology, since both the position detection mark for pattern defect detection and the mark for measuring pattern placement accuracy must be placed, there are problems such as an increase in the number of man-hours or an increase in chip size. The present invention is intended to solve these problems, and its purpose is to create a mark that does not affect the chip size or the number of man-hours for creating data, and that enables improvement in pattern placement accuracy and pattern defect detection efficiency. The purpose is to provide the shape and placement conditions.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, the position detection mark of the pattern placement accuracy measurement bag and the comparative inspection type defect detection device for detecting pattern defects have the same L-shape, and
At the four corners of the chip, there is a special feature that the scribe area is placed closer to the circuit pattern side than the edge of the scribe area (in both cases, at least Igm apart).

[For production]

According to the above configuration of the present invention, by using the pattern for measuring pattern placement accuracy and the position detection mark of the comparative inspection type defect detection device for detecting pattern defects, it is possible to reduce the number of data creation steps and chip size. [Example] The present invention will be described below based on an example. 1 and 2 show examples of the present invention, and FIG. 1 shows an example of the shape of a position detection mark for pattern defect detection and a mark for measuring pattern placement accuracy. FIG. 2 is an example of the arrangement of the pattern defect detection position detection mark and pattern placement accuracy measurement mark. 101 is a circuit pattern portion, 102 is a scribe area, and 103 is a position detection mark for detecting pattern defects and a mark for measuring pattern placement accuracy. Position detection mark for detecting pattern defects and mark for measuring pattern placement accuracy 10
3 is arranged at least 1 μm or more away from the edge of the scribe area 102. It is only necessary to know the coordinates of the X direction and Y direction of the pattern for pattern placement accuracy measurement.
It is sufficient that a rectangle parallel to the direction and a rectangle parallel to the Y direction are arranged. However, in the case of light wave length measurement, since scanning is performed in a direction parallel to the short side of the rectangle, other rectangles adjacent to the long side of the rectangle are arranged. An appropriate spacing is required between the pattern of
The value must be at least 1 μm or more. In addition, the position detection mark of the comparative inspection type defect detection device that detects pattern defects may be any mark that indicates the boundary between the circuit pattern and the scribe area.Therefore, the pattern for measuring pattern placement accuracy is an L-shaped pattern. This can be done by placing the pattern 1 μm or more away from the scribe area, and the position detection mark of the comparative inspection type defect device that detects pattern defects can be achieved by placing the above-mentioned pattern near the boundary between the circuit pattern and the scribe area. good. FIG. 3 shows a conventional example, in which 104 is a position detection mark for pattern defect detection, and 105 is a mark for measuring pattern placement accuracy. Position detection mark 10 for pattern defect detection
4 and the mark 105 for measuring pattern placement accuracy are separately arranged within one circuit pattern 101. [Effects of the Invention] As described above, according to the invention, by using both the position detection mark for detecting pattern defects and the mark for measuring pattern placement accuracy, a predetermined number of steps can be achieved without increasing the chip size or the number of man-hours for creating data. It becomes possible to achieve the purpose of position detection and measurement of placement accuracy. FIG. 3 is a diagram showing a conventional example. 101...Circuit Bakun part 102...Scribe area 103...Position detection mark for pattern defect detection and pattern placement accuracy measurement mark 104...Position detection mark for pattern defect detection 105...Pattern placement accuracy measurement mark or above

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the shape of a position detection mark for pattern defect detection and a mark for measuring pattern placement accuracy in a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram showing an example of the arrangement of position detection marks for detecting pattern defects and marks for measuring pattern placement accuracy. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) Figure

Claims (1)

[Claims] In a semiconductor integrated circuit having a scribe area provided for separating the semiconductor integrated circuit into each chip,
A semiconductor integrated circuit characterized in that L-shaped patterns are arranged at the four corners of each chip at a distance of at least 1 μm from the edge of the scribe region toward the circuit pattern.