JPH02264224A - Manufacture of active matrix substrate capable of spot defect detection and repair - Google Patents

Abstract

PURPOSE:To relieve or suppress a spot defect by evading a connection between an insulation gate type transistor(TR) for driving which has a characteristic defect or internal short circuit and a pixel electrode. CONSTITUTION:A DC voltage is applied between two signal lines 12(n) and 12(n+2), a DC voltage which turns on the insulation gate type TR 10 sufficiently or a DC voltage which turns off the TR is selected and applied to one scanning line 11(m), and the value of a current which flows between the two signal lines is measured. Then ON/OFF inspection is performed while two insulation gate type TRs 10 in addresses (m,n) and (m,n+1) are connected in series. Then a DC voltage is applied between two signal lines 12(n+1) and 12(n+3) and the value of a flowing current is measured to perform inspection while two insulation gate type TRs 10 in addresses (m,n+1) and (m,n+2) are connected in series. Thus, only normal insulation gate type TRs 10 share the pixel electrode to suppress the occurrence of a spot defect with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a design method, an inspection method, and a manufacturing method that enable effective detection and repair of point defects in image display devices, particularly active matrix image display devices.

Conventional Technology Due to recent advances in microfabrication technology, liquid crystal materials, and mounting technology, it has become possible to obtain television images on a commercial basis with liquid crystal panels that are small in size, about 2 to 6 inches, but are acceptable for practical use. Ta. Color display can be easily realized by forming an RGB colored layer on one of the two glass plates that make up the liquid crystal panel, and it is also a so-called active type liquid crystal panel in which each picture element has a built-in switching element. This ensures images with low crosstalk and high contrast ratio.

Such a liquid crystal panel has 120-24 scanning lines.
0 wires, approximately 240-720 signal wires) I
A semiconductor integrated circuit chip 3 that supplies a drive signal to a group of electrode terminals 6 of scanning lines formed on one glass substrate 2 forming a liquid crystal panel 1, as shown in FIG. 27, is standard. Directly connect COG (Ch i
T)-On-G 1 aSS) method, for example, a connection film 4 based on a polyimide resin thin film and having a gold-plated copper foil terminal group (not shown) is bonded to the electrode terminal group 5 of the signal line. An electrical signal is supplied to the image display section by a mounting means such as applying an agent and fixing the connection film 4 while pressing it. Although two mounting methods are illustrated here for convenience, it goes without saying that one of the mounting methods will be selected in reality.

Note that 7.8 is a wiring path that connects the image display section of the liquid crystal panel 1 and the electrode terminal group 5.6 of the signal line and scanning line, and is not necessarily made of the same conductive material as the electrode terminal group. There's no need.

9 is another glass plate having a transparent conductive counter electrode common to all picture elements, and the two glass plates 2.9 are separated by a predetermined distance by a spacer such as a quartz fiber or a plastic bead. The gap is a closed space sealed with a sealing material and a sealing material, and the closed space is filled with liquid crystal.

To realize a color display, an organic thin film called a colored layer containing either dye or pigment or both is deposited on the closed space side of the glass plate 9 to provide a color display function. Also called a color filter. Depending on the properties of the liquid crystal material, a polarizing plate is pasted on either or both of the upper surface of the glass plate 9 or the lower surface of the glass plate 2, and the liquid crystal panel 1 functions as an electro-optical element.

FIG. 28 is an equivalent circuit diagram of an active liquid crystal panel in which an insulated gate transistor 10 is arranged as a switching element for each picture element. Elements drawn with solid lines are formed on one glass substrate 2, and elements drawn with broken lines are formed on the other glass substrate 9. Scanning line 11 (8
) and the signal line 12 (7) are fabricated on the glass substrate 2 at the same time as forming the thin film transistor 10 having, for example, amorphous silicon as a semiconductor layer and a silicon nitride film (Sis N4) as a gate insulating film.

The liquid crystal cell 13 is a closed cell composed of two glass plates: a transparent conductive pixel electrode 14 formed on a glass substrate 2, and a transparent conductive counter electrode 15 formed on a color filter 9. It consists of a liquid crystal that fills the space, and is treated electrically the same as a capacitor. In order to align the liquid crystal molecules in a predetermined direction, it is necessary to form an alignment film on the opposing electrode and the picture element electrode, but detailed explanation thereof will be omitted here.

As described above, the colored layers made of colored photosensitive gelatin or colored photosensitive resin are arranged in the three primary colors of RGB in a predetermined arrangement on the closed space side of the color filter 9 in correspondence with the picture element electrodes. A counter electrode 15 common to all picture element electrodes is formed on the colored layer in order to avoid voltage distribution losses due to the presence of the colored layer.

Note that in FIG. 28, the storage capacitor 18 is not necessarily an essential component for an active liquid crystal panel, but it is useful for improving the utilization efficiency of the driving signal source, suppressing disturbances caused by stray parasitic capacitance, and during high-temperature operation. It is effective in preventing image flickering and is appropriately employed. Reference numeral 17 denotes a conductive path common to all storage capacitors 16, and generally 15 and 17 are used connected.

As is well known, image display devices are objects that are identified by the highly sensitive sensor of human vision, so there are very strict restrictions on various image defects. However, it is very difficult to compare with CRT, in other words, it can be said that the yield is low and it is a device that is difficult to manufacture.

In order for the yield to be extremely high and active LCD panels to be provided almost without inspection, further technological development will be required and it will take some time, and it will be similar to silicon-based semiconductor processes. As long as the manufacturing method continues, no matter how much the yield improves, the
It would be impossible to say that 0% of the products are good.

A line defect is a defect that literally appears in the form of a line on the screen, and the reason for its occurrence is clearly explained below.

(1) The scanning line or signal line is disconnected midway, (2) The electrical signal is not reaching the scanning line or signal line, (3) The scanning line and signal line are short-circuited, (4)
The main cause is that multiple scanning lines or signal lines are short-circuited.

Line defects are relatively easy to detect even before two glass plates are bonded together to form a liquid crystal panel, that is, even in the state of an active matrix substrate, and it is also possible to make the product appear defect-free by repairing it. . for example,
To deal with disconnections, in addition to regular connections to electrode lines such as scanning lines and signal lines, it is sufficient to apply the same signal from the other end via a relief line. This is because if the short circuit is cut with a laser or the like and turned into a break in one of the electrode wires, the same treatment as a break can be taken.

Inspecting point defects is equivalent to inspecting full pits in the case of semiconductor memory, and although it varies depending on the structure of the device, it is not hard to imagine that the inspection time is generally long and difficult. In fact, at present, point defects are also checked from a quality perspective during image inspection in the final process, and inspection machines that can effectively detect point defects during the manufacturing process have not yet been put into practical use. Not yet. Reducing point defects is an urgent issue in order to improve image quality.

FIG. 29 shows an equivalent circuit of an example of an improvement measure implemented to reduce the influence of point defects on displayed images. An insulated gate transistor and a pixel electrode, which are switching elements constituting a unit pixel, are divided and arranged into a plurality of pieces (two in FIG. 29), and at least one set of an insulated gate transistor and a pixel electrode is formed. This is an attempt to ensure display functionality. It is easy to understand that with this improvement measure, the deterioration in display image quality due to point defects that cannot be controlled by electrical signals is alleviated when compared with surrounding picture elements in which multiple picture element electrodes are operating normally. Good morning.

Further, the degree of relaxation is more effective as the number of divided picture elements is larger. However, if the number of divisions is increased, the space for separating the elements no longer contributes to display, and the aperture ratio inevitably decreases, so it is obvious that there are restrictions. In addition, in the case of a normally black display method, although the white spot defect is alleviated, the display always lights up (lights up) when there is no signal.
Therefore, it is very noticeable unless the picture element is very small, and it is unavoidable that the effect is evaluated as low compared to the degree of relaxation of sunspot defects.

In the configuration shown in Fig. 29, it is easy to shift the unit picture elements by half a pitch every other row, and arrange the RGB colored layers on the color filter in a delta (triangular) arrangement, which increases the apparent resolution even when the number of picture elements is small. This has the advantage of ensuring that The drawback is that it is impossible to tell which of the two sets has lost its display function unless it is converted to a liquid crystal panel.

FIG. 30 shows an equivalent circuit of another improvement measure. Two insulated gate transistors 10-1 and 10-2 are arranged diagonally within a unit picture element, and one liquid crystal cell 13 is shared and driven by the two insulated gate transistors. Even if the current supply capability of any of the insulated gate transistors decreases, writing to the picture element electrode is maintained using the normal one.

In addition, since the two insulated gate transistors are connected in series to form a closed loop, the electrical characteristics of the insulated gate transistor can be electrically tested from the outside. ON
If this occurs, the same solution as described above can be taken by cutting off the regular wiring using a cutting means such as a laser.

The disadvantage of the above improvement measures is that, in the case of color image display, the pixel electrodes must be located diagonally;
If the arrangement of the colored layers is limited to an oblique arrangement (mosaic) and the number of picture elements is small, interference fringes are likely to be noticeable. Next, in a strict sense, normal writing is not being performed in a pixel whose current supply capacity has decreased in an insulated gate transistor, and the color signal of an adjacent pixel is visually deceiving, resulting in a high It would be difficult to create an image of dignity. Even if it is acceptable as a television image, it is questionable as an office automation display that displays characters and graphics.

In the first improvement measure mentioned above, even if a plurality of insulated gate transistors as switching elements are arranged to provide redundancy against a drop in drive current capacity, control is lost due to internal short circuits of the insulated gate transistors. cannot be detected in the state of an active matrix substrate, and in the end, the essential problem of not being able to detect the presence of white spot defects by using a liquid crystal panel to display images has not been solved.

Although the success rate is low, it is possible to convert white dot defects into black dot defects by irradiating the liquid crystal panel with a laser to separate insulated gate transistors with internal short circuits from the pixel electrodes. When a plurality of transistors are arranged, it is completely meaningless unless it is known which insulated gate transistor has an internal short circuit.

Problems to be Solved by the Invention However, in the second improvement measure, although it is possible to detect point defects, it is not possible to correct defects that are not displayed with regular color signals when point defects occur. Improvement is needed. In addition, in this case, simply dividing the pixel electrode will not allow the insulated gate transistor to form a closed loop.
It has the same drawbacks as the first improvement example, and even if it is divided, there is no point in dividing it if the picture element electrodes are connected.

Means for Solving the Problems The present invention was developed in view of the above-mentioned current situation, and first removes the active matrix substrate so that the electrical characteristics of the insulated gate transistor, which is a switching element, can be inspected and evaluated on the active matrix substrate. Use possible wiring materials to connect the drain electrode or pixel electrode of an insulated gate non-type transistor for driving and a necessary signal line, between the drain electrodes or pixel electrodes of a plurality of insulated gate transistors, and even between the drain electrodes or pixel electrodes of a plurality of insulated gate transistors. A temporary electrical connection is made between the insulated gate transistor and the auxiliary insulated gate transistor, and the insulated gate transistor is electrically inspected to detect the location of the insulated gate transistor with poor characteristics, which is the main cause of point defects. .

Then, based on the information on the location and type of the characteristic defect, it is determined whether or not to proceed with the active matrix substrate in question to the panel assembly process. Prior to proceeding to the panel assembly process, temporary connections made with removable wiring material are removed using engineered etchings so as not to adversely affect the regular wiring, and multiple insulated gate transistors are removed. For those composed of unit pixels, point defects can be avoided by using a laser or other means to disconnect the pixel electrode from an insulated gate transistor with poor characteristics such as an internal short circuit. A repaired liquid crystal panel is obtained.

In a further improved manufacturing method, pixel electrodes are formed after the electrical inspection of multiple insulated gate transistors is completed, and insulated gate transistors with poor characteristics are selectively removed, leaving only normal insulated gate transistors. By co-locating the picture element electrodes, it is possible to suppress the occurrence of point defects with extremely high precision.

Insulated gate transistors for operation and drive are removed between signal lines outside the regular circuit configuration, auxiliary insulated gate transistors, or between multiple insulated gate transistors to form a closed loop. It is formed as an active matrix substrate in a state where it is temporarily connected using available wiring materials.

Therefore, it is possible to electrically and independently test the transistor characteristics of all insulated gate transistors from the outside. Therefore, the point defects can be alleviated or suppressed by avoiding the connection between the picture element electrode and the driving insulated gate transistor that has poor characteristics or internal short circuits. The wiring material used for temporary connection is removed after the electrical inspection of the insulated gate transistor is completed using an etching method selected so as not to affect other elements, so even if the wiring material used for temporary connection is Even if the material is short-circuited with the regular wiring, no secondary defects will occur in the end.

Embodiment FIG. 1(a) is an equivalent circuit of a liquid crystal panel having an active matrix structure according to a first embodiment, which is the basic concept of the present invention. As can be seen from the comparison with the conventional example in FIG.
An active matrix substrate is manufactured with a connection line 20 formed between a drain electrode or a picture element electrode of 0 and an adjacent signal line, and then inspected in an inspection step. After the electrical inspection of the insulated gate transistor 10 is completed, for example, by removing the connection line in the opening 21 formed including the connection line 20, the connection line adjacent to the drain electrode or the pixel electrode of the insulated gate transistor 10 is removed. By disconnecting the signal lines, the final circuit configuration becomes the same as that of a conventional liquid crystal panel.

The insulated gate transistor 10 has the function of AC charging and discharging the liquid crystal cell 13 as a switching element, and although the source and drain cannot be uniquely defined, it is customary here to mean supplying a video signal. The side connected to the signal line is defined as the source, and the side connected to the picture element electrode is defined as the drain.

According to the circuit configuration of FIG. 1(a), first, two signal lines 1
Applying a DC voltage between 2(n) and 12(n+2),
And the DC voltage applied to one scanning line 11 (m) is a voltage sufficient to turn on the insulated gate transistor 10 and OF
By selecting and applying the voltage to F and measuring the value of the current flowing between the two signal lines, the (man) address and (ml
An 0N10FF test is performed with two insulated gate transistors at address n +1 ) connected in series. Next 2
By applying a DC voltage between two signal lines 12 (n+1) and 12 (n+3) and measuring the current value flowing between the two signal lines, the address (m, n+1) and (m, n
+2) Inspect the two insulated gate transistors at address connected in series.

Through these two measurements, the insulated gate transistor at address (ml n + 1) is tested twice in succession. By performing such an inspection on all signal lines and scanning lines, all insulated gate transistors are inspected twice in succession, and there are no point defects between the source and drain of the insulated gate transistor 10. It is possible to know the 0N10FF characteristics of all insulated gate transistors as long as short circuits and open circuits that cause this do not occur consecutively. This makes it possible to predict point defects due to poor characteristics of the driving insulated gate transistor, which could not be detected unless the liquid crystal panel was constructed as in the past, and the effect is extremely high.

Of course, it goes without saying that short circuits between the gate and source or gate and drain of an insulated gate transistor can be easily detected by measuring the current flowing between the scanning line and the signal line.

The failure modes of the insulated gate transistor 10 can be roughly divided into: 1) the drain current is small relative to a given gate voltage (small ON current), 2) the drain current constantly flows too much (large OFF current), and 3) the gate Drain shorted (
4) There is a short circuit (leakage) between the gate and source. In image display using the no/black display method, case 1) results in a black dot defect, cases 2) and 3) result in a white point defect, and case 4) results in a cross-shaped line defect.

In the case of 1), the causes of point defects that occur irregularly on each substrate include unstable or lost electrical contact between the pixel electrode, insulated gate transistor, and source/drain wiring. In some cases, the function of an insulated gate transistor is not fully exhibited due to the absence of a semiconductor layer. In the case of 2), the O of the insulated gate transistor is
There are cases where the leakage current between the source and drain during FF is too large and cases where the source and drain are short-circuited, but the former occurs in all insulated gate transistors as an abnormality in the film quality of the semiconductor layer. Therefore, it cannot be the cause of point defects that occur irregularly on each board, and must be managed separately by inspecting monitor transistors and the like. In the circuit configuration of FIG. 1(a), there are 200 to 400 insulated gate transistors that are not to be tested in parallel in the scanning line direction, but since the 0N10FF ratio of insulated gate transistors is usually more than 5 digits, the present invention This does not interfere with testing the 0N10FF characteristics of insulated gate transistors.

If we could know all defects in insulated gate transistors along with their addresses, we would be able to decide whether to proceed to the panel assembly process as good, defective, or recyclable products based on preset criteria, and waste expensive color filters. You can avoid consuming it. However, in the first embodiment, since there is only one driving insulated gate transistor in each unit pixel, the only reproducible failure mode is the short-circuiting of 2), 3), and 4) caused by laser cutting. By means of
Only treatments that convert white spot defects to black spot defects are effective.

The short circuit (4) must be converted into a disconnection by cutting either the scanning line or the signal line, and it goes without saying that a remedy for the disconnection must also be prepared at the same time.

At present, the structure and manufacturing method of an insulated gate transistor have not yet been established, and therefore various structures and manufacturing methods of an active matrix substrate can be considered.
An example of a pattern layout diagram corresponding to figure (a) is shown in figure 1 (b).
), and cross-sectional views taken along lines A-A' and B-B'' in FIG. 1(b) are shown in FIG. 1(C) and FIG. 1(d). Branch portions 22 and 23 of the signal line 12 are source and drain wiring made of Al, for example, and the drain wiring 23 is different from the pixel electrode 14 under the insulating layer through the opening 24 formed in the insulating layer.
connected via. The connection 20 between the drain wiring 23 and the adjacent signal line is made by arranging a connection pattern 2S made of, for example, Cr and formed in the same process as the scanning line 11, and through an opening 2 formed in the gate insulating layer above the connection pattern 25.
6.27 between the drain wiring 23 and the adjacent signal line branch 28. The release of the connection 20 is caused by the connection pattern 2 formed at the same time as the opening 28.27.
This is accomplished by removing the Cr exposed through the opening 21 on the top 5 with a Cr etching solution containing cerium nitrate as a main component, and dividing the connection pattern 25. The Cr etching liquid has a low acidity of pH 5-6, and will not corrode signal lines or source/drain wiring made of AI.

In FIGS. 1(c) and 1(d), the insulating layer 29 on the picture element electrode 14 made of ITO is a highly transparent protective layer to avoid plasma damage caused by PCVD, such as silicon oxide (8,02) or 5 Tantalum oxide (T a 20 s
) is optimal, 30 is an impurity-free amorphous silicon layer that becomes the channel of the insulated gate transistor, 31
32 is a silicon nitride film (SIN) which is a gate insulating layer; 33 is an impurity layer 31; A silicon nitride film (SIN8) is used as an etching stopper for the etching. A for improving the heat resistance of insulated gate transistors
It is necessary to interpose a metal thin film such as Cr or Ti or a silicide thin film as a barrier metal between the source/drain wiring 22, 23 made of T and the impurity layer 32, and the occurrence of an impurity on the surface of the gate wiring 11 made of Cr. Details such as the layering of silicide thin films to prevent this will be omitted here.

Of course, a structure in which the picture element electrode 14 and the drain wiring 23 are connected directly instead of through the opening 24 is also possible, and the connection pattern 25 may be made of a different material than the scanning line 11 or may be made of a different material. Although it is possible to configure the manufacturing process using additional steps, the above-described process is optimal in the sense that the number of manufacturing steps does not increase.

As described above, the main points of the present invention in the first embodiment are as follows: 1) two insulated gate transistors are connected in series with a removable wiring material to form a closed loop; ) A concept is disclosed in which the connection is released after the electrical inspection of the insulated gate transistor is completed and the insulated gate transistor becomes independent.

In the first embodiment shown in FIG. 1, since there is only one set of insulated gate transistors and pixel electrodes responsible for display, the only repair possible is to convert a white spot defect into a black spot defect. They are extremely powerless against outbreaks. In this sense, applying the present invention to an active matrix substrate that is equipped with a plurality of insulated gate transistors and pixel electrodes and has redundancy against the occurrence of point defects further increases redundancy and improves yield. It is important in the sense that it contributes to When two sets of structural units each consisting of an insulated gate transistor for driving and a picture element electrode are prepared, there are four methods of arranging the structural units within the display area, and the following embodiments will be explained in order.

As a second embodiment, when one set of structural units is placed on each side of the signal line, there are three types of circuit configurations in which two insulated gate transistors form a closed loop in series, and the circuit configurations shown in FIGS. An embodiment will be described with reference to the drawings.

According to the circuit configuration of FIG. 2(a), the drain electrode or picture element electrode of the first insulated gate transistor 10-1 at address (ml n) is connected to (m, n+
1) Connected to the drain electrode or picture element electrode of the second insulated gate transistor 10-2 at the address. Therefore, a DC voltage is applied between the two signal lines 12 (n) and 12 (n+1), and the DC voltage applied to the scanning line 11 (m) is set to a voltage sufficient to turn on the insulated gate transistor and to turn it off. By selecting and applying a voltage and measuring the value of the current flowing between the two signal lines, the voltage can be set to 0 with the first and second two insulated gate transistors connected in series.
N10FF can be tested. However, due to the symmetry of the circuit configuration, it is not possible to identify which of the first and second insulated gate transistors is the cause of the small ON current or OFF current point defect. ON current is small or OFF
It can be known that the cause of the FF current point defect exists. That is, point defects can be detected. Figure 2 (a
) is shown in FIG. 2(b). The connection line 20 is composed of two drain wirings 23-1 and 23-2 and a connection pattern 25 made of Cr.

According to the circuit configuration of FIG. 3(a), the drain electrode or picture element electrode of the first insulated gate transistor 10-1 at address (m, n) is connected to (m, n+
2) Connected to the drain electrode or picture element electrode of the second insulated gate transistor 10-2 at the address. Therefore, a DC voltage is applied between the two signal lines 12(n) and 12(n+2), and the DC voltage applied to the scanning line 11(m) is set to a voltage sufficient to turn on the insulated gate transistor and to turn it off. By selecting and applying a voltage and measuring the value of the current flowing between the two signal lines, the voltage is 0N when the first and second two insulated gate transistors are connected in series.
10FF inspection is possible. In this case, as in the case of FIG. 2, it is only possible to know the existence of a point defect.

Since the connection line 20 needs to intersect with the signal line, it is necessary to use a multilayer wiring formed in the same process as the scanning line at the intersection, and connect it to the signal line and the drain of the insulated gate transistor through an opening. It is reasonable to do so. Connection line 20
The probability that the signal line 12 (n+1) is short-circuited is not O, but even if it is short-circuited, the signal line 12 (n+1) is open, so it is driven by the signal line 12 (n+1) (ml
Unless another connection line connected to the drain electrodes of the first and second insulated gate transistors at address n +1 ) is short-circuited with the signal line 12(n) or the signal line 12(n+2) at the same time, ( It will be seen that there is no problem in testing the first insulated gate transistor 10-1 at address (m, n+2) and the second insulated gate transistor 10-2 at address (m, n+2).

It can be said that the probability that such a short circuit will occur in two consecutive places is approximately O in the current well-controlled manufacturing process. It can also be seen that if the connecting wire 20 can be separated at the portions 21-1 and 21-2, secondary defects will not occur in the end. Similarly, an opening 21-3 may be provided at the intersection between the connection line 20 and the drain electrode of the first insulated gate transistor. Figure 3(a)
A pattern layout diagram corresponding to the above is shown in FIG. 3(b). If the connection line 20 is made up of a connection pattern 25 made of Cr and a connection pattern 34-1.34-2 of Al, with the picture element electrode 14-1.14-2 also serving as a part of the wiring, the connection line 20 can be 2
A multilayer wiring is possible at the intersection between 0 and the drain wiring of the first insulated gate transistor or the picture element electrode. Note that the liquid crystal cell is omitted in Figure 3(a) because the equivalent circuit is complicated, but as in Figure 2(a), all liquid crystal cells are attached to the drain electrodes of the insulated gate transistors. Needless to say, they are connected.

According to the circuit configuration of FIG. 4(a), ' (m, n)
The first insulated gate transistor 10-1 at the address forms a closed loop having a common drain with the second insulated gate transistor 10-2 at the address (m+1.n+1) via the connection line 20. .

Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+1) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+1)
It is possible to determine whether two insulated gate transistors are good or bad based on the magnitude of the DC voltage applied to them. For example, scan line 11
(m), a voltage sufficient to turn on the first insulated gate transistor 10-1 is applied to the scanning line 11(m+1
), the second insulated gate transistor 10-2 is turned on.
Signal lines 12(n) and 12(n
+1), it can be seen that the source and drain of the second insulated gate transistor 10-2 are short-circuited, and although the probability is extremely low,
ONt for two scanning lines.

This is because if current flows even though no voltage is applied, it can be seen that the source and drain of both insulated gate transistors are short-circuited. In other words, OF is applied to either of the two insulated gate transistors.
Even if an FFF current decrease occurs, it can be identified. However, it is impossible to identify a defect with a small ON current due to the symmetry of the circuit configuration. By combining two scanning lines and two signal lines in this manner, it is possible to inspect the characteristics and internal short circuits of all driving insulated gate transistors. A pattern layout diagram corresponding to FIG. 4(a) is shown in FIG.
Shown in b). In order to enlarge the picture element electrode, picture element electrode 1
4-1 also serves as a part of the connection line 20. If the connection line 20 is composed of the connection pattern 25-1, 25-2 made of Cr and the connection pattern 34-L 34-2 made of AI, multilayer wiring can be formed at the intersection of the connection line 20 and the scanning line 11. connection line 2 by the opening 21-1.21-2 formed in the connection pattern 25-1.25-2.
If 0 is separated, even if the scanning line 11 and the connection pattern 34-2 are short-circuited, no secondary failure will occur in the end.

In the embodiments shown in FIGS. 2 to 4, the connection wire 20 is removed after the electrical inspection of the insulated gate transistor is completed;
By opening or dividing, all the same active matrix substrates are obtained, and one picture element electrode is arranged on each side of the signal line. Since a unit pixel consists of two sets of insulated gate transistors and a pixel electrode, in a normally black display system, one of the insulated gate transistors may become a black spot defect due to insufficient current capacity. However, in the embodiment shown in Fig. 4, the OFF current value can identify the location of an insulated gate transistor with a short circuit between the source and drain. By using a cutting means such as a laser to disconnect the relevant insulated gate transistor and the pixel electrode prior to panel assembly, a unique effect can be obtained in which white spot defects can be converted into black spot defects with extremely high precision. .

As a third embodiment, consider the simplest circuit configuration in which two insulated gate transistors form a closed loop in series, where one set of structural units is placed on each side of the scanning line. This will be explained with reference to the drawing of FIG. In addition, since the equivalent circuit becomes complicated, the liquid crystal cell is completely omitted in the embodiments shown in FIG. Please let me know in advance.

According to the circuit configuration of FIG. 5(a), similarly to the circuit configuration of FIG. 4(a), the first insulated gate transistor 10-1 at address (m+n) is connected via the connection line 20. (m+
1. n+1) second insulated gate transistor 1 at address
It forms a closed loop that shares a drain with 0-2. Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+1) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+
1) It is possible to determine the quality of two insulated gate transistors based on the magnitude of the DC voltage applied to the transistor. A pattern layout diagram corresponding to FIG. 5(a) is shown in FIG. 5(b). If the connection line 20 is composed of the connection pattern 25 made of Cr and the connection pattern 34-1, 34-2 made of AI, multilayer wiring is possible at the intersection of the connection line 20 and the signal line 12, and the connection Opening 21-1 formed in pattern 25
．． If the connection line 20 is separated by 21-2, no secondary defects will occur.

As a fourth example, if one set of structural units is placed diagonally at each intersection of the scanning line and the signal line, the circuit configuration in which two insulated gate transistors form a closed loop in series is 3. There are various types, and the embodiments will be explained with reference to the drawings from FIG. 6 to FIG. 8.

According to the circuit configuration of FIG. 6(a), like the circuit configuration of FIG. 5(a), the first insulated gate transistor 10-1 at address (m+n) is connected via the connection line 20. (m+
1. n+1) second insulated gate transistor 1 at address
It forms a closed loop that shares the drain with 0-2. Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+1) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+
1) It is possible to determine the quality of two insulated gate transistors based on the magnitude of the DC voltage applied to the transistor. A pattern layout diagram corresponding to FIG. 8(a) is shown in FIG. 6(b). If the connection line 20 is composed of a connection pattern 25 made of Cr and a connection pattern 34 made of A1, and the function of the connection line 20 is shared with the picture element electrode 14-2, it is possible to increase the size of the picture element electrode. Become. If the connection line 20 is released so that the connection line 20 is separated by the opening 21 formed in the connection pattern 25, no secondary defects will occur.

According to the circuit configuration of FIG. 7(a), the first insulated gate transistor 10-1 at address (m+n) connects to the second insulated gate transistor at address (m+1.n+2) via the connection line 20. A closed loop having a common drain with the type transistor 10-2 is formed.

Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+2) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+1)
It is possible to determine whether two insulated gate transistors are good or bad based on the magnitude of the DC voltage applied to them. A pattern layout diagram corresponding to FIG. 7(a) is shown in FIG. 7(b). Connection line 2o
If the connection pattern 25 is made of Cr and the connection pattern 34-1.34-2 is made of AI, then the connection line 2
0 and the signal line 12, multilayer wiring is possible at the intersection of the signal line 12 and the opening 21-1.2 formed in the connection pattern 25.
If the connection line 20 is separated by 1-2, no secondary defects will occur.

According to the circuit configuration of FIG. 8(a), the first insulated gate transistor 1o-1 at address (m+n) is connected to the second insulated gate transistor at address (m+2.n+1) via the connection line 20. A closed loop having a common drain with the type transistor 10-2 is formed.

2. Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+1) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+
2) It is possible to determine whether two insulated gate transistors are good or bad based on the magnitude of the DC voltage applied. A pattern layout diagram corresponding to FIG. 8(a) is shown in FIG. 8(b). If the connection line 2o is composed of connection patterns 25-1 and 25-2 made of Cr and connection patterns 34-1 to 34-3 made of AI, multilayer wiring can be formed at the intersection of the connection line 20 and the scanning line 11. is possible, and connection pattern 25-1.25-
If the connecting wire 20 is separated by the opening 21-1.2 formed in the knee 2, no secondary defects will occur.

As a fifth embodiment, when two sets of structural units are arranged on one side of the signal line, there are two types of circuit configurations in which two insulated gate transistors form a closed loop in series, as shown in FIGS. 9 and 10. It will be explained as a practical example in the drawings up to this point.

According to the circuit configuration of FIG. 9(a), the drain electrode or picture element electrode of the first insulated gate transistor 10-1 at address (m, n) is connected to (m, n+
1) Connected to the drain electrode or picture element electrode of the second insulated gate transistor 10-2 at the address. Therefore, a DC voltage is applied between the two signal lines 12 (n) and 12 (n+1), and the DC voltage applied to the scanning line 11 (m) is set to a voltage sufficient to turn on the insulated gate transistor and to turn it off. By selecting and applying a voltage and measuring the value of the current flowing between the two signal lines, the voltage is 0N when the first and second two insulated gate transistors are connected in series.
10FF inspection is possible. However, Fig. 2(a)
Similarly to the practical defect shown in FIG. 3(a), it is only possible to detect point defects due to the symmetry of the circuit. A pattern layout diagram corresponding to FIG. 9(a) is shown in FIG. 9(b). The connection line 20 has a connection pattern 25 made of Cr and a connection pattern 3 of A1.
4-L 34-2, the multilayer structure is formed at the intersection of the connection line 20 and the drain electrode of the first insulated gate transistor or the pixel electrode, and at the intersection of the connection line 20 and the signal line 12. Wiring is possible, connection pattern 2
If the connecting wires 20 are separated by the openings 21-1 to 21-3 formed in the openings 21-1 to 21-3, no secondary defects will occur.

According to the circuit configuration of FIG. 10(a), the first insulated gate transistor 10-1 at address (m, n) connects to the second insulated gate transistor at address (m+1.n+1) via the connection line 20. It forms a closed loop having a common drain with the gate type transistor 10-2.

Therefore, if a DC voltage is applied between the two signal lines 12(n) and 12(n+1) and the current value flowing therein is measured, the two scanning lines 11(m) and 11 (m+1)
It is possible to determine the quality of two insulated gate transistors based on the magnitude of the DC voltage applied to them. A pattern layout diagram corresponding to FIG. 10(a) is shown in FIG. 10(b). The connection wire 20 has a connection pattern 25-1.25-2 made of Cr and a connection pattern 34-1.34-2.34- made of A1.
3, multilayer wiring is possible at the intersections of the connection line 20 and the scanning line 11 and the connection line 20 and the signal line 12, and the openings formed in the connection pattern 25-1, 25-2 If the connecting wires 20 are separated by 21-1 to 21-3, secondary defects will not occur.

In the third to fifth embodiments, since a unit picture element is composed of two sets of insulated gate transistors and a picture element electrode, one of the insulated gates is The same effect as before is that even if a type transistor becomes a black spot defect due to insufficient current capacity, it is not noticeable. Since the location of an insulated gate transistor with a drift or a short circuit between the source and drain can be identified, the white spot defect can be removed by disconnecting it from the pixel electrode using a cutting means such as a laser prior to panel assembly. It has the unique effect of converting black spot defects into sunspot defects with extremely high precision.

It is possible to further alleviate point defects by preparing four sets of structural units each consisting of an insulated gate transistor for driving and the N pole of a picture element, although this would result in a slightly more complicated circuit configuration. There are four ways to place the in the display area.
The following examples will be explained in order.

As a sixth embodiment, if four sets of structural units are arranged, one set at every diagonal position at each intersection of a scanning line and a signal line, two
There are two types of circuit configurations in which insulated gate transistors are connected in series to form a closed loop.
It will be explained as an implementation example in the drawings up to the figure. Figure 11(a)
According to the circuit configuration, the first insulated gate transistor 10-1 at address (ml n) is connected to the second insulated gate transistor 10-2 at address (m+1.n+1) via the connection line 20-1. Also, the third insulated gate transistor 10-3 at address (m+1.n) is connected to the fourth insulated gate transistor 10-4 at address (ml n + 2) via the connection line 20-2, They each form a closed loop with a common drain. Therefore, by using the two scanning lines 11 (m) and 11 (m+1) and the two signal lines 12 (n) and 12 (n+1), the first insulated gate transistor 10-1 and the second The quality of the insulated gate transistor 10-2 is determined, and the two scanning lines 11
(m) and 11 (m+1), and two signal lines 12 (n
) and 12(n+2) to determine the quality of the third insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, thereby determining the quality of a total of four insulated gate transistors. can be done independently.

However, due to the symmetry of the circuit, when testing is performed by combining two pieces at a time, it is possible to identify the location of a low OFF current, but it is not possible to identify where the fault is caused by a low ON current, and it is only possible to determine whether it is present or not. It is. 1st
The pattern layout diagram corresponding to Fig. 1(a) is shown in Fig. 11(b).
Shown below. Connection line 20-1 is connection pattern 2 made of Cr.
Connection pattern 34-1.34-2 consisting of 5-1 and AI
The connection line 20-2 has a connection pattern 25-2 made of Cr and a connection pattern 34-3, 34- made of AI.
4, the connecting wire 20-1 and the connecting wire 20-2
, and multilayer wiring is possible at the intersection of the connection line 20-2 and the signal line 12, and the connection pattern 25-1.25
If the connecting wires 20 are separated by the openings 21-1 to 21-5 formed at -2, secondary defects will not occur.

According to the circuit configuration of FIG. 12(a), the first insulated gate transistor 10-1 at address (m, n) is connected to the second insulated gate transistor at address (m+1.n+1) via the connection line 20-1. Insulated gate transistor 10-2 and (m, n+1
) The third insulated gate transistor 10-3 at address ) is connected to the fourth insulated gate transistor 10-4 at address (m + 21 n ) via the connection line 20-2, forming a closed loop in which the drains are common. It consists of Therefore, by using the two scanning lines 11(m) and 11(m+1) and the two signal lines 12(n) and 12(n+1), the first insulated gate transistor 10-1 and the second The quality of the insulated gate transistor 10-2 is determined, and 2
The third
By determining the quality of the insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, it is possible to independently determine the quality of a total of four insulated gate transistors. A pattern layout diagram corresponding to FIG. 12(a) is shown in FIG. 12(b). The connection line 20-1 is made up of a connection pattern 25-1 made of Cr and a connection pattern 34-1.34-2 made of AI, and the connection line 20-2 is made up of a connection pattern 25-2.25 made of Cr.
-3 and AI connection pattern 34-3.34-4.
34-5, connecting wire 20-1 and connecting wire 2
0-2 and the intersection of the connection line 20-2 and the scanning line 11, multilayer wiring is possible, and the connection pattern 25-1
．． If the connecting wire 20 is separated by the openings 21-1 to 21-5 formed in the opening 25-2, no secondary defects will occur.

As a seventh example, if the four sets of structural units are divided into two and two sets are placed on both sides of the signal line, there are two types of circuit configurations in which two insulated gate transistors form a closed loop in series. This will be explained as an embodiment using the drawings from FIG. 13 to FIG. 14.

According to the circuit configuration of FIG. 13, the first insulated gate transistor 10-1 at address (m, n) is connected to the connection line 20-
1, the second insulated gate transistor 10-2 at address (m+1.n+2) and the third insulated gate transistor 10-3 at address (ms n) are connected to connection line 2.
0-2 and the fourth insulated gate transistor 10-4 at address (ml L n +1 ), forming a closed loop having a common drain. Therefore,
Using two scanning lines 11(m) and 11(m+1) and two signal lines 12(n) and 12(n+2), the first insulated gate transistor 10-1 and the second insulated The quality of the gate type transistor 10-2 is determined, and the third By determining the quality of the insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, it is possible to independently determine the quality of a total of four insulated gate transistors. The pattern layout diagram corresponding to FIG. 13 is somewhat complicated and will therefore be omitted.

According to the circuit configuration of FIG. 14, the first insulated gate transistor 10-1 at address (m, n) is connected to the connection line 20-
1, the second insulated gate transistor 10-2 at address (m+2.n+1) and the third insulated gate transistor 10-3 at address (m, n) are connected to the connection line 20-
2 and a fourth insulated gate transistor 10-4 at address (m+1.n+1), forming a closed loop having a common drain. Therefore, two scanning lines 11 (m) and 11 (m+2) and two signal lines 1
2(n) and 12(n+1) are used to determine the quality of the first insulated gate transistor 10-1 and the second insulated gate transistor 10-2, and the two scanning lines 11
(m) and 11 (m+1), and two signal lines 12 (n
) and 12(n+1) to determine the quality of the third insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, thereby determining the quality of a total of four insulated gate transistors. can be done independently. The pattern layout diagram corresponding to FIG. 14 is also somewhat complicated and will therefore be omitted.

As an eighth example, if the four sets of structural units are divided into two and two sets are placed on each side of the scanning line, there are two types of circuit configurations in which two insulated gate transistors form a closed loop in series. This will be explained as an embodiment using the drawings from FIG. 15 to FIG. 16.

According to the circuit configuration of FIG. 15, the first insulated gate transistor 10-1 at address (m, n) is connected to the connection line 20-
1 to the second insulated gate transistor 10-2 at address (m+1.n+1), and (ml n +
1) Third insulated gate transistor 10- at address
3 constitutes a closed loop having a common drain with the fourth insulated gate transistor 10-4 at address (m+2.n) q via the connection line 2o-2. Therefore,
The first
The quality of the insulated gate transistor 10-1 and the second insulated gate transistor 10-2 is determined, and the two scanning lines 11 (m) and 11 (m+2) and the two signal lines 12 (n) are determined. and 12(n+1) to determine the quality of the third insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, thereby determining the quality of a total of four insulated gate transistors. can be done independently. The pattern layout diagram corresponding to FIG. 15 is somewhat complicated and will therefore be omitted.

According to the circuit configuration of FIG. 16, the first insulated gate transistor 10-1 at address (m, n) is connected to the connection line 20-
1, the second insulated gate transistor 10-2 at address (m+1.n+1) and the third insulated gate transistor 10-3 at address (m, n+2) are connected to connection line 2.
0-2 and the fourth insulated gate transistor 10-4 at address (m+1rn), forming a closed loop having a common drain. Therefore,
The first
The quality of the insulated gate transistor 10-1 and the second insulated gate transistor 10-2 is determined, and the two scanning lines 11 (m) and 11 (m+1) and the two signal lines 12 (n) are determined. and 12(n+2) to determine the quality of the third insulated gate transistor 10-3 and the fourth insulated gate transistor 10-4, thereby determining the quality of a total of four absolute gate transistors. can be done independently. The pattern layout diagram corresponding to FIG. 16 is also somewhat complicated and will therefore be omitted.

As a ninth embodiment, if the four sets of structural units are divided into two and two sets are placed diagonally at each intersection of the scanning line and the signal line, two insulated gate transistors form a closed loop in series. There are two types of circuit configurations, which will be explained as embodiments using the drawings from FIG. 17 to FIG. 18.

According to the circuit configuration of FIG. 17(a), (m, n)
The first insulated gate transistor 10-1 at the address (m+1.n+1) connects to the second insulated gate transistor 10-2 at the address (rrb
n) Third insulated gate transistor 10-3 at address
form a closed loop having a common drain with the fourth insulated gate transistor 10-4 at address (m+1.n+2) via the connection line 20-2. Therefore, two scan lines 11(m) and 11(m+1) and 2
The quality of the first insulated gate transistor 10-1 and the second insulated gate transistor 10-2 is determined using the main signal lines 12(n) and 12(n+1), and the two scanning lines 11(m) and 11(m+1) and two signal lines 12(n) and 12(n+2), the third insulated gate transistor 10-3 and the fourth insulated gate transistor 10 By performing the pass/fail judgment of -4, it is possible to independently judge the pass/fail of a total of four insulated gate transistors. A pattern layout diagram corresponding to FIG. 17(a) is shown in FIG. 17(b). Connection line 20-
1 is composed of a connection pattern 25-1 made of Cr and a connection pattern 34-1, 34-2 made of AI, and the connection line 20
-2 is composed of a connection pattern 25-2 made of Cr and a connection pattern 34-3, 34-4 made of AI.
Multilayer wiring is possible at the intersection of the connection line 20-2 and the signal line 12, and the connection line 20 is
If the parts are separated, secondary defects will not occur.

According to the circuit configuration of FIG. 18(a), (m+n)
The first insulated gate transistor 10-1 at address (m + 11 n + 1
) a second insulated gate transistor 10-2 at address 10-2;
Further, the third insulated gate transistor 10-3 at address (rrb n) is connected to (m+2.
the fourth insulated gate transistor 10- at address n+1)
4, forming a closed loop with a common drain. Therefore, the two scanning lines 11(m) and 11(m+
1), and two signal lines 12(n) and 12(n+1)
The first insulated gate transistor 10-1
The quality of the second insulated gate transistor 10-2 is determined, and the two scanning lines 11(m) and 11(m+2),
A third insulated gate transistor 10-3 and a fourth insulated gate transistor 10-3 and a fourth
By determining the quality of the insulated gate transistors 10-4, it is possible to independently determine the quality of a total of four insulated gate transistors. A pattern layout diagram corresponding to FIG. 18(a) is shown in FIG. 18(b). The connection line 20-1 has a connection pattern 25- made of Cr.
The connection pattern 34-L 34-2 is made of 1 and AI, and the connection line 20-2 is the connection pattern 2 made of Cr.
5-2. Connection pattern 34-3 consisting of 25-3 and At
．． If configured with 34-4.34-5, the connecting wire 20-
2 and the scanning line 11, multi-layer wiring is possible at the intersection between the connection lines 20-1 and 20-3 through the openings 21-1 to 21-3 formed in the connection patterns 25-1 to 25-3.
If 2 is separated, secondary defects will not occur.

As already explained, in the pass/fail judgment that connects two insulated gate transistors in series and performs the pass/fail judgment at the same time, it is possible to determine which side a large OFF current or a short circuit between the source and drain occurs as a defective insulated gate transistor. However, regarding the small ON current, it is impossible to distinguish which side it occurs on. In other words, normally
In the case of white display, since the address of a white spot defect is known, it is possible to convert it into a black spot defect by laser trimming, but the black spot defect cannot be corrected or corrected. However, in the sixth to eighth embodiments, there are four sets of structural units each consisting of an insulated gate transistor and a picture element electrode, so in the case of normally white display, the effect of improving black spot defects is significantly increased. Normally, there is no need to correct sunspot defects.

When testing the electrical characteristics of the driving insulated gate transistor, an auxiliary insulated gate transistor is introduced and one insulated gate transistor is tested twice, in the same way as in the first embodiment. Characteristic defects of all insulated gate transistors can be identified. This concept is the third point of the present invention, and since the purpose is to alleviate and correct or correct point defects, it is meaningless unless there are two or more insulated gate transistors for driving. We will devise a circuit configuration.

As already shown in the second to fifth embodiments, when there are two sets of structural units each consisting of an insulated gate transistor for driving and a picture element electrode, there is a method for arranging the structural units within the display area. There are four types, and the tenth to first and third embodiments will be explained below.

As a tenth embodiment, when a set of structural units is arranged diagonally at each intersection of a scanning line and a signal line, two insulated gate transistors and an auxiliary insulated gate transistor form a closed loop in series. Among such circuit configurations, the simplest one will be described as an embodiment with reference to FIG.

According to the circuit configuration of FIG. 19(a), (m, n)
The first insulated gate transistor 10-1 at the address (m+1.n+1) connects to the auxiliary insulated gate transistor 40 at the address (m+2.n+) via the connection line 20-1.
2) The second insulated gate transistor 10-2 at the address forms a closed loop with the auxiliary insulated gate transistor 40 via the connection line 20-2, each having a common drain. Therefore, two scanning lines 11 (m
) and 11(m+1), and two signal lines 12(n) and 12(n+1), the first insulated gate transistor 10-12 and the auxiliary insulated gate transistor 4
0 pass/fail judgment is performed, and two scanning lines 11(m+1) and 1
1 (m+2) and two signal lines 12 (n+1) and 12 (n+2), the second insulated gate transistor 10-2 and the auxiliary insulated gate transistor 40
By making a pass/fail decision for a total of three insulated gate transistors, it is possible to independently make a pass/fail decision for a total of three insulated gate transistors.

In determining the quality of the insulated gate transistor, the auxiliary insulated gate transistor 40 is tested twice, so it can contribute as a common factor to the evaluation of the electrical characteristics of the driving insulated gate transistor. The ON current of an insulated gate transistor is small (including the source-drain open circuit) and the O
If we follow the assumption that the probability that major defects such as large FF current (including short circuits between source and drain) will occur adjacently or in close proximity is almost 0, then for example, if the first insulated gate transistor and the auxiliary insulated gate O in any insulated gate type transistor in the combination of seven type transistors
When a low N current occurs, if the combination of the second insulated gate transistor and the auxiliary insulated gate transistor is normal, it is assumed that a low ON current has occurred in the first insulated gate transistor. If this can be determined and a low ON current occurs in one of the insulated gate transistors in the latter combination, the probability that a low ON current occurs in the first and second insulated gate transistors at the same time is almost 0. From this assumption, it can be determined that a small ON current has occurred in the auxiliary insulated gate transistor.

In the circuit configuration of FIG. 19(a), if accuracy is to be ensured, two scanning lines 11(m) and 11(m+2) and two signal lines 12(n) and 12(n+2) are make use of,
If the first insulated gate transistor 10-1 and the second insulated gate transistor 10-2 are additionally tested, all three insulated gate transistors will be tested twice. ON1 for auxiliary insulated gate transistor! ! Even if a small problem occurs, the first and second
In other words, it is possible to completely determine the quality of the drive insulated gate transistor. However, there is an undeniable drawback that the number of inspections for pass/fail determination increases and the inspection time becomes longer.

A pattern layout diagram corresponding to FIG. 19(a) is shown in FIG.
Shown in b). The connection line 20-1 is made up of a connection pattern 25-1 made of Cr and a connection pattern 734-1 made of AI, and the connection line 20-2 is made up of a connection pattern 25-1 made of Cr.
2.25-3 and the connection pattern 34-2 consisting of AI, the connection line 20-1 and the connection line 20-2, the connection line 20-1 and the signal line 12, and the connection line 20-2. Multilayer wiring is possible at the intersection with the scanning line 11, and the auxiliary insulated gate transistor has a connection pattern 25-2, 25-4 made of Cr and a connection pattern 34- made of AI.
3 to configure the circuit, and connect the connection patterns 25-1 to 25.
-4, the connection line 20 is separated by the openings 21-1 to 21-6 formed in the openings 21-1 to 21-6, and the auxiliary insulated gate transistor is disconnected from the scanning line and the signal line. It will be understood that even if an insulated gate transistor is short-circuited to a scanning line or a signal line, no secondary failure will occur in the end.

As an eleventh embodiment, when one set of structural units is placed on each side of the scanning line, a circuit configuration in which two insulated gate transistors and an auxiliary insulated gate transistor form a closed loop in series. , the easiest one is number 20
This will be explained as an embodiment using figures.

According to the circuit configuration shown in FIG. 20(a), N (m, n
) The first insulated gate transistor 10-1 at the address (m+2+n+1) is connected via the connection line 20-1.20-2.
An insulated gate transistor 40 auxiliary to the address, and (
The second insulated gate transistor 10-2 at address m+Ln) forms a closed loop with the auxiliary insulated gate transistor 40 via the connection line 20-2, each having a common drain. Therefore, by using two scanning lines 11(m) and 11(m+2) and two signal lines 12(n) and 12(n+1),
The quality of the insulated gate transistor 10-1 and the auxiliary insulated gate transistor 40 are determined, and the two scanning lines 11 (m+1) and 11 (m+2) and the two signal lines 12 (n) and 12 ( n+1) to determine the quality of the second insulated gate transistor 10-2 and the auxiliary insulated gate transistor 40, thereby making it possible to independently determine the quality of a total of three insulated gate transistors. It can be done.

In the circuit configuration shown in FIG. 20(a), the first and second insulated gate transistors do not form a closed loop in series, so complete pass/fail judgment cannot be made as in the tenth embodiment, but this has already been emphasized many times. As shown in FIG. 2, as long as the probability that defects occur adjacently or very close to each other in the ON/OFF current of an insulated gate transistor is approximately 0, it is possible to make a pass/fail determination without any problem.

A pattern layout diagram corresponding to FIG. 20(a) is shown in FIG.
Shown in b). The connection line 20-1 has a connection pattern 25-1 made of Cr and a connection pattern 34-1.34 made of AI.
-2, the connection wire 20-2 is composed of a connection pattern 25-2 and 25-3 made of Cr and a connection pattern 3 made of AI.
4-3.34-4 allows multilayer wiring at the intersection of the connection line 20-2 and the scanning line 11,
The auxiliary insulated gate transistor 40 has a circuit configured with a connection pattern 25-4 made of Cr and source/drain wiring 34-5, 34-6 made of AI, and is formed in connection patterns 25-1 to 25-4. opening 21-1~
If the connection line 20 was separated by 21-4 and the auxiliary insulated gate transistor was disconnected from the signal line, the auxiliary insulated gate transistor would have been shorted to the scanning line and the signal line. Even so, no secondary defects occur.

As a twelfth embodiment, when one set of structural units is placed on both sides of a signal line, the most According to the circuit configuration of FIG. 21(a), which is explained as a simple embodiment in FIG. 21, the first insulated gate transistor 10-1 at address (m, n) Via (m+1.
The auxiliary insulated gate transistor 40 at address n+1) and the second insulated gate transistor 10-2 at address (m-Ln+2) are connected to the auxiliary insulated gate transistor 40 via the connection line 20-2. A transistor 40;
They each form a closed loop with a common drain. Therefore, two scanning lines 11(m) and 11(m+1),
The quality of the first insulated gate transistor 10-1 and the auxiliary insulated gate transistor 40 is determined using the two signal lines 12(n) and 12(n+1).
Book scanning lines 11(m-1) and 11(m+1), and 2
By using the main signal lines 12 (n+1) and 12 (n+2) to determine the quality of the second insulated gate transistor 10-2 and the auxiliary insulated gate transistor 40, a total of three insulated gate transistors It is possible to independently determine whether the transistor is good or bad.

In the circuit configuration of FIG. 21(a), the first and second insulated gate transistors form a closed loop in series, and are controlled ON/OFF separately by two scanning lines. If we add the pass/fail judgment of the combination of type transistor 10-1 and second insulated gate type transistor 10-2, all three insulated gate type transistors will be inspected twice, and the auxiliary Even when a small ON current occurs in an insulated gate transistor, a complete determination of the quality of the first and second, ie, driving insulated gate transistors can be performed.

A pattern layout diagram corresponding to FIG. 21(a) is shown in FIG.
Shown in b). The connection line 20-1 has a connection pattern 25-1 made of Cr and a connection pattern 34-1.34 made of AI.
-2, the connection wire 20-2 is composed of a connection pattern 25-2 and 25-3 made of Cr and a connection pattern 3 made of AI.
By configuring 4-3.34-4, multilayer wiring is possible at the intersections between the connection line 20-1 and the connection line 20-2, and between the connection line 20-2 and the scanning line 11 and the signal line 12. , the auxiliary insulated gate transistor 40 has a connection pattern 25-4 made of Cr and a connection pattern 34-2 made of AI.
．． Configure the circuit with 34-5, and connect the connection pattern 25-
If the connecting line 20 is separated by the openings 21-1 to 21-7 formed in the openings 1 to 25-4 and the auxiliary insulated gate transistor is disconnected from the signal line, the auxiliary insulated gate transistor can be disconnected from the signal line. Even if an insulated gate transistor is short-circuited to a scanning line or signal line, no secondary defects will occur.

As a thirteenth embodiment, when two sets of structural units are arranged on each side of the signal line, the most Two simple types are devised and explained as embodiments in FIGS. 22 and 23.

According to the circuit configuration of FIG. 22(a), (m+n)
The first insulated gate transistor 10-1 at the address is connected to the auxiliary insulated gate transistor 40 at the address (m+2°n+1) via the connection line 20-1.
+1. n) second insulated gate transistor 10 at address
-2 forms a closed loop with an auxiliary insulated gate transistor 40 via a connection line 20-2, each having a common drain. Therefore, two scanning lines 11
(m) and 11 (m+2), and two signal lines 12 (
n) and 12(n+1), the quality of the first insulated gate transistor 1o-1 and the auxiliary insulated gate transistor 40 is determined, and the two scanning lines 11(m+1)
and 11 (m+2), and two signal lines 12(n) and 12(n+1), the second insulated gate transistor 10-2 and the auxiliary insulated gate transistor 40
By making a pass/fail decision for a total of three insulated gate transistors, it is possible to independently make a pass/fail decision for a total of three insulated gate transistors.

In the circuit configuration of FIG. 22(a), since the first and second insulated gate transistors cannot form a closed loop in series, the accuracy regarding the quality determination of the insulated gate transistors is equivalent to that of the eleventh embodiment. be.

A pattern layout diagram corresponding to FIG. 22(a) is shown in FIG.
Shown in b). The connection line 20-1 has a connection pattern 25-1.25-2 made of Cr and a connection pattern 34 made of AI.
-1.34-2, the connection line 20-2 is a connection pattern 25-3 made of Cr and a connection pattern 3 made of AI.
4-3.34-4 allows multilayer wiring at the intersection of the connection line 20-1 and the scanning line 11,
The auxiliary insulated gate transistor 40 has a connection pattern 25-4 made of Cr and a connection pattern 34-4 made of AI.
4. Configuring the circuit in 34-5 and connecting pattern 25
Openings 21-1 to 21-4 formed in -1 to 25-3
By separating the connection line 20 and disconnecting the auxiliary insulated gate transistor 40 from the scanning line and signal line, it is possible to prevent the auxiliary insulated gate transistor from shorting with the scanning line or signal line. Even if this happens, no secondary defects will occur.

According to the circuit configuration of FIG. 23(a), the first insulated gate transistor 10-1 at the address (m, n) is connected to the address (m + Ln+2) via the connection line 20-1, 20-2. auxiliary insulated gate transistor 40, and (m
, n+1) second insulated gate transistor 10 at address
-2 forms a closed loop with an auxiliary insulated gate transistor 40 via a connection line 20-2, each having a common drain. Therefore, two scanning lines 11
(m) and 11 (m+1), and two signal lines 12 (n
) and 12 (n+2) are used to determine the quality of the first insulated gate transistor 10-1 and the auxiliary insulated gate transistor 40, and the two scanning lines 11 (m) and 11 (m+1), The second insulated gate transistor 10-2 and the auxiliary insulated gate transistor 4 are connected using the two signal lines 12(n+1) and 12(n+2).
By performing the pass/fail judgment of 0, it is possible to independently judge the pass/fail of a total of three insulated gate transistors.

In the circuit configuration of FIG. 23(a), the first and second insulated gate transistors form a closed loop in series via connection lines 20-1 and 20-2, but one common Since the scanning lines are simultaneously controlled by 0N10FF, the defect of low ON current occurs in the first and second lines.

Although it cannot be identified by testing the combination of insulated gate transistors, the auxiliary insulated gate transistor and the first
Taking into consideration the test results obtained by combining the first insulated gate transistor and the second insulated gate transistor, the accuracy regarding the quality determination of the insulated gate transistor is such that there is no problem in practical use.

The pattern layout diagram corresponding to FIG. 23(a) is shown in FIG.
Shown in b). The connection line 20-1 has a connection pattern 25-1 made of Cr and a connection pattern 34-1.34 made of AI.
-2, and the connection line 20-2 is connected to the connection pattern 25-1.
If the connection pattern 34-3 is made of a part of Cr and AI, multilayer wiring is possible at the intersection of the connection line 20-1 and the signal line 12, and the auxiliary insulated gate transistor 40 is made of Cr. A circuit is constituted by the connection pattern 25-2 made of 25-2 and the connection pattern 34-2, 34-4 made of AI, and the openings 21-1 to 21-4 formed in the connection pattern 25-1. If the connection line 20 is separated and the auxiliary insulated gate transistor 40 is disconnected from the signal line, even if the auxiliary insulated gate transistor is short-circuited to the scanning line or signal line, it will not be possible to No further defects will occur.

Above, we have explained the circuit configuration for electrically testing two insulated gate transistors for driving using an auxiliary insulated gate transistor, but it is also possible to prepare four sets of structural units or introduce an auxiliary insulated gate transistor. As a result, the number of connection lines increases and becomes longer, the size of the pixel electrodes that contribute to display becomes smaller, the aperture ratio decreases, and the brightness of the display screen becomes darker. As is clear from the comparison with the pattern layout diagram, the effects of further promoting the relaxation of sunspot defects and detecting even defects with low ON current are extremely unique features of the present invention. Furthermore, two insulated gate transistors can be independently connected to each other without introducing an auxiliary insulated gate transistor.
There are several circuit configurations that can be used for electrical inspection, and the simplest one is the 14th embodiment, which uses a set of insulated gate transistors and pixel electrodes that are driven by the same scanning line and signal line. A second active matrix substrate having two sets of units at diagonal positions at each intersection of the scanning line and the signal line is provided.
4, in the 15th embodiment, a set of structural units consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are connected to each other at each intersection of the scanning line and the signal line. A second active matrix substrate with two sets on both sides of the line
This will be explained using Figure 5.

According to the circuit configuration of FIG. 24(a), (m, n)
The first insulated gate transistor 10-1 at the address is connected to the second insulated gate transistor 10-2 at the address (m+1.n+2) via the connection line 20-1, and the second insulated gate transistor 10-2 is connected to the connection line 20-1.
-2, and the second insulated gate transistor 10-2 at the same address ((m+2, n+1), forming a closed loop in which the drains are common. Therefore, first, the two scanning lines 11 ( m) and 11 (m+1), and two signal lines 12(n) and 12(n+2),
The first insulated gate transistor 10-1 and (m+1.
n+2) second insulated gate transistor 10-
2, and then the two scanning lines 11 (m) and 11 (m+2) and the two signal lines 12 (n) and 1
2(n+1) to determine the quality of the first insulated gate transistor 10-1 and the second insulated gate transistor 10-2 at address (m+2.n+1). The gated transistor will be inspected twice in succession. In this way, by performing the 0N10FF test on each of the first and second insulated gate transistors twice in succession, it is possible to determine the quality of all the insulated gate transistors.

A pattern layout diagram corresponding to FIG. 24(a) is shown in FIG.
Shown in b). The connection line 20-1 has connection patterns 25-1 and 25-2 made of Cr and a connection pattern 34 made of AI.
-1, and the connecting wire 20-2 is 25-2 made of Cr.
．． Connection patterns 34-1 to 34 consisting of 25-3 and AI
-3, the connection line 20-1 and the connection line 20-
2. Connection line 20-1, signal line 12 and connection line 20-2
Multi-layer wiring is possible at the intersection of the scanning line 11 and the scanning line 11, and the connection line 20 is separated by the openings 21-1 to 21-6 formed in the connection patterns 25-1 to 25-3. If so, no secondary defects will occur.

According to the circuit configuration of FIG. 25(a), the first insulated gate transistor 10-1 at address (m, n) is connected to the second insulated gate transistor at address (m+1.n+1) via the connection line 20-1. Insulated gate transistor 10-2 and connection line 20-
2 and a second insulated gate transistor 10-2 at the same address <(m-1, n+2), forming a closed loop having a common drain. Therefore, first 2
The first
Insulated gate transistor 10-1 and (m+1.n+
1) Check the quality of the second insulated gate transistor 10-2 at the address, and then connect the two scanning lines 11 (m-1) and 11 (m) and the two signal lines 12 (n). and 12
(n+2) to determine the quality of the first insulated gate transistor 10-1 and the second insulated gate transistor 10-2 at address (m-1, n+2). The insulated gate transistor will be tested twice in a row. In this way, by performing the 0N10FF test on each of the first and second insulated gate transistors twice in succession, it is possible to determine the quality of all the insulated gate transistors.

A pattern layout diagram corresponding to FIG. 25(a) is shown in FIG.
Shown in b). The connection line 20-1 has connection patterns 25-1 and 25-2 made of Cr and a connection pattern 34 made of AI.
-1.34-2, the connection wire 20-2 is made of Cr and the connection pattern 34 is made of 25-3.25-4 and Al.
-3.34-4, multiple layers can be formed at the intersections of the connection line 20-1 and the connection line 20-2, the connection line 20-1 and the scanning line 11, and the connection line 20-2 and the signal line 12. If wiring is possible and the connection wires 20 are separated by the openings 21-1 to 21-5 formed in the connection patterns 25-1 to 25-4, secondary defects will not occur. .

As described above, one set, two sets, and four sets of structural units each consisting of an insulated gate transistor for driving and a picture element electrode are arranged in the display area.
In the active matrix substrate that has the integrated circuit, connection lines are arranged between the insulated gate transistors or between the pixel electrodes connected to the insulated gate transistors and between the signal lines so that the insulated gate transistors form a closed loop. , a method for manufacturing an active matrix substrate has been described in which after externally inspecting various characteristics such as electrical characteristics and internal short circuits of an insulated gate transistor, the connection is released and the process proceeds to a panel assembly process. As a result,
In the stage before panel construction, the main causes of point defects are low ON current (open source and drain) and OFF current short circuit between source and drain of insulated gate transistors, which are the main causes of point defects.
Since the presence of the phosphor can be recognized and identified, its industrial value is extremely high, especially in large-area display devices, where yields are decreasing at an accelerating rate. Since the OFF current becomes a white dot defect in a normally white display, it is converted into a black dot defect by cutting off the insulated gate transistor from the signal line or scanning line using a cutting means such as a laser and losing its display ability. The improvement effect is evaluated as the complete elimination of white spot defects. Regarding the low ON current, by providing a plurality of picture element electrodes within the display area, there will be no problem at all with normal video display.

Further improvements were made to completely eliminate black spot defects, and this invention was originally intended to give normal display capability to white spot defects, which had been converted into black spot defects and lost their display capability.
This will be explained as a 16th embodiment. Further, an invention that provides normal display ability to black spot defects will be described as a seventeenth embodiment.

In the 16th embodiment, when manufacturing the active matrix substrate, a manufacturing method is adopted in which the substrate is manufactured by removing only the picture element electrodes, and the picture element electrodes are formed after the electrical inspection of the insulated gate transistor is completed. This is because in order to collect information on poor characteristics and internal short circuits of the drive insulated gate transistor, which are the main causes of point defects (in the example, the pattern layout diagram used as part of the connection line is also This is because pixel electrodes are not always necessary (although shown); in order to be able to correct or correct point defects, a plurality of constituent units are required within the display area, and the formed picture Since it is not permitted for elementary electrodes to be located on constituent elements such as scanning lines, signal lines, or insulated gate transistors to increase parasitic capacitance or cause short circuits, applicable circuit configurations are within the scope of the claims. It is limited to what is described in Sections 8, 11, 13, 15, and 18. In both of these, two constituent units each consisting of a picture element electrode and an insulated gate transistor are arranged side by side, and constituent elements such as scanning lines, signal lines, or insulated gate transistors are arranged between the picture element electrodes. not exist. Therefore, it is possible to separate the OFF current edge gate type transistor from the normal circuit configuration and drive one picture element electrode having a size corresponding to two picture element electrodes with one normal insulated gate type transistor. In this sense, it is necessary to design the transistor in advance so as to have a surplus of current drive capacity, and this can be said to be an essential design item, especially when the number of insulated gate type transistors is two. The current drive capability of an insulated gate transistor depends on the channel width (
It is known that it is determined by the ratio of W) to length (L), W/L.

There are two methods to avoid connection between one shared picture element electrode and a defective insulated gate transistor having an internal short circuit between the OFFFF current.

The first method is to use a positive-type photosensitive resin for pattern formation in the photolithography process for forming picture element electrodes, and perform spot exposure based on electrical inspection data. In a defective insulated gate transistor, a part of the picture element electrode is removed so that there is no electrical contact between them.

Although this method involves the inconvenience of transferring the electrical test results of the insulated gate transistor to the photolithography process,
It has the advantage of not causing secondary defects.

The second method is to remove the drain or drain wiring using a cutting means such as a laser when the picture element electrode is formed so that the defective insulated gate transistor is not connected to the picture element electrode. Alternatively, it is possible to remove the connection between the defective insulated gate transistor and the scanning line or signal line using the same laser, which can be done at the same time as the electrical inspection of the insulated gate transistor. However, cutting by laser irradiation has the drawback that there is a risk that conductive material scattered on the substrate may re-adhere and cause secondary defects.

Regarding the specific method of forming the pixel electrode after forming the insulated gate transistor, the structures and manufacturing methods of insulated gate transistors are diverse, and it is not possible to cover all the methods, so the points to be considered in particular are as follows. I will write it down.

These are as follows: 1) It does not cause damage to the transistor characteristics of the insulated gate transistor that cannot be recovered by heat treatment, and 2) The drain electrode or drain wiring of the insulated gate transistor, as well as the wiring layer that requires connection. maintain ohmic contact with
3) Avoid changing the film thickness or film quality of other conductive layers or insulating layers.Industrially, forming the pixel electrode after forming the insulated gate transistor or star reduces the need for new manufacturing processes. It is important to take care to avoid high costs due to the need to introduce special manufacturing machinery.

As a seventeenth embodiment, a method for providing normal display ability to a black spot defect will be described. In a structural unit consisting of a picture element electrode and an insulated gate transistor for driving, if the insulated gate transistor has a low ON current or an open source/drain failure, a normal structure in the neighboring structural unit will be detected. If a drive current can be supplied from an insulated gate transistor, black spot defects can be corrected. For this purpose, it is necessary to design the transistor in advance so as to have a surplus current drive capacity, as in the 16th embodiment. ON? I! The circuit configuration that can identify the location of the defective flow or source-drain open is described in claims 17 to 33, but the active matrix (IJ) substrate proposed in the present invention In the configuration, there is no insulating layer on the signal line, and the formed pixel electrode is located on the scanning line, signal line, or component such as an insulated gate transistor, increasing parasitic capacitance or causing short circuits. Therefore, applicable pattern configurations are limited to those described in claim 19. In both of these, two constituent units each consisting of a picture element electrode and an insulated gate transistor are arranged side by side, and constituent elements such as scanning lines, signal lines, or insulated gate transistors are arranged between the picture element electrodes. That's because it doesn't exist. The drain electrode of an insulated gate transistor with poor characteristics (low ON current) or the pixel electrode connected to the relevant insulated gate transistor, and the drain electrode of a normal insulated gate transistor or the pixel electrode connected to the relevant insulated gate transistor. In order to connect the picture element electrodes with a small conductive pattern, for example, a laser spot debonition device L manufactured by Micurion Co., Ltd. in the United States, sold by Tokyo Electron Ltd.
-ID can be mentioned. This device irradiates a laser onto a substrate while flowing an organic metal gas under a reduced pressure of several tens of Torr, thereby forming a small conductive pattern with a pattern width of several to several tens of micrometers in a width of just 0.00 m. 1-0. 1μm with 2μm film thickness
It can be deposited with good coverage on a substrate having a step difference. If the connection is made using such a small pattern, the parasitic capacitance that occurs between the small pattern and the scanning line or signal line will not interfere with image display if there is an insulating layer on the scanning line and the signal line. It should be noted that since the size of the circuit is small, it can be adopted in all of the circuit configurations described in claims 17 to 20.

When an auxiliary capacitor is introduced, intersections between the common line of the auxiliary capacitor and the connection line between insulated gate transistors and signal lines and between insulated gate transistors will inevitably occur, and short circuits will occur at the intersections. It is clear that the probability of occurrence is not zero, so in order to simplify understanding, an active matrix substrate without an auxiliary capacitor is described in the embodiment. However, since the connecting lines are eventually separated or removed, there is no risk of increasing defects and lowering yield, and the effectiveness of the present invention is not impaired even in the case of active matrix organization with auxiliary capacitors. . However, it should be noted that a short circuit between the common line of the auxiliary capacitor and the connection line forms an extra current path, so it is inevitable that the number of electrical inspection items will increase. I'll omit it.

Here, let us summarize the arrangement of picture element electrodes when the active matrix substrate of the present invention is used in FIG. 26. Second
FIG. 6(a) is a layout diagram corresponding to the first embodiment, which is the same as the conventional layout, and there is one picture element electrode 14 at each intersection of the scanning line 11 and the signal line. Figure 26(b) shows the 2nd and 12th
This is a layout diagram corresponding to the fifteenth embodiment, in which two picture element electrodes 14-1 and 14-2 are present on both sides of the signal line at each intersection of the scanning line 11 and the signal line 12. Figure 26 (
C) is a layout diagram corresponding to the fourth, tenth, and fourteenth embodiments, in which two picture element electrodes 14-L and 14-2 are provided at diagonal positions at each intersection of the scanning line 11 and the signal line 12. exists. FIG. 26(d) is a layout diagram corresponding to the third and eleventh embodiments, in which two picture element electrodes 14-1. 14-2
exists. FIG. 26(e) is a layout diagram corresponding to the fifth and thirteenth embodiments, in which two picture element electrodes 14-1.1 are provided on one side of the signal line at each intersection of the scanning line 11 and the signal line 12.
4-2 exists. FIG. 26(1) is a layout diagram corresponding to the sixth embodiment, in which four picture element electrodes 14-1 to 14-1 are placed at all diagonal positions at each intersection of the scanning line 11 and the signal line 12.
14-4 exists one by one. FIG. 26(g) is a layout diagram corresponding to the ninth embodiment, in which four picture element electrodes 14-
There are two each of 1 to 14-4. Figure 26 (h)
is a layout diagram corresponding to the eighth embodiment, in which two of four picture element electrodes 14-1 to 14-4 are present on both sides of the scanning line at each intersection of the scanning line 11 and the signal line 12. There is. FIG. 26(i) is a layout diagram corresponding to the seventh embodiment, in which four picture element electrodes 14-1 to 14-4 are arranged on both sides of the signal line at each intersection of the scanning line 11 and the signal line 12. There are two of each.

As can be easily seen from Figure 26, there are a wide variety of arrangements when using a plurality of picture element electrodes, and for color display, the size of the dot (picture element electrode) and the resolution of color display (the resolution of the picture element electrode) It is desirable to select the optimal one by considering the degree of dispersion. In addition, in many embodiments, by shifting the unit picture elements by half a pitch every other row and arranging the RGB colored layers on the color filter in a delta (triangular) arrangement,
For circuit configurations that can secure apparent resolution even when the number of picture elements is small, it is natural that even if the connection destination of the connection line is changed and at the same time the combination of scanning line and signal line in electrical inspection is changed, It belongs to the scope of the present invention.

In addition, according to the gist of the present invention, there is no reason why the active matrix substrate is limited to a liquid crystal panel, and even a device having a light emitting element such as EL or SiC as an optical element can be applied. Furthermore, liquid crystal panels are not limited to the transmissive type as explained in the main text, but the invention is extremely useful for reflective type liquid crystal panels as well, if slight changes and changes in the manufacturing process related to the formation of picture element electrodes are allowed. I would like to add this.

Effects of the Invention As described above, the present invention first uses an active material (active material).
It becomes possible to estimate the occurrence of point defects before converting an IJ board into a liquid crystal panel, and it is possible to avoid the loss of wasteful use of expensive color filters. In addition, by combining the technology with multiple insulated gate transistors, the degree of freedom in mitigating point defects is greatly enhanced, and in its most advanced form, it is possible to obtain an active matrix substrate in which point defects do not occur in principle. In this way, the yield can be improved.

[Brief explanation of drawings]

This corresponds to the embodiments shown in FIGS. 1 to 25, and the first
Figures 3 to 16 and (a) in each figure are equivalent circuit diagrams of a liquid crystal panel or active matrix substrate, and (b) in each figure is an equivalent circuit diagram of a liquid crystal panel or active matrix substrate.
) is a pattern layout diagram corresponding to the equivalent circuit, Figure 1 (c
), (d) are cross-sectional views of the insulated gate transistor (on the line A-A'') and the connection line (on the line B-B') in FIG. A layout diagram of the elementary electrodes, FIG. 27 is a perspective view showing the mounting means on the liquid crystal panel,
FIG. 28 is an equivalent circuit diagram of a conventional active type liquid crystal panel, and FIGS. 29 and 30 are equivalent circuit diagrams of improved active type liquid crystal panels. 1. Liquid crystal panel, 2. Active (matrix) substrate, 3. Integrated circuit chip, 4. Connection film, 5.
6. Electrode terminals (groups) for signal lines and scanning lines, 9. Color filters, 10. Insulated gate transistors, 11.
(8)...Scanning line, 12 (7)...Signal line, 13...Liquid crystal cell, 14...Picture element electrode, 16...Storage capacitor, 20...
・Connection line, 21... Opening, 22... Source wiring, 23
...Drain wiring, 25...(Cr) connection pattern,
26.27...Opening, 28...Signal line branch, 29
... Insulating layer, 30... Amorphous silicon layer, 31... Amorphous silicon layer (containing impurities), 32... Gate insulating layer, 33... Insulating layer (for etching stopper), 34...
・(AI) connection pattern, 40...auxiliary insulation gate...
type transistor. Name of agent Patent attorney Shigetaka Awano Name of engineer Figure 1 Figure 1 "15 Figure Figure (C) <d) Figure Z/2 (72) /2 (Ilsu l) /2 (71 2) (a) Figure /z (72) Figure (b 12 (7L+1) Figure 2 (η) /2 (72+1) 2 in 12) (a) /2 (3 in n ) Person-15 Figure Figure /2 (72) (b) 12 (yl*i) <b) Figure 12 (71 n/2 (1 in n) /2 (πf2 n<a> Figure /2 (72) 12 (ηtυ /2 (η inside 2) tz<nsu3) (a An Figure / 2 (η) Figure 12 (Tochu! N Cb) (b) Figure / 2 (π) / 2(π10l) /2(ηri) (a) Funeral figure 72(yzn12(72suυ A?(n+2)) (L2) Figure/2(72) Figure 1012(π) /2 (72s1) Cb) 12(n+υ (bn Figure 10 Figure 1 1 Figure 12(η)) (d) 12(ηt!) 12(n+2) all 1 Figure f2 (η Figure 2 Figure 2/2(n ya ln (bn kuku 1 2 Fig. 12 (n) Fig. 13/2 (72) /2 (sword 1) /2 (7I◆22 /2 (nφ12 12 (n-2+ Fig. 1 4/2) (ηn72(n+t) Fig.15h!(72) Fig.1712(η+ri12(72s2)) Fig.17(bn(b) Fig.17/2(72)/2 (Sword 10l) /2 (η + 2n (<2) f2 (1 out of n) 12 (2 out of n) Fig. 19 Fig. 20 (b) Cb) Fig. 20] Fig. 21 / 2 (sword) (4 12 (n◆/) ノ2 (nQI (a) Figure 21 Figure 22 (b) Cb) Figure 22 Figure 23 (a> (a) Figure 23 Figure Cb) (b) Figure 24 Ka 25 Cause (a> (cL) Fig. 25 Fig. 26 <b> (C) (d) Fig. 26 Fig. 26 (b) (Tomoe) Bi) Fig. 26 Fig. 27 (L) m-1 liquid crystal Panel 11 - Active board 1 - Kirin chinoboo - Confucian 1 sales cycle moo - Sword - fill Figure 26 Figure 28 <1> Line 111 Trouble Cell/2 Figure 29 10-7.-2 11, tso you gate type transistor/2, jIs Procedural amendment is the formula) Display of the case 1999 Patent No. 86227 Invention Person correcting name

Claims (26)

[Claims] (1) In an active matrix substrate that has a set of insulated gate transistors and pixel electrodes at each intersection of a scanning line and a signal line (nth), the drain of the nth insulated gate transistor is connected using a removable wiring material. The electrode or pixel electrode is connected to the adjacent signal line n+1, and a voltage is applied between the signal lines n and n+2 to connect the two insulated gate transistors n and n+1 in series. 1. A method for manufacturing an active matrix substrate capable of detecting point defects, characterized in that the connection is released after electrical characteristics are inspected. (2) A set of structural units consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line (m number) and signal line (n number) are arranged at each intersection of the scanning line and the signal line. In an active matrix substrate with two sets of signal lines on both sides,
Two insulated gate transistors are formed by being connected by a removable wiring material so as to be configured in series, and the connection is released after an electrical test of the insulated gate transistors is completed;
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that an insulated gate transistor with poor characteristics (large OFF current) is disconnected from a picture element electrode. (3) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and the second insulated gate transistor at address (m, n+1), (m, n+2) or (m+1, n+1) The drain electrode or the pixel electrode of the insulated gate transistor is connected with a removable wiring material, and a voltage is applied between the signal lines n and n+1, between the n and n+2, or n+1, 3. The method of manufacturing an active matrix substrate capable of detecting point defects according to claim 2, wherein the connection is released after the electrical characteristics of the first insulated gate transistor and the second insulated gate transistor are connected in series. (4) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided on both sides of the scanning line at each intersection of the scanning line and the signal line. In the active matrix substrate, the drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and the drain electrode or picture element electrode of the second insulated gate transistor at address (m+1, n+1) are connected. A voltage is applied between the n-th and n+1-th signal lines, the first and second insulated gate transistors are connected in series, and the electrical characteristics of the connections are inspected. A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that the connection between an insulated gate transistor with poor characteristics (large OFF current) and a picture element electrode is disconnected. (5) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided at diagonal positions at each intersection of the scanning line and the signal line. In an active matrix substrate, two insulated gate transistors are connected in series by a removable wiring material. A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that a connection between an insulated gate transistor (with a large current) and a pixel electrode is disconnected. (6) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and (m+1, n+1)
address, (m+1, n+2) address or (m+2, n+1
) is formed by connecting the drain electrode or picture element electrode of the second insulated gate transistor at the address with a removable wiring material, and the signal of number n and number n+1, number n and number n+2, or number n and number n+1 is formed. 6. Detection of point defects according to claim 5, wherein the connection is released after a voltage is applied between the lines and the first and second insulated gate transistors are connected in series and their electrical characteristics are inspected. and a method for manufacturing a repairable active matrix substrate. (7) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided on one side of the signal line at each intersection of the scanning line and the signal line. In an active matrix substrate, two insulated gate transistors are connected in series by a removable wiring material.
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that a connection between an insulated gate transistor (with a large current) and a pixel electrode is disconnected. (8) The drain electrode or pixel electrode of the first insulated gate transistor at address (m, n) and the drain electrode or pixel electrode of the second insulated gate transistor at address (m, n+1) can be removed. A voltage is applied between the nth and n+1 signal lines, the first and second insulated gate transistors are connected in series, and the electrical characteristics are inspected, and then the connection is released. 8. The method of manufacturing an active matrix substrate capable of detecting point defects according to claim 7, wherein: (9) A set of structural units consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are placed at all diagonal positions at each intersection of the scanning line and the signal line. In an active matrix substrate having four sets, two of the four insulated gate transistors are connected in series with a removable wiring material, and after the electrical inspection of the insulated gate transistors is completed, the connections are Cancellation and
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that an insulated gate transistor with poor characteristics (large OFF current) is disconnected from a picture element electrode. (10) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and (m+1, n+1
) address (m+1, n) or (m,
The drain electrode or picture element electrode of the third insulated gate transistor at address (m, n+2) or the fourth insulated gate transistor at address (m+2, n) are removed. A voltage is applied between the nth and n+1 signal lines, the nth and n+2 signal lines, or between the nth and n+1 signal lines, and the first, second and third 10. The active matrix capable of detecting and repairing point defects according to claim 9, wherein the connection is released after two fourth insulated gate transistors are connected in series and their electrical characteristics are inspected. Substrate manufacturing method. (11) In an active matrix substrate that has two sets of structural units on each side of the signal line, each consisting of an insulated gate transistor and a pixel electrode that are driven by the same scanning line and signal line, four Two of the insulated gate transistors are connected in series with a removable wiring material, and after the electrical inspection of the insulated gate transistors is completed, the connection is canceled and the characteristics are defective (large OFF current).
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that the connection between an insulated gate transistor and a pixel electrode is disconnected. (12) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and (m+1, n+2)
) or the drain electrode or picture element electrode of the second insulated gate transistor at address (m+2, n+1);
The drain electrodes or picture element electrodes of the third insulated gate transistors at addresses (m, n) and the drain electrodes or picture element electrodes of the fourth insulated gate transistors at addresses (m+1, n+1) are made of removable wiring materials. connected and formed, n
Between the signal lines No. and n+2, and between the signal wires No. n and No. n+1, or n
A voltage is applied between the signal voltages of the first and second signals.
18. The point defect detection method according to claim 11, wherein the connection is released after two third and fourth insulated gate transistors are connected in series and their electrical characteristics are inspected. A method for manufacturing a repairable active matrix substrate. (13) In an active matrix substrate that has two sets of structural units on each side of the scanning line, each consisting of an insulated gate transistor and a pixel electrode that are driven by the same scanning line and signal line, four Two of the insulated gate transistors are connected in series with a removable wiring material, and after the electrical inspection of the insulated gate transistors is completed, the connection is canceled and the characteristics are defective (large OFF current).
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that the connection between an insulated gate transistor and a pixel electrode is disconnected. (14) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and (m+1, n+1
) and the drain electrode or picture element electrode of the second insulated gate transistor at address (m, n+1) or (m,
n+2) and the drain electrode or picture element electrode of the third insulated gate transistor at address (m+2, n) or (m+
The drain electrode or picture element electrode of the fourth insulated gate transistor at address 1, n) is connected to the pixel electrode using a removable wiring material, and between the signal line n and n+1, or between the signal line n and n+1, After a voltage is applied between the nth and n+2 signal lines and the first and second and third and fourth insulated gate transistors are connected in series, and their electrical characteristics are inspected, the connection is released. 14. The method of manufacturing an active matrix substrate capable of detecting and repairing point defects as claimed in claim 13. (15) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are placed diagonally at each intersection of the scanning line and the signal line. In an active matrix substrate having two insulated gate transistors, two of the four insulated gate transistors are connected in series by a removable wiring material, and the connection is released after the electrical inspection of the insulated gate transistors is completed. and,
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that an insulated gate transistor with poor characteristics (large OFF current) is disconnected from a picture element electrode. (16) The drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and (m+1, n+1
) and the drain electrode or picture element electrode of the second insulated gate transistor at address (m, n) and the drain electrode or picture element electrode of the third insulated gate transistor at address (m, n).
n
Between the signal lines No. and n+1 and No. n and No. n+2, or n
A voltage is applied between the signal voltages of the first and second signals.
16. The point defect detection and repair method according to claim 15, wherein the connection is released after the third and fourth insulated gate transistors are connected in series, two each, and their electrical characteristics are inspected. Possible active matrix substrate manufacturing method. (17) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided at diagonal positions at each intersection of the scanning line and the signal line. In an active matrix substrate both having auxiliary insulated gate transistors, a first insulated gate transistor at address (m, n) and an address (m+2, n+2),
The drain electrode or picture element electrode of the second insulated gate transistor at address (m+1, n) or (m-1, n+2) and the address (m+1, n+1), (m+2, m+1)
The address or the drain electrode of the auxiliary insulated gate transistor at address (m+1, n+1) is connected with a removable wiring material. A voltage was applied between the and n+1 signal lines, or between n and n+1 and n+1 and n+2 signal lines, and two insulated gate transistors, one for driving and one for auxiliary use, were connected in series and the electrical characteristics were tested. An active matrix substrate capable of detecting and repairing point defects, characterized in that the connection is subsequently released and the connection between the insulated gate transistor with poor characteristics (large OFF current) and the pixel electrode is released. Manufacturing method. (18) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided on one side of the signal line at each intersection of the scanning line and the signal line. In an active matrix substrate both having auxiliary insulated gate transistors, one of the two insulated gate transistors and the auxiliary insulated gate transistor are connected by a removable wiring material so as to be configured in series. After the electrical inspection of the insulated gate transistor is completed, the connection is removed and the characteristics are defective (large OFF current).
A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that the connection between an insulated gate transistor and a pixel electrode is disconnected. (19) The drain electrode or pixel electrode of the first insulated gate transistor at address (m, n) and the second insulated gate transistor at address (m+1, n) or (m+2, n+1) and (m+2, The drain electrode of the auxiliary insulated gate transistor at address n+1) is connected to the drain electrode of the auxiliary insulated gate transistor at address n+1 with a removable wiring material, and the signal line between n and n+1, or between n and n+2 and between n+1 and n+2 is formed. 18. The disconnection is performed after a voltage is applied between the lines and the two driving and auxiliary insulated gate transistors are connected in series and their electrical characteristics are inspected.
A method for manufacturing an active matrix substrate capable of detecting and repairing the described point defects. (20) Two sets of structural units each consisting of an insulated gate transistor and a pixel electrode driven by the same scanning line and signal line are provided at diagonal positions at each intersection of the scanning line and the signal line. In the active matrix substrate, the drain electrode or picture element electrode of the first insulated gate transistor at address (m, n) and the address (m+2, n+1) or (m+1, n
+1) The drain electrode or picture element electrode of the second insulated gate transistor at address (m+1, n+2) or the drain electrode or picture element electrode of the second insulated gate transistor at address (m-1, n+2) The first and second insulated gate transistors are connected in series with each other and the electrical characteristics are inspected twice, and then the connection is canceled and the characteristics are defective (large OFF current). A method for manufacturing an active matrix substrate capable of detecting and repairing point defects, characterized in that the connection between an insulated gate transistor and a pixel electrode is disconnected. (21) A removable wiring material is used between the signal line and the plurality of insulated gate transistors so that the plurality of insulated gate transistors can be electrically inspected independently within a unit picture element. In an active matrix substrate formed with interconnections between the
A method for manufacturing an active matrix substrate with point defects repaired, characterized by selectively forming a common pixel electrode except for insulated gate transistors. (22) The point defect repair method according to claim 21, wherein the interconnection of the plurality of insulated gate transistors has a configuration as described in claim 7, 11, 13, 15, or 18. A manufacturing method for active matrix substrates. (23) A removable wiring material is provided between the signal line and the plurality of insulated gate transistors so that the plurality of insulated gate transistors constituting a unit picture element can be electrically inspected independently. The interconnections between the elements are formed, and after the electrical inspection of the insulated gate transistor is completed, the interconnection is released, resulting in defective characteristics (O
A claim characterized in that a part of the picture element electrode is formed so that the connection between the insulated gate transistor (FF current large) and the picture element electrode is selectively avoided based on electrical inspection data. 22. A method for manufacturing an active matrix substrate with point defects repaired according to item 21. (24) A removable wiring material is provided between the signal line and the plurality of insulated gate transistors so that the plurality of insulated gate transistors constituting a unit picture element can be electrically inspected independently. Interconnections between elements are formed, and after the electrical inspection of the insulated gate transistor is completed, the interconnection is released, and based on the electrical inspection data, the insulated gate transistor with poor characteristics (large OFF current) is removed from the regular wiring. 22. The method for manufacturing an active matrix substrate with point defects repaired according to claim 21, characterized in that after separation by laser irradiation, one picture element electrode shared by two insulated gate transistors is selectively formed. . (25) Wiring that can be removed between signal lines and between multiple insulated gate transistors so that multiple insulated gate transistors and pixel electrodes can be electrically inspected independently within a unit pixel The interconnection between the elements is formed using a material, and the interconnection is released after the electrical inspection of the insulated gate transistor, and the drain electrode of the insulated gate transistor with poor characteristics (low ON current) after the electrical inspection is completed. A small conductive pattern is formed by laser spot irradiation on the pixel electrode connected to the insulated gate transistor and the drain electrode of a normal insulated gate transistor or the pixel electrode connected to the insulated gate transistor in question. A method for manufacturing an active matrix substrate with point defects repaired, characterized by connecting with a thin film. (26) A method for manufacturing a point defect repaired active matrix substrate according to claim 25, wherein the interconnection of the plurality of insulated gate transistors has a structure as described in claim 18.