JPH02256230A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a good plug with respect to any via holes of various shapes by a method wherein a conductive layer is formed only in the vicinity of the via holes formed on an insulation layer and the conductor is fused by an energy beam to form plugs in the via holes. CONSTITUTION:A conductive layer is formed only in the vicinity of via holes 10, 12 formed on an insulation layer 8, and the conductor is fused by an energy beam to form plugs 16, 18 in the via holes 10, 12. Therefore the plugs 16, 18 for filling up a plurality of via holes 10, 12. Forming a wiring layer after formation of the plugs 16, 18 permits the plugs to be electrically connected to the respective via holes 10, 12 so that the wiring layer of uniform thickness can be formed. Thus a good plug can be formed with respect to via holes having various shapes.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for manufacturing a semiconductor device in which a conductor layer deposited near a via hole is melted by an energy beam to form a plug in the via hole, and is suitable for via holes of various shapes. The purpose of this method is to provide a method for manufacturing a semiconductor device that can form a plug with a wide range of characteristics.The purpose of this method is to form a conductor layer only in the vicinity of a via hole formed in an insulating layer, and melt the conductor with an energy line to melt the conductor inside the via hole. configured to form a plug.

[Industrial application field]

The present invention is directed to a method of manufacturing a semiconductor device in which a conductor layer deposited near a via hole is melted by an energy beam to form a plug in the via hole.

(Prior Art) It is known that when a wiring metal layer is deposited on an uneven surface by vapor deposition or sputtering, the step coverage of the wiring metal layer is generally not very good. In particular, the wiring metal layer is difficult to adhere to the inner surface of so-called via holes such as contact holes and through holes. As semiconductor devices become more highly integrated and densely packed, wiring becomes finer and via holes become finer, making it increasingly difficult for wiring metal layers to adhere. Good wiring could not be formed.

For this reason, a technique is known in which a wiring metal layer is formed and then irradiated with pulsed laser light to flatten the wiring metal layer. Although this planarization technology fills the inside of the via hole with wiring metal, it is not possible to make the thickness of the wiring layer uniform in the case of an uneven formation surface, and the subsequent etching process of the wiring layer is difficult. It was causing trouble.

For this reason, it has been considered to bury metal in the via hole in advance (see Japanese Patent Application Laid-Open No. 115835/1983).
. The inside of the via hole is filled with metal, and a wiring layer of a certain thickness is deposited to fill the via hole.

[Problem to be solved by the invention]

However, since the via holes in which plugs are actually to be formed have various sizes and depths, it has been extremely difficult to form good plugs in any of these via holes.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form good plugs even in via holes of various shapes.

[Means to solve the problem]

The above purpose is to form a conductor layer only in the vicinity of multiple via holes formed in the insulating layer, and to irradiate the conductor layer with an energy beam so that the molten conductor completely fills the via holes to form each via hole. This is achieved by a method of manufacturing a semiconductor device comprising the step of forming a conductive plug within the semiconductor device.

The above object also includes a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer, and a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer, and a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer, and a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer, and a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer, and a step of forming a conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer. forming a conductive plug in each via hole by irradiating the conductive layer with an energy beam so as to fill the conductive layer with the energy beam, and the second layer is an insulator that is substantially transparent to the energy beam and is conductive. This is also achieved by a method of manufacturing a semiconductor device in which the body layer is made of a material with a higher absorption coefficient than the second layer.

The above purpose is to form a first conductor layer only in the vicinity of one or more via holes formed in a second layer provided on the first layer; forming a second conductor layer; irradiating the second conductor layer with an energy beam so that the melted first and second conductors completely fill the via hole to form a conductor in each via hole; forming a plug, a second layer being an insulator substantially transparent to the energy beam, and a second conductor layer being larger than the two layers and the first conductor layer. This can also be achieved by a method of manufacturing a semiconductor device made of a material having an absorption coefficient.

The above purpose is to form a conductor layer only in the vicinity of one or more via holes formed in an insulating layer and a reflective layer provided on the first layer, and to completely fill the via hole with the molten conductor. irradiating the conductor layer with an energy beam to form a conductor plug in each via hole, the insulating layer being substantially transparent to the energy beam, and the reflective layer being substantially transparent to the insulating layer. This is achieved by a method of manufacturing a semiconductor device made of a material having a higher reflectance than the layer.

Furthermore, the above object includes forming a conductive layer only in the vicinity of one or more via holes formed in the insulating layer;
forming an absorbing layer on the conductive layer and the insulating layer;
forming a conductor plug in each via hole by irradiating the conductor layer with an energy beam so that the molten conductor completely fills the via hole, and the insulating layer is substantially in contact with the energy beam. This can also be achieved by a method of manufacturing a semiconductor device that is transparent and in which the absorbing layer is made of a material that has a larger absorption coefficient for the energy rays than the insulating layer.

[Effect]

According to the present invention, since the via conductor layer is deposited near each via hole, when the conductor layer is melted with an energy beam, the via hole is exactly filled and a good plug is formed.

〔Example〕

A method of manufacturing a semiconductor ￥A＠ according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. Hereinafter, in order to facilitate understanding, the size and depth of the via hole will be explained in a simplified manner, but the same applies even in the case of a more complicated case.

FIG. 1 shows the case where plugs are formed in two via holes 10, 12 of the same size and depth formed in the insulating layer 8. As shown in the figure, the size of each via hole 10.12 is 2μm x 2μm, and the depth is 1.5μm.
It is m.

In this case, the total volume VO of the via holes 10.12 is VO-2X (2X2X 1.5) = 12μ fake3.

The metal layer 14 is deposited in a rectangular shape of 4 μm×B μm as shown in FIG.

After forming the metal layer 14, a laser beam serving as an energy beam is irradiated, for example, under the following conditions.

Light: XeC excimer laser Energy density: 2.2 J/cm Number of irradiation times = 4 times Substrate heating temperature: 300°C Atmosphere during irradiation: ゛Vacuum (4X 10'' 5 Torr)
As a result, the metal layer 14 melts and the via hole 10°12
Plug 16.1 flows into the via hole 10.12.
8 is formed.

2 to 4 show the states before and after melting when the thickness of the metal layer 14 having the area shown in FIG. 1 is changed.

Assuming that the thickness of the metal layer 14 is 2 μm as shown in FIG. 2(a), the volume Vm of the deposited metal is Vm-(4X8-2X2X2) assuming that almost no metal layer 14 is deposited on the via hole 10.12. X2 = 48 μm 3 >2V.

becomes. In this case, as shown in FIG. 2(b), too much metal spreads to the periphery and no plug is formed.

Assuming that the thickness of the metal layer 14 is 1 μm as shown in FIG. 3(a), the volume Vm of the deposited metal is m=(4x8-2x2x2)x1 =24am3=2VO. In this case, a plug 16.18 is formed in the via hole 10.12 as shown in FIG. 3(b).

Assuming that the thickness of the metal layer 14 is 0.5 μm as shown in FIG. 4(a), the volume Vm of the deposited metal is Vm=(4x8
-2x2x2)xO,5=12um3<2V.

becomes. In this case, a short plug 16.18 is formed in the via hole 10.12 as shown in FIG. 4(b).

As can be seen from FIGS. 2 to 4, if the volume of the metal layer 14 is less than twice the total volume of the via hole 10.12, a good plug 16.18 is formed in each via hole 10.
．． 12.

Note that in the above case, the area of the metal layer 14 was made the same, but
The area may be increased as long as it can flow into the via hole in a fluidized state after melting.

Next, an embodiment applied when the via holes 10.12 have different volumes will be described with reference to FIGS. 5 to 7.

FIG. 5 is a diagram for explaining the second embodiment, and in this embodiment, the via holes 10 and 12 have different sizes.

FIG. 5(a) is a plan view thereof, and FIG. 2(b) is a sectional view thereof.

The via hole 10 has a size of 2 μm×2 μm, and the via hole 12 has a size of 4 μlll×4 μm.

The depth is the same, 1.5 μm.

In this case, the total volume of the via hole 10.12 is Vo = 1.5x (2x2+4x4) = 30μm3, so the metal layer 14 with a thickness of 1μm is shaped into a shape with an area of 60μm2 as shown in Fig. 5(a). Form it so that it becomes. At this time, as shown in FIG. 5, more metal layer 14 is deposited near the via hole 12 having a larger volume.

The volume Vm of the entire metal layer 14 is Vm= (4X4-2X2 +8X8-4X4)Xl -6C1m 3 = 2V.

becomes.

Therefore, in the case of Figure 5, 1
It is only necessary to form the metal layer 14 with a thickness of μm or less.

FIG. 6 is a diagram for explaining the third embodiment, and in this embodiment as well, the via holes 10 and 12 have different sizes.

FIG. 5(a) is a plan view thereof, and FIG. 2(b) is a sectional view thereof.

The via hole 10 has a size of 2 μm×2 μm, and the via hole 12 has a size of 2 μm×4 μm.

In this case, the total volume vO of the via hole 10.12 is Vo = 1.5 Form it so that At this point, as shown in FIG. 6, more metal layer 14 is deposited near the via hole 12, which has a larger volume.

The volume Vm of the entire metal layer 14 is Vm-(4X12-2X2-2X4>X1=36μm
3=2VO.

Therefore, in the case of Figure 6, 1
It is sufficient to form the metal layer 14 with a thickness of μm or less.

FIG. 7 is a diagram for explaining the fourth embodiment, and in this embodiment, the depths of the via holes 10 and 12 are different.

FIG. 5(a) is a plan view thereof, and FIG. 2(b) is a sectional view thereof.

Both via holes 10 and 12 have a size of 2μn+2μm, and the depth of the via hole 10 is 1.5μm.
The depth is 3 μm.

In this case, the total volume vO of the via hole 10.12 is V o = 1.5x 2 X 2+ 3 X 2
2=18 .mu.m, so gold B@14 with a thickness of 1 .mu.m is formed into a shape with an area of 36 .mu.m.sup.2 as shown in FIG. 7(a). At this time, as shown in FIG. 7, more metal layer 14 is deposited near the via hole 12, which has a larger volume.

The volume ■m of the entire metal layer 14 is Vm-(4x11-2x2-2x2)xl-36μn
3 = 2V.

becomes.

Therefore, in the case of FIG. 7, it is sufficient to form the metal layer 14 having a thickness of 36 μm2Jj and a thickness of 1 μm or less in the area below.

In this way, if the area and thickness of the metal layer formed around the via hole are determined so that the volume is less than twice the volume of the via hole, even if separate metal layers are not formed for each via hole, A metal layer covering multiple via holes may be formed.

It goes without saying that the number of via holes is not limited to two, and the shape of the via holes can also be set arbitrarily. Further, the metal layer may be formed of aluminum (An, a metal other than A2, an alloy containing a metal such as A2, etc.), and may be a conductive layer.

Further, in FIGS. M2 to FIG. 7, the illustration of the wiring layer is omitted for convenience, but in FIGS. 2 to 6, for example, a wiring layer connecting to two plugs is provided in the substrate 8, and In the figure, for example, first and second wiring layers are provided in the substrate 8, which are respectively connected to two plugs having different depths.

Multilayer wiring is used depending on the structure of the semiconductor device.

For example, a first wiring layer is formed on a substrate (or an insulating layer), a second wiring layer is formed on a living room insulation layer provided on the first wiring layer, and these first and second wiring layers The wiring layers are connected via via holes. However, when forming a plug in a via hole prior to forming the second wiring layer, a portion of the interlayer insulating layer other than the vicinity of the via hole is directly irradiated with pulsed laser light. This pulsed laser beam is used to melt the metal layer near the via hole and form a plug in the via hole, as in each of the above embodiments.

Usually, the interlayer insulating layer is made of PSG, 5iOz, etc., and is transparent to pulsed laser light. Therefore, when the living room insulating layer is irradiated with pulsed laser light, the pulsed laser light is irradiated onto the first wiring layer under the living room insulating layer, and the first wiring layer is melted. If the first wiring layer melts, problems such as destruction of the pattern of the first wiring layer and disconnection will occur.

Therefore, an embodiment that can solve this problem will be described.

In the fifth embodiment, the metal layer is formed on the interlayer insulating layer near the via hole as in the first to fourth embodiments, but
This metal layer is made of a material that melts at a lower pulsed laser energy density than the wiring layer provided below the interlayer insulating layer. According to this embodiment, it is possible to prevent the wiring layer under the interlayer insulating layer from melting when forming a plug in a via hole. The fifth embodiment will be described below with reference to FIG.

In FIG. 8(a), a 5iOz layer 22 is formed on a 3i substrate 21, and a first wiring layer 2 is formed on the 5iOz layer 22.
3 is formed. In this example, the film thickness of 5iOzJi 22 is 0.8 μm t', and the first wiring layer 23 is made of A2 and has a film thickness of 0.5 μm.

An interlayer insulating layer 24 is formed on the first wiring layer 23 .

The interlayer insulating layer 24 is made of PSG, for example, and has a thickness of 0.5μ.
It is m. A metal layer 26 is formed near the via hole 25 on the interlayer insulating layer 24 . This metal layer 26 is made of copper (Cu
) and has a film thickness of 0.6 μm. When the metal layer 26 is irradiated with pulsed laser light, the molten metal forms the via hole 25.
For example, it is formed in the same manner as in the first to fourth embodiments so as to flow into the inner part.

The absorption coefficient of Cu is about 0.9 x 106/cm in the optical wavelength band of 190 nm to 350 nm, and the absorption coefficient of A2 is about 1.3 x 106/cm in the same optical wavelength band. In other words,
The absorption coefficients of Cu and A,2 are almost the same, and both absorb 80% or more of the incident light to a depth of about 100 m from the surface. On the other hand, the reflectance of CLI is about 20%, while the reflectance of Ae is about 90% or more. As a result,
Between the Cu layer and the A2 layer, the Cu layer emits about 70% more pulsed laser light than the A4 layer, contributing to heating the CLI layer. As a result, even though the melting point of Cu is 1084°C, which is higher than the melting point of Ae, 660°C,
It becomes possible to melt the Cu layer at a lower energy density than the pulsed laser energy density required to melt the two layers. When a XeC2 excimer laser is used, a pulsed laser energy density of 6 J/i is required to melt A2, but Cu can be melted at a lower energy density of 2 J/ci.

Therefore, simply add the metal (Cu) layer 26 to 2 J/cm
(7) By melting with pulsed laser energy density, the plug 2 is melted into the via hole 25 as shown in FIG. 8(b).
8 can be formed. In this case, the wiring layer 23 is irradiated with pulsed laser light through the interlayer insulating layer 24 that is transparent to the pulsed laser light, but the wiring layer 23 does not melt because the pulsed laser energy density is low. Therefore, there is no risk of destruction or disconnection of the wiring layer 23 due to irradiation with pulsed laser light.

In the sixth embodiment, a metal layer is formed on the interlayer insulating layer near the via hole as in the first to fourth embodiments.
This metal layer has a two-layer structure.

This two-layer structure consists of a first metal layer formed on an interlayer insulating layer and a second metal layer formed on the first metal layer. The second metal layer is made of a material that melts at a lower pulse laser energy density than the first metal layer and melts at a lower pulse laser energy density than the wiring layer provided under the interlayer insulating layer. According to this embodiment, it is possible to prevent the wiring layer under the interlayer insulating layer from melting when forming a plug in a via hole. The sixth embodiment will be described below with reference to FIG. 9.

In FIG. 9, parts that are substantially the same as those in FIG. 8 are designated by the same reference numerals, and their explanation will be omitted. In FIG. 9(a), an A2 layer 31 is formed near the via hole 25 on the interlayer insulating layer 24, and a Cu layer 32 is formed on this Ae131. 'For example, the thickness of the A2 layer 31 is O', 5 μm,
The thickness of the Cu layer 32 is 100 mm, and the diameter of the via hole 25 is 0.8 μm. Pulsed laser light is Cu132
When irradiated with the Cu layer 32, about 20% of the pulsed laser light is reflected, but the remaining 80% is absorbed into the Cu layer 32. Therefore, the 00 layer 32 is heated, and this heat is transferred to the A2 layer 31 to melt the A2 layer 31. As a result, an alloy consisting of Cu and A2 flows into the via hole 25, as shown in FIG.
) A plug 33 as shown in FIG. Here, 00 layer 3
The pulsed laser energy density required to melt 2 is 2
Since it is as low as J/ci, destruction and disconnection of the wiring layer 23 can be prevented.

In the fifth and sixth embodiments, only one via hole is shown for convenience, but it goes without saying that these embodiments can be similarly applied even when there are two or more via holes. Further, ditanium (T i ) may be used instead of Cu. Furthermore, if the wiring layer provided under the living room insulating layer is made of silicide or silicon, a second metal layer made of A2 instead of Cu (T i ) may be formed near the via hole.

Note that the first and second metal layers (31, 32) do not necessarily need to be metal, but may be conductive layers.

Next, depending on the structure of the semiconductor device, such as the metal layer formed near the via hole or the material used for the wiring layer under the interlayer dielectric layer, a relatively high pulsed laser energy density may be required to melt the layer. Sometimes it is required. In such a case, layers such as a wiring layer provided under the interlayer insulating layer will be damaged by the pulsed laser beam.

Therefore, an embodiment that can solve this problem will be described.

In the seventh embodiment, a reflective layer is formed on the interlayer insulating layer to prevent pulsed laser light from passing through the interlayer insulating layer when forming a plug. In FIG. 10(a), an A2 wiring layer 43 is formed on the substrate layer 42, and a P2 wiring layer 43 is formed on the A2 wiring layer 43.
An SG interlayer insulating layer 44 is formed. PSG interlayer insulation layer 4
A reflective layer 45 is formed on the reflective layer 4, and Ae is formed on the reflective layer 45.
-8i metal layer 46 is formed. The reflective layer 45 is made of, for example, iridium (Ir) or rhodium (Rh).

In this embodiment, the thickness of the PSG interlayer insulating layer 44 is 1 μm1.
The thickness of the reflective layer is 10 nIl, and the thickness of the Al1-3i metal layer 46 is 1 μm.

Patterning is performed to form via holes 46, and etching is performed to leave metal layer 46A only in the vicinity of via holes 47, as shown in FIG. 10(b). beer hall 4
7 penetrates through layers 45 and 44 to expose the surface of A2 wiring layer 43.

Next, the entire surface of the structure shown in FIG. 10 (bi) is irradiated with xecg excimer laser light having a wavelength of 308 nm. By irradiating this laser light, the metal layer 46A is melted and
7 to form a plug 48 shown in FIG. 10(C). However, the reflective layer 45 is XeCJ! Since the metal layer 46A has a high reflectance for system excimer laser light and a high melting point, the metal layer 46A melts and satisfactorily fills the via hole 47.
There is no fear that the laser light will damage the A4 wiring 843 through the PSG interlayer insulating layer 44.

For the wave f, 308 nm XeCf1 excimer laser light, the reflectance of lr is about 80% and the melting point is 2454.
It is ℃. For the same laser beam, the reflectance of Rh is about 7
0% and the melting point is 1966°C.

In the eighth embodiment, an absorption layer is formed on the interlayer insulating layer so that the pulsed laser light does not pass through the interlayer insulating layer when forming the plug. In FIG. 11, parts that are substantially the same as those in FIG. 10 are designated by the same reference numerals, and their explanation will be omitted.

In FIG. 11(a), an absorbing layer 51 is formed on the entire surface of the structure basically the same as that in FIG. 10(b) except that a reflective layer is not provided. In this embodiment, the A2 wiring layer 43
The film thickness of the PSG interlayer insulating layer 44 is 1 μm.
The absorption layer 51 is made of polysilicon and has a thickness of 5Q.
It is nm. Polysilicon has a reflectance of about 40% for ArF excimer laser light. Therefore, ArF
When the entire surface of the structure shown in FIG. 11(a) is irradiated with system excimer laser light, the metal layer A near the via hole 47
A melts and flows into the via hole 47 as shown in Fig. 11 (
A plug 58 shown in b) is formed. Polysilicon absorption layer 51A remains on PSG interlayer insulating layer 44 except in the vicinity of via ball 47. Since the melting point of PSG is higher than that of Ae, the PSG interlayer insulating layer 44 becomes the absorption layer 51 (51A).
Since the wiring layer 43 is not melted by the heat absorbed by the wiring layer 43, the wiring layer 43 is prevented from being destroyed or disconnected.

In the seventh and eighth embodiments, only one via hole is shown for convenience, but it goes without saying that these embodiments can be similarly applied even when there are two or more via balls. In addition, the materials used for the reflective layer and the absorbing layer are the seventh and eighth materials.
It is not limited to the examples. Furthermore, the layer provided under the living room insulation layer is not limited to the wiring layer. The purpose of providing the reflective layer and the absorbing layer in the seventh and eighth embodiments is to prevent damage to the layer provided under the interlayer insulating layer when forming the plug.

In each embodiment, the shape of the via hole may be any shape, and the metal layer provided to form the plug may be a conductive layer.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

(Effects of the Invention) According to the present invention, a conductor layer is formed only in the vicinity of a via hole formed in an insulating layer, and a plug is formed in a via hole by melting the conductor with a single energy wire. A plug is formed to exactly fill each via hole, and if a wiring layer is formed after the plug is formed, it is electrically connected to each via hole, so a wiring layer with a thickness of - can be formed, and subsequent etching This makes it easier and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a plan view for explaining the first embodiment of the present invention, FIGS. 2 to 4 are sectional views for explaining the first embodiment under different conditions, and FIGS. 5 to 4 are sectional views for explaining the first embodiment under different conditions. 7 is a cross-sectional view for explaining the second to fourth embodiments of the present invention, FIGS. 8 and 9 are cross-sectional views for explaining the fifth and sixth embodiments of the present invention, respectively. 11 are cross-sectional views for explaining seventh and eighth embodiments of the present invention, respectively. 1 to 11, 8 is an insulating layer, 10.12.25.47 is a via hole, 14.26, 3
1, 32, 46, 46△ is a metal layer, 16.18, 28,
33.48.58 is the plug, 21 is the board, 22 is S! Oz layer, 23.43 is a wiring layer, 24.44 is an interlayer insulating layer, 45 is a reflective layer, and 51.51A is an absorption layer. zu←−tad≦? → 1 so 1; 1 wamin sleep A door beg beg vivi) river 1-r-s tasau pfu El”to” 1st figure shitoshicho l doctor o beg Shin 1 sweet Tokorikawa T Rome no C
Figure 4) The anger of early Pt Ding 17) Nishikigami 111 C1 in order to defeat the enemy 21 Different flight → To Ding to ν 1 Takabo package νil襄寥υ Use 6 for the reverse chain diagram Figure 3 God's dumb shoulder BJ to 2 Tsun every sand F wave selection 1 to use Hagen'r
Qtfi Figure 5 (a) (b) Oki 9 Ru 13 Pheasant color + Ji' Rust and NT sake cup diagram (a) (b) Ne 4 foundation q 4 f) 斃 5 Great note request ya 11 a Yaya Wataru [6 Figure 8 (a) (b) Honhatsu pruning 7 + Daimasuro 1 Kyoju) To make snow (蓼0.8
μm (a) (b) Suzutsukuda diagram for half-six large defenses and 1 shadow of the ears (a) (b) (c) Rule p number n% 7 male direction Ijden ◇ Ko Palm motion diagram for T (a
) (b) Ohan 9th Kaya 8 Oi also IJ Shiba Ku) Zero to go down the moon is Ka Figure 11

Claims (1)

[Claims] (1) A plurality of via holes (1) formed in an insulating layer (8)
forming a conductor layer (14) only in the vicinity of the via hole (0, 12); and irradiating the conductor layer with an energy beam so that the molten conductor completely fills the via hole to form a conductor layer in each via hole. A method for manufacturing a semiconductor device, comprising the step of forming plugs (16, 18). (2) Second layer (4) provided on the first layer (23)
forming a conductor layer (26) only in the vicinity of one or more via holes (25) formed in the conductor layer; and irradiating the conductor layer with energy beams so that the molten conductor completely fills the via holes. forming a conductive plug (28) in each via hole, the second layer (24) being an insulator substantially transparent to the energy beam; 26) A method for manufacturing a semiconductor device, characterized in that the second layer (24) is made of a material having a larger absorption coefficient. (3) The second layer (24) provided on the first layer (23)
) forming a first conductor layer (31) only in the vicinity of one or more via holes (25) formed in the first conductor layer; and forming a second conductor layer (32) on the first conductor layer. forming a conductor plug (33) in each via hole by irradiating the second conductor layer with an energy beam so that the molten first and second conductors completely fill the via hole; the second layer (24) is an insulator substantially transparent to the energy beam, and the second conductive layer (32) is formed on the second layer (24). ) and a material having a larger absorption coefficient than the first conductor 8 (31). (4) One or more via holes (4) formed in the insulating layer (44) and the reflective layer (45) provided on the first layer.
Step 6) of forming a conductor layer (46A) only in the vicinity of the conductor layer (46A), and irradiating the conductor layer with an energy beam so that the molten conductor completely fills the via hole to form a conductor plug (46A) in each via hole. 48), the insulating layer (44) is substantially transparent to the energy beam, and the reflective layer (45) is made of a material having a greater reflectivity than the insulating layer (44). A method of manufacturing a semiconductor device, comprising: (5) forming a conductive layer (46A) only in the vicinity of one or more via holes (46) formed in the insulating layer (44); ), and forming a conductor plug (58) in each via hole by irradiating the conductor layer with an energy beam so that the molten conductor completely fills the via hole. The insulating layer (44) is substantially transparent to the energy rays, and the absorption layer (51) is made of a material having a larger absorption coefficient for the energy rays than the insulating layer (44). A method for manufacturing a semiconductor device.