JPH0691086B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0691086B2 JPH0691086B2 JP59124941A JP12494184A JPH0691086B2 JP H0691086 B2 JPH0691086 B2 JP H0691086B2 JP 59124941 A JP59124941 A JP 59124941A JP 12494184 A JP12494184 A JP 12494184A JP H0691086 B2 JPH0691086 B2 JP H0691086B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- opening
- openings
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものであって、
高密度LSIにおける多層配線を形成するのに用いて最適
なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device,
It is most suitable for forming multi-layer wiring in high density LSI.
背景技術とその問題点 LSIにおける多層配線は、従来例えば次のような方法に
より形成されていた。即ち、第１図に示すように、シリ
コン基板１の表面に形成されているSiO2膜２上に第１層
のAl配線３を形成し、次いでこの第１層のAl配線３を被
覆するように、層間絶縁膜としてのPSG膜４を形成した
後、このPSG膜４の所定部分をエッチング除去して開口4
a（コンタクト・ホール）を形成する。なお開口4aの上
端にはテーパ4bを形成しておく。次に全面にAl膜を被着
形成し、次いでこのAl膜をパターンニングすることによ
り、上記開口4aを通じて第１層のAl配線３と接続されて
いる第２層のAl配線５を形成する。このようにして、Al
配線３とAl配線５とから成る２層配線が形成される。Background Art and Its Problems Multilayer wiring in LSI has been conventionally formed, for example, by the following method. That is, as shown in FIG. 1, the first layer Al wiring 3 is formed on the SiO 2 film 2 formed on the surface of the silicon substrate 1, and then the first layer Al wiring 3 is covered. After forming a PSG film 4 as an interlayer insulating film on the above, a predetermined portion of the PSG film 4 is removed by etching to form an opening 4
Form a (contact hole). A taper 4b is formed at the upper end of the opening 4a. Next, an Al film is deposited on the entire surface, and then this Al film is patterned to form a second layer Al wiring 5 connected to the first layer Al wiring 3 through the opening 4a. In this way, Al
A two-layer wiring composed of the wiring 3 and the Al wiring 5 is formed.
ところが、LSIの高密度化に伴って素子が微細化された
結果、次のような問題が生じている。即ち、素子の微細
化は、LSIの動作速度の低下防止、１個のトランジスタ
の取扱い電荷量の減少防止、駆動電圧を5Vに固定するこ
と等の理由により縦方向（厚さまたは深さ方向）のスケ
ーリングには限界があるため、主に横方向（平面上）の
スケーリングによって行われている。しかしながら、こ
のように横方向のスケーリングが行われると、上述の第
１図に示す開口4aの径ｄに対するその深さｈの比h/d、
即ちいわゆるアスペクト比（aspect ratio）が大きくな
り、この結果、開口4aの近傍において第２層のAl配線５
のステップ・カバレッジ（atep coverage）が悪化してA
l配線５の断線等が生じやすい。これを防止するため
に、従来は開口4aの上端に第１図に示すようにテーパ4b
を形成することにより、開口4aの近傍でのAl配線５のス
テップ・カバレッジを改善させていた。しかし、このよ
うな方法では、第１に、アスペクト比が大きくなった場
合（特に0.5以上の場合）、Al配線５のステップ・カバ
レッジが第２図に示すように悪くなるので、Al配線５の
断線を避けるのが難しい。また第２に、開口4aにテーパ
4bを形成することによって良好なステップ・カバレッジ
を得ようとする場合には、第３図に示すように、テーパ
4bの横方向及び縦方向の寸法ｔ、ｔ′を開口4aの径ｄ及
び深さｈに対して大きくしなければならないので、LSI
の高密度化に適さない。第３に、第４図に示すようにPS
G膜４の厚さが互いに異なる領域にそれぞれAl配線3a,3b
に達する開口4c,4dをエッチングにより同時に形成する
場合、深さが小さい方の開口4dの径がテーパ4bを形成し
ない場合に比べてかなり大きくなってしまう。However, the following problems have arisen as a result of the miniaturization of elements accompanying the higher density of LSIs. That is, the miniaturization of the device is performed in the vertical direction (thickness or depth direction) for reasons such as prevention of reduction in the operating speed of the LSI, prevention of reduction in the amount of charge handled by one transistor, and fixation of the drive voltage at 5V. Since there is a limit to the scaling of, the scaling is mainly performed in the lateral direction (on the plane). However, when the lateral scaling is performed in this manner, the ratio h / d of the depth h to the diameter d of the opening 4a shown in FIG.
That is, the so-called aspect ratio becomes large, and as a result, the Al wiring 5 of the second layer is formed near the opening 4a.
A step coverage (atep coverage) deteriorates
l The wiring 5 is likely to be broken. In order to prevent this, conventionally, the taper 4b is provided at the upper end of the opening 4a as shown in FIG.
By forming the above, the step coverage of the Al wiring 5 near the opening 4a was improved. However, in such a method, firstly, when the aspect ratio becomes large (particularly when it is 0.5 or more), the step coverage of the Al wiring 5 becomes worse as shown in FIG. It is difficult to avoid disconnection. Secondly, the opening 4a is tapered.
In order to obtain good step coverage by forming 4b, as shown in FIG.
Since the horizontal and vertical dimensions t and t'of 4b must be larger than the diameter d and depth h of the opening 4a, the LSI
Not suitable for high density. Third, as shown in Fig. 4, PS
Al wirings 3a and 3b are formed in regions where the thickness of the G film 4 is different from each other.
When the openings 4c and 4d reaching the height are simultaneously formed by etching, the diameter of the opening 4d having a smaller depth becomes considerably larger than that in the case where the taper 4b is not formed.
なお例えば回路基板等の分野において上述と同様な問題
を解決するための技術として、特開昭55-86198号公報に
は液状導電材を用いたコンタクト・ホールの接続方法
が、また特開昭55-108103号公報及び特開昭56-134404号
公報にはガリウムを主体とした液状導電材がそれぞれ開
示されている。As a technique for solving the same problem as described above in the field of circuit boards, for example, JP-A-55-86198 discloses a contact hole connection method using a liquid conductive material, and JP-A-55-86198. -108103 and JP-A-56-134404 disclose liquid conductive materials mainly containing gallium.
発明の目的 本発明は、上述の問題にかんがみ、多層配線を形成する
ための従来の半導体装置の製造方法が有する上述のよう
な欠点を是正した半導体装置の製造方法を提供すること
を目的とする。SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the above-mentioned drawbacks of the conventional method of manufacturing a semiconductor device for forming a multi-layer wiring are corrected. .
発明の概要 本発明に係る半導体装置の製造方法は、第１の絶縁膜上
に第１の配線を形成する工程と、上記第１の配線及び上
記第１の絶縁膜を被覆する第２の絶縁膜を形成する工程
と、上記第１の配線に達する開口を上記第２の絶縁膜に
形成する工程と、少なくとも上記開口を埋めるように、
流動性を有する導電性物質を形成する工程と、流動性を
有する上記導電性物質を固化させる工程と、固化された
上記導電性物質と接続されている第２の配線を、上記固
化の後に上記第２の絶縁膜上に形成する工程とをそれぞ
れ具備している。このようにすることによって、第２の
絶縁膜の開口のアスペクト比が大きい場合においても、
開口の近傍において配線の断線を生ずることなく第２の
配線を形成することができる。SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first wiring on a first insulating film, and a second insulation covering the first wiring and the first insulating film. A step of forming a film, a step of forming an opening reaching the first wiring in the second insulating film, and at least filling the opening,
The step of forming a conductive material having fluidity, the step of solidifying the conductive material having fluidity, and the second wiring connected to the solidified conductive material, And a step of forming on the second insulating film. By doing so, even when the aspect ratio of the opening of the second insulating film is large,
The second wiring can be formed in the vicinity of the opening without breaking the wiring.
実施例 以下本発明に係る半導体装置の製造方法の一実施例につ
き図面を参照しながら説明する。EXAMPLE One example of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
第5A図に示すように、第４図と同様にシリコン基板１の
表面にSiO2膜２（第１層の絶縁膜）を形成する。なおこ
のSiO2膜２のうちの膜厚の大きい部分及び膜厚の小さい
部分がそれぞれフィールド酸化膜2a及び例えばゲート酸
化膜2bを構成し、これらのフィールド酸化膜2aとゲート
酸化膜2bとの間に段差2cが形成されている。次にSiO2膜
２上に例えばスパッタ法によりAl膜を被着形成し、次い
でこのAl膜の所定部分をエッチング除去して第１層のAl
配線3a,3bを形成する。次に例えばCVD法により全面にPS
G膜４を被着形成し、次いで公知の平坦化プロセスによ
りPSG膜４の表面を第5A図に示すように平坦化する。こ
の後、反応性イオンエッチング（RIE）によりPSG膜４の
所定部分をエッチング除去して、Al配線3a,3bに達する
開口4c,4dを形成する。なおPSG膜４の表面が上述のよう
に平坦化された結果、開口4c,4dの深さは互いに異な
り、開口4cの方が開口4dよりも深くなっている。またシ
リコン基板１内には所定の拡散層（例えばMOS LSIにお
いてはソース領域及びドレイン領域等）が形成されてい
るが、第5A図においてはそれらの図示を省略した（以下
同様）。As shown in FIG. 5A, a SiO 2 film 2 (first insulating film) is formed on the surface of the silicon substrate 1 as in FIG. It should be noted that a portion of the SiO 2 film 2 having a large film thickness and a portion having a small film thickness respectively form a field oxide film 2a and, for example, a gate oxide film 2b, and between the field oxide film 2a and the gate oxide film 2b. A step 2c is formed on the. Next, an Al film is deposited on the SiO 2 film 2 by, for example, a sputtering method, and then a predetermined portion of this Al film is removed by etching to form the first layer of Al.
Wirings 3a and 3b are formed. Then, for example, the PS is
The G film 4 is deposited and then the surface of the PSG film 4 is planarized by a known planarization process as shown in FIG. 5A. After that, a predetermined portion of the PSG film 4 is etched and removed by reactive ion etching (RIE) to form openings 4c and 4d reaching the Al wirings 3a and 3b. As a result of the surface of the PSG film 4 being flattened as described above, the openings 4c and 4d have different depths, and the opening 4c is deeper than the opening 4d. Although a predetermined diffusion layer (for example, a source region and a drain region in a MOS LSI) is formed in the silicon substrate 1, their illustration is omitted in FIG. 5A (the same applies hereinafter).
次に第5B図に示すように、例えば粒径が約300ÅのAg粉
末が混合されているアルコール等の有機溶剤（導電性物
質）をスプレー（霧状またはシャワー状）法等により全
面に塗布し、次いでベーキング等の熱処理を行って上記
有機溶剤を蒸発させる。この結果、第5C図に示すよう
に、上記開口4c,4dの内部及び上記PSG膜４上に上記Ag粉
末が堆積する。このようにして、PSG膜４の開口4c,4dが
Ag粉末によって埋められる。なお上記Ag粉末から成る膜
を以下においては導電膜10と称する。Next, as shown in Fig. 5B, for example, an organic solvent (conductive substance) such as alcohol mixed with Ag powder having a particle size of about 300Å is applied to the entire surface by a spray (fog or shower) method. Then, heat treatment such as baking is performed to evaporate the organic solvent. As a result, as shown in FIG. 5C, the Ag powder is deposited inside the openings 4c and 4d and on the PSG film 4. In this way, the openings 4c and 4d of the PSG film 4 are
Filled with Ag powder. The film made of the Ag powder will be referred to as a conductive film 10 hereinafter.
次に第5D図に示すように、スパッタ法（または真空蒸着
法）によりAl膜11（またはAl-Si合金膜等）を全面に被
着形成し、次いでこのAl膜11上にフォトレジスト12を塗
布した後、このフォトレジスト12をパターンニングして
所定形状のフォトレジスト12a,12bを形成する。次にこ
れらのフォトレジスト12a,12bをマスクとして例えば既
述と同様なRIEにより上記Al膜11及び導電膜10を順次エ
ッチングすることにより、Al膜11a,11bと、Ag粉末から
成る導電膜10a,10bとから成る２層構造の配線14a,14bを
形成する。この後、フォトレジスト12a,12bを除去し
て、Al配線3a,3bと配線14a,14bとの２層配線構造の半導
体装置を完成させる。Next, as shown in FIG. 5D, an Al film 11 (or an Al-Si alloy film or the like) is deposited on the entire surface by a sputtering method (or a vacuum evaporation method), and then a photoresist 12 is formed on the Al film 11. After coating, the photoresist 12 is patterned to form photoresists 12a and 12b having a predetermined shape. Next, using the photoresists 12a and 12b as a mask, the Al film 11 and the conductive film 10 are sequentially etched by, for example, the same RIE as described above, so that the Al films 11a and 11b and the conductive film 10a made of Ag powder, Wirings 14a and 14b having a two-layer structure composed of 10b are formed. After that, the photoresists 12a and 12b are removed to complete a semiconductor device having a two-layer wiring structure of Al wirings 3a and 3b and wirings 14a and 14b.
上述の実施例によれば、第5B図に示す工程において、Ag
粉末が混合されている有機溶剤を全面に塗布し、次いで
熱処理を行って有機溶剤を蒸発させることによりAg粉末
から成る導電膜10を形成しているので、次のような利点
がある。即ち、PSG膜４の開口4c,4dは共に導電膜10で完
全に埋められているため、これらの開口4c,4dのアスペ
クト比が例えば0.5以上であっても、これらの開口4c,4d
の近傍においてAl膜11a,11bのステップ・カバレッジが
悪くなってAl膜11a,11b、従って配線14a,14bが断線を生
じることがない。またAl膜11a,11bのうちの開口4c,4dに
対応する部分に凹部が生じないため、多層配線を形成す
る上で有利である。同様に、配線の断線を防止するため
に、従来のように開口4c,4dの上端にテーパを設ける必
要がないので、製造工程が比較的簡単であるという利点
もある。According to the above embodiment, in the step shown in FIG. 5B, Ag
Since the organic solvent mixed with the powder is applied to the entire surface and then the heat treatment is performed to evaporate the organic solvent to form the conductive film 10 made of Ag powder, there are the following advantages. That is, since both the openings 4c and 4d of the PSG film 4 are completely filled with the conductive film 10, even if the aspect ratio of these openings 4c and 4d is 0.5 or more, these openings 4c and 4d are formed.
There is no possibility that the step coverage of the Al films 11a and 11b deteriorates in the vicinity of and the Al films 11a and 11b, and therefore the wirings 14a and 14b, are disconnected. Further, since no recesses are formed in the portions of the Al films 11a and 11b corresponding to the openings 4c and 4d, it is advantageous in forming a multilayer wiring. Similarly, it is not necessary to taper the upper ends of the openings 4c and 4d in order to prevent disconnection of the wiring, which is also advantageous in that the manufacturing process is relatively simple.
さらに、上述のように開口4c,4dにテーパを設ける必要
がないので、これらの開口4c,4dの深さが互いに異なる
にもかかわらず、第４図に関連して述べたように深さの
小さい方の開口4dの径がテーパを形成するためのエッチ
ングにより、開口4cの径に比べて大きくなるという問題
を解決することができる。従って、上述の実施例と同様
な工程を繰り返すことにより、２層以上の多層配線を形
成することが可能である。Further, since it is not necessary to taper the openings 4c and 4d as described above, the depths of the openings 4c and 4d are different as described with reference to FIG. It is possible to solve the problem that the diameter of the smaller opening 4d becomes larger than the diameter of the opening 4c due to the etching for forming the taper. Therefore, it is possible to form a multilayer wiring having two or more layers by repeating the same steps as those in the above-mentioned embodiment.
また上述の実施例によれば、開口4c,4dにテーパを形成
しないでも開口4c,4dの近傍においてAl膜11a,11bの断線
を生ずることがないので、これらの開口4c,4dの間隔を
小さくすることができ、このためLSIを高密度化する上
で極めて有利である。Further, according to the above-described embodiment, even if the openings 4c, 4d are not tapered, the Al films 11a, 11b are not broken in the vicinity of the openings 4c, 4d, so that the distance between the openings 4c, 4d is reduced. Therefore, it is extremely advantageous for increasing the density of the LSI.
本発明は上述の実施例に限定されるものではなく、本発
明の技術的思想に基づく種々の変形が可能である。例え
ば、上述の実施例においては、流動性を有する導電性物
質として、Ag粉末が混合された有機溶剤を用いたが、有
機溶剤の代わりにエポキシ樹脂等の流動性を有する有機
接着剤等を用いてもよく、またAg粉末の代わりに、Al、
Ｃ、Cu等の金属の粉末を１種または複数種同時に混合さ
せた有機溶剤または有機接着剤等を用いてもよい。なお
例えば金属粉末が混合された有機接着剤を用いた場合、
塗布時においては絶縁物であったとしても、その後に熱
処理を行ったりレーザビーム等により塗布膜に局所的に
エネルギーを与えたりすることによって導電性を付与す
ることができる。さらに、流動性を有する導電性物質と
しては、加熱等の処理を行って軟化させた金属等を用い
ることも可能である。The present invention is not limited to the above-mentioned embodiments, but various modifications can be made based on the technical idea of the present invention. For example, in the above-described examples, as the conductive material having fluidity, an organic solvent mixed with Ag powder was used, but instead of the organic solvent, an organic adhesive having fluidity such as epoxy resin is used. Alternatively, instead of Ag powder, Al,
You may use the organic solvent or organic adhesive etc. which mixed 1 type or multiple types of powders of metal, such as C and Cu, simultaneously. For example, when using an organic adhesive mixed with metal powder,
Even if it is an insulator at the time of coating, conductivity can be imparted by performing heat treatment thereafter or locally applying energy to the coating film by a laser beam or the like. Further, as the conductive material having fluidity, it is also possible to use a metal or the like that is softened by performing a treatment such as heating.
なお上述の実施例において用いる導電性物質は、LSIの
配線材料として用いられるAl、Mo、Ti、Ｗ、Pt、Au等の
金属、これらの金属の合金、これらの金属とシリコンと
の化合物（金属ケイ化物）及びシリコン等との接触抵抗
が数百Ω〜数ＫΩ（面積抵抗率で表して10-4〜10-5Ωcm
2）以下であると共に、下地材料に対してオーミック接
触となるのが好ましい。なお接触抵抗を減少させたりオ
ーミック接触させたりするために必要に応じて加熱処理
を行ってもよい。また上記導電性物質は上述のような種
々の配線材料や、LSIにおいて用いられるSiO2、Si3N4、
有機絶縁物等の絶縁物との密着性が高いことが好まし
い。なお密着性の向上のために必要に応じて加熱処理を
してもよい。さらに上記導電性物質は、常温または上記
加熱処理に用いる程度の温度で配線材料、半導体及び絶
縁膜等と著しい化学反応を起こしたり、配線の断線及び
絶縁破壊等を生じないのが好ましい。The conductive substance used in the above-mentioned embodiments is a metal such as Al, Mo, Ti, W, Pt, Au, etc. used as a wiring material of LSI, an alloy of these metals, a compound of these metals and silicon (metal Contact resistance with silicide and silicon etc. is several hundred Ω to several KΩ (area resistivity is 10 -4 to 10 -5 Ωcm
2 ) It is preferably less than or equal to, and is in ohmic contact with the underlying material. If necessary, heat treatment may be performed to reduce the contact resistance or make ohmic contact. Further, the conductive substance is various wiring materials as described above, SiO 2 used in LSI, Si 3 N 4 ,
It is preferable that the adhesiveness with an insulator such as an organic insulator is high. If necessary, heat treatment may be performed to improve the adhesion. Furthermore, it is preferable that the conductive substance does not cause a significant chemical reaction with the wiring material, the semiconductor, the insulating film, or the like at normal temperature or a temperature at which the heat treatment is performed, and does not cause disconnection or dielectric breakdown of the wiring.
また上述の実施例においては、Ag粉末が混合された有機
溶剤をスプレー法により塗布したが、必要に応じてスピ
ン・コート法等の他の方法を用いることも可能である。Further, in the above-mentioned examples, the organic solvent mixed with the Ag powder was applied by the spray method, but other methods such as the spin coating method can be used if necessary.
さらに上述の実施例においては、第5C図に示すように導
電膜10を全面に形成し、次いでAl膜11を形成したが、次
のようにしてもよい。即ち、導電膜10を形成後、RIEに
よりこの導電膜10をエッチングして第6A図に示す状態と
した後、第6B図に示すように、第5D図と同様にAl膜11及
びフォトレジスト12a,12bを形成し、次いで第6C図に示
すようにフォトレジスト12a,12bをマスクとしてAl膜11
をRIEによりエッチングして第２層のAl配線5a,5bを形成
してもよい。Further, in the above-described embodiment, the conductive film 10 is formed on the entire surface and then the Al film 11 is formed as shown in FIG. 5C, but it may be performed as follows. That is, after the conductive film 10 is formed, the conductive film 10 is etched by RIE to the state shown in FIG. 6A, and then, as shown in FIG. 6B, as in FIG. 5D, the Al film 11 and the photoresist 12a. , 12b are formed, and then the Al film 11 is formed using the photoresists 12a, 12b as masks as shown in FIG. 6C.
May be etched by RIE to form the second-layer Al wirings 5a and 5b.
また上述の実施例においては、PSG膜４の開口4c,4dの内
部全体に亘って導電性物質を形成したが、例えば第７図
に示すように、開口4c,4dの底部にのみ導電性物質を形
成しても、これらの開口4c,4bの深さが実効的に減少す
る結果アスペクト比が小さくなるので、上述の実施例と
同様に開口4c,4dの近傍における配線14a,14b（図示せ
ず）の断線を防止することができる。Further, in the above-mentioned embodiment, the conductive material is formed over the entire inside of the openings 4c, 4d of the PSG film 4, but as shown in FIG. 7, for example, the conductive material is formed only at the bottoms of the openings 4c, 4d. However, since the aspect ratio is reduced as a result of the effective reduction of the depth of these openings 4c, 4b, the wirings 14a, 14b (not shown) near the openings 4c, 4d are formed as in the above-described embodiment. It is possible to prevent the disconnection.
なお上述の実施例においては、第5A図に示す工程におい
てPSG膜４の表面を平坦化したが、この平坦化は必ずし
も必要ではなく、必要に応じて省略可能である。Although the surface of the PSG film 4 is flattened in the step shown in FIG. 5A in the above-mentioned embodiment, this flattening is not always necessary and can be omitted if necessary.
ところで、以上の実施例及び変形例の何れにおいても、
導電膜10を形成した後にAl膜11を形成しているが、これ
らの順序を逆にして、Al膜11を形成した後に導電膜10を
形成しようとすると、第２図に示した様に、開口4aのア
スペクト比が高くてAl配線５に庇状の部分が形成された
状態で有機溶剤等を塗布することになる場合があり、有
機溶剤等であっても開口4aを完全には埋めることができ
ないおそれがある。従って、Al膜11を形成した後に導電
膜10を形成するという方法を採用することはできない。By the way, in any of the above-mentioned examples and modifications,
Although the Al film 11 is formed after the conductive film 10 is formed, if the order of these is reversed and the conductive film 10 is formed after the Al film 11 is formed, as shown in FIG. There is a case where the organic solvent or the like is applied in a state where the opening 4a has a high aspect ratio and the eaves-shaped portion is formed on the Al wiring 5. Even if the organic solvent is used, the opening 4a should be completely filled. May not be possible. Therefore, the method of forming the conductive film 10 after forming the Al film 11 cannot be adopted.
発明の効果 本発明に係る半導体装置の製造方法によれば、特に、少
なくとも第２の絶縁膜の開口を埋めるように、流動性を
有する導電性物質を形成し且つ固化した後に、第２の配
線を形成しているので、開口のアスペクト比が高い場合
においても、上記開口の近傍において配線の断線を生ず
ることなく第２の配線を形成することができる。EFFECTS OF THE INVENTION According to the method for manufacturing a semiconductor device of the present invention, in particular, after the conductive material having fluidity is formed and solidified so as to fill at least the opening of the second insulating film, the second wiring is formed. Therefore, even if the aspect ratio of the opening is high, the second wiring can be formed in the vicinity of the opening without disconnection of the wiring.
第１図及び第２図は従来の半導体装置における層間絶縁
膜の開口近傍の配線の形状を示す断面図、第３図は従来
の半導体装置における層間絶縁膜の開口の上端に大きな
テーパが形成されている状態を示す断面図、第４図は従
来の半導体装置における層間絶縁膜に互いに深さが異な
る開口が形成されている状態を示す断面図、第5A図〜第
5E図は本発明に係る半導体装置の製造方法の一実施例を
工程順に示す断面図、第6A図〜第6C図は本発明の変形例
を説明するための第5C図〜第5E図と同様な断面図、第７
図は第6A図〜第6C図に示す変形例とは異なる変形例を示
す第5C図と同様な断面図である。 なお図面に用いた符号において、 ２……SiO2膜（第１の絶縁膜） 2c……段差 3,3a,3b……Al配線（第１の配線） ４……PSG膜（第２の絶縁膜） 4a,4c,4d……開口 ５……Al配線 5a,5b……Al配線（第２の配線） 10……導電膜（固化された導電性物質） 11a,11b……Al膜 14a,14b……配線（第２の配線） である。1 and 2 are cross-sectional views showing the shape of the wiring near the opening of the interlayer insulating film in the conventional semiconductor device, and FIG. 3 shows a large taper formed at the upper end of the opening of the interlayer insulating film in the conventional semiconductor device. 5A to 5C are sectional views showing a state in which openings having different depths are formed in the interlayer insulating film in the conventional semiconductor device.
FIG. 5E is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS. 6A to 6C are similar to FIGS. 5C to 5E for explaining a modification of the present invention. Sectional view, No. 7
The figure is a sectional view similar to FIG. 5C showing a modification different from the modifications shown in FIGS. 6A to 6C. In the reference numerals used in the drawings, 2 ... SiO 2 film (first insulating film) 2c ... steps 3, 3a, 3b ... Al wiring (first wiring) 4 ... PSG film (second insulating film) Film) 4a, 4c, 4d …… Opening 5 …… Al wiring 5a, 5b …… Al wiring (second wiring) 10 …… Conductive film (solidified conductive material) 11a, 11b …… Al film 14a, 14b ... Wiring (second wiring).
Claims (1)
程と、 上記第１の配線及び上記第１の絶縁膜を被覆する第２の
絶縁膜を形成する工程と、 上記第１の配線に達する開口を上記第２の絶縁膜に形成
する工程と、 少なくとも上記開口を埋めるように、流動性を有する導
電性物質を形成する工程と、 流動性を有する上記導電性物質を固化させる工程と、 固化された上記導電性物質と接続されている第２の配線
を、上記固化の後に上記第２の絶縁膜上に形成する工程
とをそれぞれ具備することを特徴とする半導体装置の製
造方法。1. A step of forming a first wiring on a first insulating film; a step of forming a second insulating film covering the first wiring and the first insulating film; Forming an opening reaching the first wiring in the second insulating film; forming a conductive material having fluidity so as to fill at least the opening; and solidifying the conductive material having fluidity And a step of forming a second wiring connected to the solidified conductive material on the second insulating film after the solidification, respectively. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59124941A JPH0691086B2 (en) | 1984-06-18 | 1984-06-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59124941A JPH0691086B2 (en) | 1984-06-18 | 1984-06-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS614244A JPS614244A (en) | 1986-01-10 |
| JPH0691086B2 true JPH0691086B2 (en) | 1994-11-14 |
Family
ID=14897976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59124941A Expired - Lifetime JPH0691086B2 (en) | 1984-06-18 | 1984-06-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691086B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6215834A (en) * | 1985-07-15 | 1987-01-24 | Nec Corp | Multilayer interconnection |
| JPS63146539U (en) * | 1987-03-17 | 1988-09-27 | ||
| US11370579B2 (en) | 2017-02-07 | 2022-06-28 | Ball Corporation | Tapered metal cup and method of forming the same |
| US10875076B2 (en) | 2017-02-07 | 2020-12-29 | Ball Corporation | Tapered metal cup and method of forming the same |
| USD950318S1 (en) | 2018-05-24 | 2022-05-03 | Ball Corporation | Tapered cup |
| USD906056S1 (en) | 2018-12-05 | 2020-12-29 | Ball Corporation | Tapered cup |
| USD953811S1 (en) | 2020-02-14 | 2022-06-07 | Ball Corporation | Tapered cup |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085514A (en) * | 1983-10-17 | 1985-05-15 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-06-18 JP JP59124941A patent/JPH0691086B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS614244A (en) | 1986-01-10 |
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| EXPY | Cancellation because of completion of term |