JPH02254731A - Hetero-junction type field effect transistor - Google Patents

Hetero-junction type field effect transistor

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Publication number
JPH02254731A
JPH02254731A JP7756589A JP7756589A JPH02254731A JP H02254731 A JPH02254731 A JP H02254731A JP 7756589 A JP7756589 A JP 7756589A JP 7756589 A JP7756589 A JP 7756589A JP H02254731 A JPH02254731 A JP H02254731A
Authority
JP
Japan
Prior art keywords
layer
inp substrate
lattice constant
yas
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7756589A
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Japanese (ja)
Other versions
JPH088354B2 (en
Inventor
Kaoru Inoue
薫 井上
Kurisutofu Aruman Jiin
ジーン クリストフ アルマン
Toshinobu Matsuno
年伸 松野
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Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Priority to JP1077565A priority Critical patent/JPH088354B2/en
Publication of JPH02254731A publication Critical patent/JPH02254731A/en
Publication of JPH088354B2 publication Critical patent/JPH088354B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable a novel hetero-junction structure lightening the restriction on the lattice alignment to be manufactured by a method wherein InGaAs, InAlAs in larger lattice constant than that of an InP substrate are used in the region in film thickness exceeding the film thickness. CONSTITUTION:A non-doted InyAl1-yAs layer 11 in larger lattice constant than that of an InP substrate 1, another non-doped InxGa1-xAs layer 12, the other non-doped InyAl1-yAs thin film 13 and an N type InyAl1-yAs layer 14 respectively in the same lattice constant as that of the the said layer 11 are successively formed on the semiinsulating InP substrate 1. Then, the whole thickness of the layers formed on the InP substrate 1 is set up thicker than the film thickness determined by the difference from the lattice constant of the semiinsulating InP substrate 1. Through these procedures, the restriction on the crystal deposition such as the lattice alignment with the InP substrate 1 can be lightened so as to attain the simplification, the mass production and the price cut down of the crystal deposition process.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ヘテロ接合構造を用いた電界効果型トランジ
スタの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a field effect transistor using a heterojunction structure.

従来の技術 ノンドープのGaAs層上にN型AeGaAs層を形成
したヘテロ接合構造では、ヘテロ接合界面のGaAs側
に高易動度の2次元電子ガスが形成され、これを利用し
て高電子移動度トランジスタ(HEMT)と呼ばれるヘ
テロ接合型電界効果トランジスタが発明された。このH
E M Tの特性を向上させるために材料面・構造面か
ら多(の研究がなされている。材料面ではGaAsのか
わりにInPに格子整合したI no、s3c ao、
47A sを用い、AeGaAsのかわりにInAeA
sを用いたものが、At!GaAs/GaAs系HEM
Tよりも高い電子移動度、高い電子飽和速度、高い2次
元電子ガス濃度を示し、高速デバイスとして有望視され
ている。しかしながら、InP基板上に形成したI n
GaAs/InAf! As系HEMTではInGaA
sやInAeAsの各層の格子定数がInAs組成によ
り異なるため、InP基板に格子整合するようにInA
sの組成を正確に制御しなければならないという大きな
制約があった。この制約を緩和することと、InAs組
成を高めることにより電子移動度を向上し、素子特性を
さらに向上させる目的で、InGaAs/InAeA、
s系HEMTにおいてチャンネル層となるInGaAs
層のInAs組成を0.6程度にまで高め、InGaA
s層の層厚を格子欠陥が導入されない範囲に薄く形成す
る手法が近年用いられるようになっている。このような
InGaAs歪層を用いたI nGaAs/InAe 
As系HE M Tの層構造の断面図を第3図に示す。
Conventional technology In a heterojunction structure in which an N-type AeGaAs layer is formed on a non-doped GaAs layer, a two-dimensional electron gas with high mobility is formed on the GaAs side of the heterojunction interface, and this is used to generate high electron mobility. A heterojunction field effect transistor called a transistor (HEMT) was invented. This H
In order to improve the characteristics of EMT, many studies have been conducted from the material and structural aspects.In terms of materials, INO, s3cAO, lattice matched to InP instead of GaAs,
47A s, and InAeA instead of AeGaAs.
The one using s is At! GaAs/GaAs HEM
It exhibits higher electron mobility, higher electron saturation velocity, and higher two-dimensional electron gas concentration than T, and is considered promising as a high-speed device. However, InP formed on an InP substrate
GaAs/InAf! In As-based HEMT, InGaA
Since the lattice constant of each layer of S and InAeAs differs depending on the InAs composition, InA is lattice-matched to the InP substrate.
There was a major constraint that the composition of s had to be precisely controlled. In order to alleviate this constraint and increase the InAs composition to improve electron mobility and further improve device characteristics, InGaAs/InAeA,
InGaAs which becomes the channel layer in s-based HEMT
The InAs composition of the layer is increased to about 0.6, and the InGaA
In recent years, methods have been used to reduce the thickness of the s-layer so that lattice defects are not introduced. InGaAs/InAe using such an InGaAs strained layer
FIG. 3 shows a cross-sectional view of the layer structure of the As-based HEMT.

第3図において、1は半絶縁性InP基板、2はInP
と格子整合した層厚が2000〜5000人のノンドー
プI no、52A(0,48A Sバッファー層、3
はInPと格子整合したノンドープI no、s3G 
ao、+7A s層、4はノンドープでXが0.53以
上のInGaAs 0.53でほぼ格子整合となる)、5はノンドープI 
no、52Ae 0.411A Sスペーサ層、6はN
型I no、5zAe 0.4eA 8層、7はノンド
ープI no、52Ae0.48A s層である。しか
シナカラコの構造でも、I nxG a 1−、A s
歪層4以外の2゜3.5,6.7の各層は、InP基板
に格子整合するようなInAs組成が選ばれており、結
晶成長上、格子整合の問題が大きな制約となって残って
いる。
In Fig. 3, 1 is a semi-insulating InP substrate, 2 is an InP substrate, and 2 is an InP substrate.
Non-doped Ino, 52A (0,48A S buffer layer, 3
is undoped I no, s3G lattice matched to InP
ao, +7A s layer, 4 is non-doped InGaAs with X of 0.53 or more (approximately lattice matched at 0.53), 5 is non-doped I
no, 52Ae 0.411A S spacer layer, 6 is N
Type I no, 5zAe 0.4eA 8 layers, 7 is a non-doped I no, 52Ae0.48A s layer. However, even with the structure of Shinakarako, I nxG a 1-, A s
For each of the 2°3.5 and 6.7 layers other than strained layer 4, InAs compositions are selected to lattice match the InP substrate, and the problem of lattice matching remains a major constraint on crystal growth. There is.

発明が解決しようとする課題 以上のように従来構造のInGaAs/InAeAs系
HEMTでは、チャンネル層を除いて結晶成長の各層を
InP基板と格子整合させる必要があり、結晶成長時に
おいてInAs組成を正確に制御しなければならないと
いう大きな制約があった。結晶成長の膜厚を薄くすれば
、この制約はある程度緩和されるが、通常バッファー層
2などは、InP基板からの不純物混入など、基板から
の悪影響を抑制する目的で200nm以上に形成される
ので、結晶成長層を極端に薄くすることは非現実的であ
る。
Problems to be Solved by the Invention As described above, in an InGaAs/InAeAs HEMT with a conventional structure, it is necessary to lattice match each layer of crystal growth with the InP substrate except for the channel layer, and it is necessary to accurately adjust the InAs composition during crystal growth. There were major constraints that had to be controlled. This restriction can be alleviated to some extent by reducing the thickness of the crystal growth film, but buffer layer 2 and the like are usually formed to a thickness of 200 nm or more in order to suppress adverse effects from the substrate, such as impurity contamination from the InP substrate. , it is unrealistic to make the crystal growth layer extremely thin.

本発明は、従来構造のI nGaAs/I nAe A
s系HEMTのへテロ構造における上記の格子整合の制
約を大幅に低減した新規なヘテロ接合構造を提供するも
のである。
The present invention is based on the conventional structure of InGaAs/I nAe A.
The present invention provides a novel heterojunction structure in which the above-mentioned lattice matching constraints in the heterostructure of an s-based HEMT are significantly reduced.

従来、InP基板上に結晶成長したI nGaAs/I
nAeAsへテロ構造では、良好な電気的特性を得るた
めにInGaAsやInAeAsの格子定数をInP基
板と整合させる必要があると考えられていた。また、結
晶成長する膜の格子定数を基板の格子定数からずらした
場合には、格子定数のずれに対応した臨界膜厚以下に成
長膜厚を限定しなければ、良好な電気特性の成長膜が得
られないと考えられていた。
Conventionally, InGaAs/I crystals were grown on InP substrates.
In the nAeAs heterostructure, it was considered necessary to match the lattice constant of InGaAs or InAeAs with that of the InP substrate in order to obtain good electrical characteristics. Furthermore, when the lattice constant of the crystal-grown film is shifted from that of the substrate, the grown film with good electrical properties must be limited to a critical film thickness that corresponds to the shift in the lattice constant. It was thought that it could not be obtained.

本発明者らは、InP基板上にInGaAs/InAe
As系HEMTのへテロ構造を広いInAs組成比の領
域で作製し、その電気的特性を比較検討した結果、臨界
膜厚以上の領域においても良好な電気的特性が得られる
ことを見出した。
The present inventors have developed an InGaAs/InAe film on an InP substrate.
As a result of fabricating As-based HEMT heterostructures in a wide range of InAs composition ratios and comparing their electrical properties, it was found that good electrical properties can be obtained even in a region where the thickness exceeds the critical film thickness.

課題を解決するための手段 本発明は、このような発見に基づ(ものであり、InP
基板よりも格子定数が大きいInGaAs。
Means for Solving the Problems The present invention is based on such discoveries, and is based on InP.
InGaAs has a larger lattice constant than the substrate.

InAeAsを臨界膜厚を越えた膜厚領域で積極的に用
いるものである。この際にチャンネル層となるInGa
As層とこの直下に設けたInAeAs層の格子定数は
ほぼ整合がとれた構造とすることが重要であり、このよ
うな構造を用いることにより、InP基板に格子整合さ
せた場合よりも、より高い電子移動度をもつl nGa
As/I nAe As系HE M T構造を得ること
ができる。
InAeAs is actively used in a film thickness region exceeding the critical film thickness. At this time, InGa becomes the channel layer.
It is important to have a structure in which the lattice constants of the As layer and the InAeAs layer provided directly below are almost matched, and by using such a structure, the lattice constants of the As layer and the InAeAs layer provided directly below are higher than when lattice-matched to the InP substrate. l nGa with electron mobility
An As/I nAe As-based HEMT structure can be obtained.

また、チャンネル層となるInGaAs層の格子定数が
、その直下に設けられたInGaAs層の格子定数より
も大きい場合には、InGaAs層の層厚を両層の格子
定数差から決定される臨界膜厚よりも薄くすることによ
り良好な電気特性を得ることができることも実験より明
らかになった。
In addition, when the lattice constant of the InGaAs layer serving as the channel layer is larger than the lattice constant of the InGaAs layer provided directly below it, the layer thickness of the InGaAs layer is determined from the critical film thickness determined from the lattice constant difference between the two layers. Experiments have also revealed that good electrical characteristics can be obtained by making the film thinner than the above.

本発明は以上のような実験結果に基づ(ものである。The present invention is based on the above experimental results.

作用 InP基板と格子定数が大きく異なるInGaAs/I
nAl2sへテロ構造が、何故良好な電気的特性を示す
かは明確でない。InP基板よりも格子定数が小さいI
 nGaAs/I nAe Asへテロ構造では、電気
的特性は著しく劣化することから、InP基板より格子
定数が大きいInGaAs/fnAeAsヘテロ構造で
は、結晶中に依存する欠陥があまり電気伝導に悪影響を
及ぼさないものと考えられる。推測ではあるが、InP
基板よりも格子定数の大きいInGaAs/InAe 
Asへテロ構造ではInP基板とこのへテロ構造の界面
付近に欠陥が主として閉じ込められ、表面側へは伸びて
いかな(なるものと考えられる。
InGaAs/I has a lattice constant significantly different from that of the working InP substrate.
It is not clear why the nAl2s heterostructure exhibits good electrical properties. I has a smaller lattice constant than the InP substrate
In the nGaAs/I nAe As heterostructure, the electrical properties are significantly degraded, so in the InGaAs/fnAeAs heterostructure, which has a larger lattice constant than the InP substrate, defects depending on the crystal do not have much of a negative effect on electrical conduction. it is conceivable that. Although it is a guess, InP
InGaAs/InAe with a larger lattice constant than the substrate
In the As heterostructure, defects are mainly confined near the interface between the InP substrate and this heterostructure, and are thought to extend toward the surface.

実施例によって、より詳細に説明するが、本発明による
InGaAs/InAl2 Asへテロ構造のInAs
組成および膜厚のとり得る値の範囲はきわめて広範囲で
あり、本発明は従来困難と考えられていたI nGaA
s/I nA+2 Asへテロ構造の結晶成長を容易に
し、この系の成長の量産化、低価格に大きく寄与するも
のである。
As will be explained in more detail by way of examples, InAs of the InGaAs/InAl2As heterostructure according to the present invention
The range of values that the composition and film thickness can take is extremely wide, and the present invention can be applied to InGaA, which was previously thought to be difficult.
This facilitates crystal growth of the s/I nA+2 As heterostructure and greatly contributes to mass production and low cost of growth of this system.

実施例 本発明の第1の実施例を11図に従って説明する。第1
図(a)は、InP基板1に分子線エピタキシー法を用
いて結晶成長したInGaAs/InAgAs系HEM
T橘造の断面構造図を示すものである。半絶縁性InP
基板1に、ノンドープのI nyAe +−yAs層1
1をW、の膜厚に形成し、次に、I nxG a 1−
XA 8層12をW2の膜厚に形成する。その上に、ノ
ンドープのI nyAf21−y A sスペーサ層1
3を例えば30A形成し、その上に、N形1 ny A
 Q 1−y、A s層14を300A形成した。 I
a  Ga−x  As層12はI ny Ae l−
y As層11にほぼ格子整合させている。つまりX 
zyの状態とした。15はショットキー電極形成用のキ
ャップ層であり、薄膜のGaAsやAeGaASなどを
用いる。この時、yをInP基板1に格子整合する0、
52から0.72まで変化させると同時に、W、とW2
の膜厚の和を種々変化させてヘテロ構造の特性を調べた
。第1図(b)はその結果を示しているが、斜線の領域
において、室温での移動度が10’cli?/V、Sを
十分越える寓い値を示した。第1図(b)1こおいて破
線は、InP基板との格子定数の差から計算される臨界
膜厚を示しているが、実際に実験から得られる電気特性
の良好な領域は、はるかに広い範囲であることがわかる
Embodiment A first embodiment of the present invention will be described with reference to FIG. 1st
Figure (a) shows an InGaAs/InAgAs-based HEM grown on an InP substrate 1 using molecular beam epitaxy.
It shows a cross-sectional structural diagram of T Tachibana-zukuri. semi-insulating InP
A non-doped I nyAe +-yAs layer 1 is provided on the substrate 1.
1 to a film thickness of W, and then InxG a 1-
The XA 8 layer 12 is formed to a thickness of W2. On top of that, a non-doped I nyAf21-y As spacer layer 1
3 is formed, for example, 30A, and on top of that, N type 1 ny A
Q 1-y, As layer 14 was formed with a thickness of 300A. I
a Ga-x As layer 12 is I ny Ae l-
y It is almost lattice matched to the As layer 11. In other words, X
zy state. 15 is a cap layer for forming a Schottky electrode, and a thin film of GaAs, AeGaAS, or the like is used. At this time, 0, which lattice matches y to the InP substrate 1,
At the same time as changing from 52 to 0.72, W, and W2
The characteristics of the heterostructure were investigated by varying the sum of the film thicknesses. Figure 1(b) shows the results, and in the shaded area, the mobility at room temperature is 10'cli? /V,S showed a value well in excess of S. The dashed line in Figure 1(b)1 shows the critical film thickness calculated from the difference in lattice constant with the InP substrate, but the region with good electrical properties actually obtained from experiments is much wider. It can be seen that the range is wide.

しかもy=0.72の時であっても、1μm程度の膜厚
までは10’cj/V、Sという高い移動度を示してお
り、実用上この0.72の組成においても十分厚い膜の
形成が可能であることがわかる。
Moreover, even when y=0.72, it shows a high mobility of 10'cj/V,S up to a film thickness of about 1 μm, and in practice, even with a composition of 0.72, it is possible to form a sufficiently thick film. It can be seen that formation is possible.

本実施例では、I nxG a 1−xA S層厚(W
2)は典型的には0.1μmを用いた。本実施例の特徴
は、InP基板と格子整合しないInGaAs/InA
l2sへテロ構造の全体の膜厚く基板1上の層11〜1
5全体の膜厚)がInPとの格子定数差で決められる臨
界膜厚を越えていることと、ヘテロ構造を構成するI 
nGaAs層とInAs組成層のそれぞれが互いに格子
整合していることである。
In this example, InxG a 1-xA S layer thickness (W
2) typically used 0.1 μm. The feature of this example is that InGaAs/InA which is not lattice matched to the InP substrate
The entire film thickness of the l2s heterostructure is the layer 11 to 1 on the substrate 1.
5) exceeds the critical thickness determined by the lattice constant difference with InP, and the I
The nGaAs layer and the InAs composition layer are lattice matched to each other.

本発明の第2の実施例は、第1図(a)の断面構造にお
ける半絶縁性InP基板1とノンドープI ny/l 
1−yA、 9 N 11の間に、InP基板1と格子
整合させたノンドープI no、5zAeo、4aA 
sバッファー層を挿入したものである。通常InP基板
は結晶品質が十分でな(、結晶成長した層に基板から不
要な不純物等が取り込まれる。これを除く意図からバッ
ファー層を導入することが望まれるが、本実施例では膜
厚が100OA−5000AのノンドープI no、s
2G ao、4eA s層をInP基板1と層11の間
に挿入した。その結果は第1図(b)の斜線領域におい
て、やはり良好なHE M T構造を得られることを示
した。従って、第1図(a)の半絶縁性InP基板1と
ノンドープI nyAel−yAs層110間に基板と
格子整合したバッファー層を導入しても何ら変化はない
ことがわかる。このバッファー層は臨界膜厚の範囲であ
れば、InP基板よりも格子定数が多少大きくとも良い
ことは言うまでもない。
A second embodiment of the present invention has a semi-insulating InP substrate 1 with a cross-sectional structure shown in FIG. 1(a) and a non-doped I ny/l
Non-doped Ino, 5zAeo, 4aA lattice-matched to the InP substrate 1 between 1-yA, 9N11
s buffer layer is inserted. Normally, InP substrates do not have sufficient crystal quality (unnecessary impurities, etc. are introduced from the substrate into the crystal-grown layer. It is desirable to introduce a buffer layer to remove this, but in this example, the film thickness is 100OA-5000A non-doped I no,s
A 2G ao, 4eA s layer was inserted between InP substrate 1 and layer 11. The results showed that a good HEMT structure could still be obtained in the shaded area in FIG. 1(b). Therefore, it can be seen that there is no change even if a buffer layer lattice-matched to the substrate is introduced between the semi-insulating InP substrate 1 and the non-doped InyAel-yAs layer 110 in FIG. 1(a). It goes without saying that this buffer layer may have a somewhat larger lattice constant than the InP substrate as long as it is within the critical thickness range.

本発明の第3の実施例を第2図を用いて説明する。第2
図において21は層厚が3000A程度のノンドープI
 no、52A90.48A Sバッファー層であり、
第2の実施例で説明したように、特に本発明において必
要なものではない。11はI nyAel−yAs層で
y>0.!52かつ層厚がInP基板との格子定数差で
決まる臨界膜厚より大きいものとした。22はI n、
Ae 1−yA 9層11より格子定数が大きいI n
、G’a 1−、A s層で、I n、Ael−、A 
9層11との伝導帯不連続値をより太き(する目的で、
InAs組成を太き(したものである。すなわちy<z
としている。このようなI nzG a 1−、A s
層を用いた場合には、層22のInAs組成2によって
電気的特性が太き(変化し、I nzG a 1−zA
 s層厚をあまり大きくできないことが実験より示され
た。この場合、yと2によって決定される臨界膜厚より
も、In、Ga1−、As層を薄く形成する必要がある
A third embodiment of the present invention will be described using FIG. 2. Second
In the figure, 21 is a non-doped I with a layer thickness of about 3000A.
no, 52A90.48A S buffer layer,
As explained in the second embodiment, this is not particularly necessary in the present invention. 11 is an InyAel-yAs layer with y>0. ! 52 and the layer thickness was greater than the critical film thickness determined by the lattice constant difference with the InP substrate. 22 is In,
Ae 1-yA 9 layers I n with larger lattice constant than 11
, G'a 1-, A s layer, In, Ael-, A
In order to make the conduction band discontinuity value thicker with layer 9 and layer 11,
InAs composition is thickened (i.e. y<z
It is said that Such I nzG a 1-, A s
In the case of using a layer 22, the electrical characteristics become thick (changed depending on the InAs composition 2 of the layer 22, and
Experiments have shown that the s-layer thickness cannot be made too large. In this case, it is necessary to form the In, Ga1-, and As layers thinner than the critical thickness determined by y and 2.

通常チャンネル層は150A〜300A程度の膜厚でよ
いので、Zの値の上限としてyが0.65の時に0.8
程度となる。
Usually, the thickness of the channel layer is about 150A to 300A, so the upper limit of the value of Z is 0.8 when y is 0.65.
It will be about.

なお、第2図の断面構造のI nyAf! 1−yAs
As層上1 nzG a +−,A s層22の間に、
I nVAel−yAsAs層上1子整合したI nx
G a +−xA s層を挿入した構造としてもよいこ
とは容易に類推できる。
In addition, I nyAf! of the cross-sectional structure shown in FIG. 1-yAs
Between 1 nzG a +− on the As layer and the As layer 22,
I nx with single-child matching on I nVAel-yAsAs layer
It can be easily inferred that a structure in which a Ga + -xA s layer is inserted may also be used.

発明の効果 本発明は、InP基板上にInPと格子不整合したIn
GaAs/InA1! Asへテロ接合構造を形成する
ものであり、ヘテロ構造の層厚が格子欠陥が導入される
臨界膜厚を越えた領域であることを特徴とするが、本発
明によってInP基板との格子整合という結晶成長上の
制約が大幅に軽減されることになり、InGaAs/I
nAeAs系HEMT構造の結晶成長工程の簡易化、量
産化、低価格化に本発明は大きく寄与するものである。
Effects of the Invention The present invention provides an InP substrate with a lattice-mismatched InP substrate.
GaAs/InA1! It forms an As heterojunction structure, and is characterized in that the layer thickness of the heterostructure exceeds the critical film thickness at which lattice defects are introduced. The constraints on crystal growth are significantly reduced, and InGaAs/I
The present invention greatly contributes to the simplification, mass production, and cost reduction of the crystal growth process of nAeAs-based HEMT structures.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の第1の実施例の電界効果型トラ
ンジスタの断面図、第1図(b)は同トランジスタにお
けるInAs組成と層厚の関係図、第2図は本発明の第
2の実施例の電界効果型トランジスタの断面図、第3図
は従来の電界効果型トランジスタの断面図である。 1・・・・・・半絶縁性InP基板、11・・・・・・
ノンドープI nyA eI−yA s il、12・
・・・・・ノンドープI nxG al−xA s層、
13・・・・・・ノンドープI nyAel−、A s
スペーサ層、14・・・・・・N型I nyAe +−
yAs層、15・・・・・・ショットキー電極形成用キ
ャップ層、16・・・・・・ゲート電極、17・・・・
・・ソース電極、18・・・・・・ドレイン電極、21
・・・・・・ノンドープI no、52Aeo4aAs
バツフア一層、22・・・・・・ノンドープI nzG
 a I−zA s層。 代理人の氏名 弁理士 粟野重孝 ほか1名θ、s2 ρ57 σ32
FIG. 1(a) is a cross-sectional view of a field-effect transistor according to a first embodiment of the present invention, FIG. 1(b) is a diagram showing the relationship between InAs composition and layer thickness in the same transistor, and FIG. A cross-sectional view of the field-effect transistor of the second embodiment, and FIG. 3 is a cross-sectional view of a conventional field-effect transistor. 1... Semi-insulating InP substrate, 11...
Non-doped InyA eI-yA sil, 12.
...Non-doped InxGal-xAs layer,
13...Non-doped InyAel-, As
Spacer layer, 14...N type I nyAe +-
yAs layer, 15... Schottky electrode formation cap layer, 16... gate electrode, 17...
... Source electrode, 18 ... Drain electrode, 21
・・・・・・Non-doped I no, 52Aeo4aAs
Batsuhua, 22...Non-doped InzG
a I-zA s layer. Name of agent: Patent attorney Shigetaka Awano and one other person θ, s2 ρ57 σ32

Claims (2)

【特許請求の範囲】[Claims] (1)半絶縁性InP基板上にこのInP基板よりも大
きな格子定数を有するノンドープ In_yAl_1_−_yAs層とこのIn_yAl_
1_−_yAs層と格子定数がほぼ等しいノンドープの In_xGa_1_−_xAs層と、ノンドープのIn
_yAl_1_−_yAs薄層およびN形のIn_yA
l_1_−_yAs層が順次形成されてなり、かつ前記
InP基板上に形成された層厚の全体が、前記半絶縁性
InP基板との格子定数差より決定される臨界膜厚より
も厚く設定されているヘテロ接合構造を有してなるヘテ
ロ接合型電界効果トランジスタ。
(1) A non-doped In_yAl_1_-_yAs layer with a larger lattice constant than this InP substrate on a semi-insulating InP substrate and this In_yAl_
A non-doped In_xGa_1_-_xAs layer whose lattice constant is almost the same as that of the 1_-_yAs layer, and a non-doped In_xGa_1_-_xAs layer.
_yAl_1_-_yAs thin layer and N-type In_yA
l_1_-_yAs layers are sequentially formed, and the total thickness of the layers formed on the InP substrate is set to be thicker than a critical film thickness determined from a lattice constant difference with the semi-insulating InP substrate. A heterojunction field effect transistor having a heterojunction structure.
(2)半絶縁性InP基板上に、前記InP基板よりも
大きな格子定数を有し、前記InP基板との格子定数の
差から決められる臨界膜厚よりも厚い膜厚を有するノン
ドープの In_yAl_1_−_yAs層と、このIn_yAl
_1_−_yAs層よりも格子定数が大きいノンドープ
の In_zGa_1_−_zAsの薄層と、ノンドープの
In_yAl_1_−_yAs薄層およびN形のIn_
yAl_1_−_yAs層が順次形成されてなるヘテロ
接合構造を有してなるヘテロ接合型電界効果トランジス
タ。
(2) Non-doped In_yAl_1_-_yAs having a larger lattice constant than the InP substrate and thicker than the critical film thickness determined from the difference in lattice constant with the InP substrate on a semi-insulating InP substrate. layer and this In_yAl
A thin layer of non-doped In_zGa_1_-_zAs with a larger lattice constant than the _1_-_yAs layer, a thin layer of non-doped In_yAl_1_-_yAs and an N-type In_
A heterojunction field effect transistor having a heterojunction structure in which yAl_1__yAs layers are sequentially formed.
JP1077565A 1989-03-28 1989-03-28 Heterojunction field effect transistor Expired - Lifetime JPH088354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1077565A JPH088354B2 (en) 1989-03-28 1989-03-28 Heterojunction field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1077565A JPH088354B2 (en) 1989-03-28 1989-03-28 Heterojunction field effect transistor

Publications (2)

Publication Number Publication Date
JPH02254731A true JPH02254731A (en) 1990-10-15
JPH088354B2 JPH088354B2 (en) 1996-01-29

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ID=13637535

Family Applications (1)

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Country Status (1)

Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322541A (en) * 1989-06-20 1991-01-30 Sanyo Electric Co Ltd Epitaxial wafer
WO2012073539A1 (en) * 2010-12-01 2012-06-07 住友電気工業株式会社 Light-receiving element, detector, semiconductor epitaxial wafer, and method for producing these
JP2012256826A (en) * 2010-12-01 2012-12-27 Sumitomo Electric Ind Ltd Light-receiving element, semiconductor epitaxial wafer, manufacturing method therefor and detector
WO2013179901A1 (en) * 2012-05-30 2013-12-05 住友電気工業株式会社 Light receiving element, semiconductor epitaxial wafer, detecting apparatus, and light receiving element manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466972A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Heterojunction fet
JPS6474765A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Hetero-junction fet

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466972A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Heterojunction fet
JPS6474765A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Hetero-junction fet

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322541A (en) * 1989-06-20 1991-01-30 Sanyo Electric Co Ltd Epitaxial wafer
WO2012073539A1 (en) * 2010-12-01 2012-06-07 住友電気工業株式会社 Light-receiving element, detector, semiconductor epitaxial wafer, and method for producing these
JP2012256826A (en) * 2010-12-01 2012-12-27 Sumitomo Electric Ind Ltd Light-receiving element, semiconductor epitaxial wafer, manufacturing method therefor and detector
WO2013179901A1 (en) * 2012-05-30 2013-12-05 住友電気工業株式会社 Light receiving element, semiconductor epitaxial wafer, detecting apparatus, and light receiving element manufacturing method
US9391229B2 (en) 2012-05-30 2016-07-12 Sumitomo Electric Industries, Ltd. Light receiving element, semiconductor epitaxial wafer, detecting device, and method for manufacturing light receiving element

Also Published As

Publication number Publication date
JPH088354B2 (en) 1996-01-29

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