JPS63284869A - Heterojunction field-effect semiconductor device - Google Patents
Heterojunction field-effect semiconductor deviceInfo
- Publication number
- JPS63284869A JPS63284869A JP11911487A JP11911487A JPS63284869A JP S63284869 A JPS63284869 A JP S63284869A JP 11911487 A JP11911487 A JP 11911487A JP 11911487 A JP11911487 A JP 11911487A JP S63284869 A JPS63284869 A JP S63284869A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- semiconductor thin
- film layer
- ingaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000010409 thin film Substances 0.000 claims abstract description 69
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000203 mixture Substances 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 25
- 230000017105 transposition Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 241000837181 Andina Species 0.000 description 1
- 101100480530 Danio rerio tal1 gene Proteins 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 101100480538 Mus musculus Tal1 gene Proteins 0.000 description 1
- 101100312945 Pasteurella multocida (strain Pm70) talA gene Proteins 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、２次元電子ガス層を利用して高速化を図つ
九ヘテロ接合゛鑞界効果半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to an improvement in a nine-heterojunction field effect semiconductor device that utilizes a two-dimensional electron gas layer to achieve higher speed.
（従来の技術）
現在、ヘテロ接合電界効果半導体装置として実現してい
るのは、主にＧａＡｌ！Ａｓ／ＧａＡｓ系である。これ
は高濃度にドーグされたＧａ Ｍ Ａｓ層を電子供給層
とし、ＧａＡｓ層をチャンネルとする所謂選択ドーグ構
造でラシ、また、このような構造に加えて前記Ｇａ Ａ
ｔ Ａｌ１層を界面近傍で量子井戸構造とするものも知
られている。(Prior Art) Currently, heterojunction field effect semiconductor devices are mainly made of GaAl! It is As/GaAs based. This is a so-called selective dog structure in which a GaM As layer doped with high concentration is used as an electron supply layer and the GaAs layer is used as a channel.
It is also known that the tAl1 layer has a quantum well structure near the interface.
しかしながら、このＧａＡｌ！Ａｓ／ＧａＡａ系電界効
果半導体装置も完成されたものではなく、まだ多くの問
題点を持っている。However, this GaAl! As/GaAa field effect semiconductor devices are not yet complete and still have many problems.
Ｇａ、Ｍ’Ａｓ層に添加したｎ型不純物はＤ−Ｘ中心と
呼ばれる深い準位を形成し素子特性を劣化させる。The n-type impurity added to the Ga and M'As layers forms a deep level called a DX center and deteriorates device characteristics.
Ｇａ Ａｌ！Ａｌ１層には３ Ｘ ＩＱ”ｍ−”以上Ｓ
ｔを添加するのが困難であり、２次元電子濃度も８ Ｘ
１０１１．−ｚよシも大きくするのは困難で、それが
素子特性の性能限界の一因となっている。GaAl! 3 x IQ”m-” or more S for Al1 layer
It is difficult to add t, and the two-dimensional electron concentration is also 8
1011. It is difficult to increase the -z ratio, which is one of the reasons for the performance limits of the device characteristics.
石川知則氏ら（電子通信学会技術研究報告ＥＤ８６−５
６ 、 Ｐ５１ ）はプレーナドープなどの不純物添加
法の改善などにより、シートキャリア増加の努力をして
いるが、 １，２Ｘ１０１２ｗ−”以上を達成するの
は困難であった。Tomonori Ishikawa et al. (IEICE Technical Research Report ED86-5
6, P51) has made efforts to increase the number of sheet carriers by improving impurity addition methods such as planar doping, but it has been difficult to achieve 1,2 x 1012w-'' or more.
−１、Ｉ ｎ ＡＩ ＡｌｌにはＩ Ｘ １０”３−”
以上添加するのが容易にできるなどの利点が”）、Ｉｎ
Ｐ基板上に格子定数がマツチし九Ｉｎｏ、ｓｓ Ｇａａ
ｔｙ Ａｓ／Ｉｎａｓ＊ Ａｌｈａｓ Ａｓ系電界効果
半導体素子（以下ＦＥＴという）が試作され、良好な特
性を得ている（ Ｋ、Ｈｉｒｏａｅ ｅｔ ａｔ。-1, I x 10"3-" for I n AI All
The advantages include that it is easy to add
The lattice constants match on the P substrate, 9 Ino, ss Gaa
ty As/Inas* Alhas As-based field effect semiconductor devices (hereinafter referred to as FETs) have been prototyped and have obtained good characteristics (K, Hiroae et at.
インスト フイゼツクス コンファレンス、 Ｉｎａｔ
Ｐｈｙｓ （：ｏｎｆＳｅｒ 、 Ｎ１１７９ Ｃｈ
ａｐｔｅｒ １０ （１９８５） Ｐ５２９ ）。Instrument Physics Conference, Inat
Phys (:onfSer, N1179 Ch
apter 10 (1985) P529).
すなわち、 Ｉｎ混晶系では、 ＧａＡａに比べ大き
な電子移動度μｎ 大きな電子速度Ｖ、が得られること
、２次元電子ガス密度が２ Ｘ １０１０ｌ２”とＧａ
Ａｓ／ＧａＡｌＡｓ系に比べ２．５倍程大きくできるこ
となどの利点を持つ。That is, in the In mixed crystal system, larger electron mobility μn and larger electron velocity V can be obtained compared to GaAa, and the two-dimensional electron gas density is 2 x 1010 l2'' and Ga
It has the advantage that it can be made about 2.5 times larger than the As/GaAlAs system.
しかしながら、ＧａＡａはＩｎＰなどの他の化合物半導
体に比べ研究開発も古く、グロセス技術も確立しておシ
、良質のＧａＡｓ基板が入手でき、この種の半導体装置
を生産ラインにのせて量産する際の大きな利点になるも
のと考えられる。However, compared to other compound semiconductors such as InP, GaAa has been researched and developed for a long time, and its production technology has been established. This is considered to be a big advantage.
そこで、半導体基板としてＱａ Ａｌ！ｌを用い、その
上に成長させる半導体層としては、 Ｉｎ系混晶を使
用することができれば好都合である。ＧａＡｓの格子定
数が５．５６４スなのに対し、ＩｎＡａは６．０５８λ
でめるため、ＧａＡｓ基板上にＩｎ系混晶を単純に成長
させると、格子定数不整合によるミスフィツト転位が発
生する。Therefore, as a semiconductor substrate, QaAl! It would be advantageous if an In-based mixed crystal could be used as the semiconductor layer grown thereon. The lattice constant of GaAs is 5.564, while that of InAa is 6.058λ.
If an In-based mixed crystal is simply grown on a GaAs substrate to prevent this, misfit dislocations will occur due to lattice constant mismatch.
しかしながら、ＧａＡｓ基板上に格子定数が一致しなく
てもミスフィツト欠陥の発生しないようにＩｎＧａＡｓ
などのＩｎ混晶薄膜を成長できる。後述するこの発明の
発明者らによってＩｎの組成比が０．２で２５０λ程度
の厚さまでミスフィツト欠陥が発生しないことが確認さ
れている。However, in order to prevent misfit defects from occurring even if the lattice constants do not match on the GaAs substrate, InGaAs is
It is possible to grow In mixed crystal thin films such as The inventors of the present invention, which will be described later, have confirmed that misfit defects do not occur up to a thickness of about 250λ when the In composition ratio is 0.2.
（発明が解決しようとする問題点）
従来はミスフィツト欠陥の発生とＩｎ混晶膜の成長条件
の関係が把握できておらず、ＧａＡｔＡ１層にドーグし
ＩｎＧａＡｓ ｍ ｔ−チャンネル層に応用するにとど
まってい次。(Problems to be Solved by the Invention) Conventionally, the relationship between the occurrence of misfit defects and the growth conditions of In mixed crystal films was not understood, and the application to the InGaAs m t-channel layer was limited to doping in a single GaAtA layer. Next.
Ｆ Ｅ Ｔ ０４！性パラメータである電流駆動力ｆｍ
は２次元電子層のシートキャリア密度にほぼ比例する形
で増加することが知られている。しかしながら、従来型
のＧａ ｌ’Ｊ Ａ１１に不純物をドーグしたヘテロ接
合ＦＥＴでは、シートキャリア密度の高いものが得られ
ないなどの欠点が６つ九。FET 04! Current driving force fm, which is a physical parameter
is known to increase approximately in proportion to the sheet carrier density of the two-dimensional electronic layer. However, the conventional heterojunction FET made by doping impurities into Gal'J A11 has several drawbacks, such as the inability to obtain a high sheet carrier density.
この発明は、前記従来技術がもっている問題点のうち、
ＧａＡｌＡｓに不純物をドーグしたヘテロ接合ＦＩＴで
は、シートキャリア増加の高いものが得られない点につ
いて解決し九ヘテロ接合電界効果半導体装置を提供する
ものである。This invention solves the problems of the above-mentioned prior art.
The present invention solves the problem that a heterojunction FIT in which GaAlAs is doped with impurities cannot achieve a high increase in sheet carriers, and provides a nine-heterojunction field effect semiconductor device.
（問題点を解決するための手段）
この発明はヘテロ接合電界効果半導体装置において、
ＧａＡｓ半導体基板上に１格子定数不整合によるミスフ
ィツト転位が発生しない組成比および膜厚に制御したＩ
ｎＧａＡｓ半導体薄膜層、ＧａＡ／Ａｓ半導体薄膜層、
およびＩ ｎ Ｉ’Ｊ Ａｓ半導体薄膜層を形成したも
のである。(Means for Solving the Problems) The present invention provides a heterojunction field effect semiconductor device including:
The composition ratio and film thickness of I are controlled so that misfit dislocations due to 1 lattice constant mismatch do not occur on the GaAs semiconductor substrate.
nGaAs semiconductor thin film layer, GaA/As semiconductor thin film layer,
and an I n I'J As semiconductor thin film layer.
（作用）
この発明によれば１以上のようにヘテロ接合電界効果半
導体装置を構成し九ので、信頼性が高いＧａＡｓ半導体
基板上のＩ ｎ ＡＩ Ａｓ半導体薄膜層をキャリア供
給層とし、 ＧａＡｓ層に比べ高萱度にｎ型不純物を添
加し、 ＩｎＧａＡｓ半導体薄膜層をチャンネル層と
し、ＧａＡｓ層に比べ移動度、飽和速度、ピーク速度を
大きくするとともＫＩ ＩｎＡｔＡｓ半導体薄膜層と
ＩｎＧａＡｓ半導体薄膜層との間のＧａＡｊＡａ半導体
薄膜がスペーサとなり、格子定数不整合歪を緩和し、し
かもチャンネル層となるＩｎＧａＡ３半導体薄膜層との
伝導帯でのバンドギヤラグを〜０，４ｅＶ程度と大きく
する。(Function) According to the present invention, since a heterojunction field effect semiconductor device is constructed as described above, an In AI As semiconductor thin film layer on a highly reliable GaAs semiconductor substrate is used as a carrier supply layer, and the GaAs layer is The InGaAs semiconductor thin film layer is doped with n-type impurities to a higher degree than the GaAs layer, and the mobility, saturation velocity, and peak velocity are increased compared to the GaAs layer. The GaAjAa semiconductor thin film acts as a spacer, alleviates the lattice constant mismatch strain, and increases the band gear lag in the conduction band with the InGaA3 semiconductor thin film layer, which becomes the channel layer, to about 0.4 eV.
（実施例）
以下、第１図乃至第４図に本発明装置の要部断面図、第
５図にＩｎＧａＡｓ膜における膜厚とキャリア供給密度
との関係を示す特性図及び第６図にＩｎＧａＡｓ膜にお
ける膜厚とキャリア移動度との関係を示す特性図を示し
て、本発明の詳細な説明する。(Example) Below, Figs. 1 to 4 are sectional views of essential parts of the device of the present invention, Fig. 5 is a characteristic diagram showing the relationship between film thickness and carrier supply density in an InGaAs film, and Fig. 6 is a sectional view of an InGaAs film. The present invention will be explained in detail by showing a characteristic diagram showing the relationship between film thickness and carrier mobility in .
第１図において、図示の半導体装置を製造する場合の工
程について説明する。まずＭＢＥ （分子エピタキシ）
法により半絶縁性ＧａＡｓ基板ｌ上にノンドーグＧａＡ
ｌ！Ａｓ半導体薄膜層２ｔ−約１０００人成長する。Referring to FIG. 1, steps for manufacturing the illustrated semiconductor device will be described. First, MBE (molecular epitaxy)
Non-doped GaA was deposited on a semi-insulating GaAs substrate by
l! As semiconductor thin film layer 2t - about 1000 people grow.
次に、ドーグＩ ｎｘｉ Ｇ！ＬＸ −ｘＩＡＩ半導体
薄膜層３を、例えば第６図の特性図よりキャリアの移動
度が大となる膜厚１００＾程度に形成し、さらにその上
にノンドーグＧａ Ａｊ Ａｌ半導体薄膜層４を、例え
ば４０λの厚さにスペーサ層として成長させる。Next, Dawg Inxi G! The LX-xIAI semiconductor thin film layer 3 is formed to have a thickness of, for example, about 100^, which increases carrier mobility as shown in the characteristic diagram of FIG. as a spacer layer to a thickness of .
次に、ノンドーグＩｎｙｔＡ／１−ｙｔＡｓ半導体薄膜
層５を、例えば第５図の特性図より高凹度のキャリアが
供給できる膜厚１００＾積みＸｌとＹｌが０．２ならば
、Ｉｎ液晶系の厚さを全体で３００λ程度まで厚くする
ことができる。次に、ドーグＧａ Ａｓ半導体薄膜層６
を形成する。Next, if the non-doped InytA/1-ytAs semiconductor thin film layer 5 is made with a film thickness of 100^ that can supply highly concave carriers from the characteristic diagram of FIG. The total thickness can be increased to about 300λ. Next, Dogue GaAs semiconductor thin film layer 6
form.
ここで、成長させるドーグＩｎＧａＡｓ半導体薄膜層３
のドーパントはＭＢＥでｎ型の不純物として王に使用さ
れているシリコン（Ｓｔ）である。Here, the grown InGaAs semiconductor thin film layer 3
The dopant is silicon (St), which is commonly used as an n-type impurity in MBE.
上記ドーグＧａＡ１半導体薄膜層６上には金ｒルマニウ
ム／ Ａｕ （ＡｕＧｅ／Ａｕ ）によるソース１他７
とドレイン電極８が形成されているとともに、アルミニ
ウムによるｒ−上電極９が形成されている。On the above-mentioned Dogu GaA1 semiconductor thin film layer 6 are sources 1 and 7 made of gold/rumanium/Au (AuGe/Au).
A drain electrode 8 is formed, and an r-upper electrode 9 made of aluminum is formed.
半導体基板などに格子整合しない半導体薄膜の膜厚が薄
ければ、ミスフィツト転位が発生しないことが仰られて
いる。It is said that misfit dislocations will not occur if the thickness of a semiconductor thin film that is not lattice matched to a semiconductor substrate is thin.
そこで、この発明では、上記からも明らかなように、ミ
スフィツト転位が発生しない条件下で半絶縁性Ｇａ Ａ
ｓ基板上にＧａＭＡｓ 、 ＩｎＧａＡｓ 、 ＧａＡ
Ａ’Ａｓ 。Therefore, in this invention, as is clear from the above, semi-insulating GaA
GaMAs, InGaAs, GaA on s substrate
A'As.
ＩｎＡＡ’Ａｓ 、 ＧａＡａ １１どｔ−ＭＢＥ法で
連続的に成長して形成しているので、 ＩｎＧａＡａ
（ドーグＩｎｘｘＧａｔ−ｘｘＡａ半導体薄膜層３）
とＩｎＡ／ＡＩ！ （ノンドーグＩｎｙｔ Ａｊ１−）
Ｑ Ａｓｓ半導体薄膜層５）との間にＧａ ＡＩ ＡＢ
（ノンドーグＧａ Ａｔ Ａｓ手中４体膜層４）をスペ
ーサ層として挾むことによシ、格子定数不整合を緩和で
き、しかもチャンネル層となるＩｎＧａＡｓとの伝導帯
でのバンドギヤラグを〜０，４ｅＶ程度大きくすること
ができる。Since InAA'As and GaAa 11 are formed by continuous growth using the t-MBE method, InGaAa
(Dawg InxxGat-xxAa semiconductor thin film layer 3)
and InA/AI! (Nondawg Inyt Aj1-)
Ga AI AB between Q Ass semiconductor thin film layer 5)
By sandwiching (Non-Dog Ga At As 4 body film layer 4) as a spacer layer, the lattice constant mismatch can be alleviated, and the band gear lag in the conduction band with InGaAs, which becomes the channel layer, can be reduced to about ~0.4 eV. Can be made larger.
第２図はこの発明の第２の実施例の要部を切断して示す
断面図である。この第２図においては、半絶縁性ＧａＡ
ｓ基板ｌＩ上にノンドーグＧａＡｓ半導体薄膜層１２、
ドーグＩｎｘｚＧａｌ−ｘ２Ａｓ半導体薄膜層１３、ノ
ンドーグＧａ Ａｌ！Ａ！１半導体薄膜層１４％ノンド
ーグＩｎ ｙｚ Ａｊ ｌ−ｙｚ Ａｓ半導体薄膜層１
５、ノンドーグＧａＡｓ半導体薄膜層１６、ドーグＧａ
Ａ１半導体薄膜層１７が順次形成されている。FIG. 2 is a sectional view showing a main part of a second embodiment of the invention. In this figure 2, semi-insulating GaA
a non-doped GaAs semiconductor thin film layer 12 on the s-substrate lI;
Dawg InxzGal-x2As semiconductor thin film layer 13, non-Dawg Ga Al! A! 1 Semiconductor thin film layer 14% non-doped In yz Aj l-yz As semiconductor thin film layer 1
5, non-dawg GaAs semiconductor thin film layer 16, dodged Ga
A1 semiconductor thin film layers 17 are sequentially formed.
ドーグＧａ Ａｓ半導体薄膜層１７上には金ゲルマニウ
ム／金（ＡｕＧｅ／Ａｕ ）からなるソース電極１８と
ドレイン電極１９、アルミニュウムからなるｆ −上電
極２０がそれぞれ形成されている。A source electrode 18 and a drain electrode 19 made of gold germanium/gold (AuGe/Au) and an f-upper electrode 20 made of aluminum are formed on the Dogu GaAs semiconductor thin film layer 17, respectively.
この第２図の実施例を製造する場合の工程は第１図の実
施例とほぼ同じで６夕詳述を避ける。The process for manufacturing the embodiment shown in FIG. 2 is almost the same as the embodiment shown in FIG. 1, and will not be described in detail.
第１図および第２図の実施例において、ＧａＡｊＡｇ半
導体薄膜層はノンドーグである几め、ＡＩ！の組成比を
ＩｎＧａＡｓとのバンドギヤラグ差が最大になる値、た
とえば０．４５程度まで大きくすることができる利点を
持つ。In the embodiments of FIGS. 1 and 2, the GaAjAg semiconductor thin film layer is non-drug, AI! It has the advantage that the composition ratio of InGaAs can be increased to a value that maximizes the band gear lag difference with InGaAs, for example, about 0.45.
第３図はこの発明の第３の実施例の要部を切断して示す
断面図であり、図中の２１はＩ ｎ Ａｔ Ａ８半導体
薄膜層であシ、このＩｎＡｊＡｓ半導体薄膜層２１に不
純物２２がプレーナドープされている。FIG. 3 is a cross-sectional view showing a main part of a third embodiment of the present invention, and 21 in the figure is an In At A8 semiconductor thin film layer, and this InAjAs semiconductor thin film layer 21 is doped with impurities 22. is planar doped.
このＩ ｎ ｋｌ Ａｓ半導体層２１上には、ノンドー
グＧａ Ａｔ Ａｓ半導体薄膜層２３、ノンドーグＩｎ
ＧａＡｌ半導体薄膜層２４が順次形成されている。On this I n kl As semiconductor layer 21, a non-doped Ga At As semiconductor thin film layer 23 and a non-doped In
GaAl semiconductor thin film layers 24 are successively formed.
第４図はこの発明の第４の実施例の要部を切断して示す
断面図である。この第４図において、 ３１はＩｎＡｓ
とＡＩ！Ａ８とからなる超格子薄膜であり、３２はノン
ドーグＡ／Ａｓ単原子層であシ、３３はドーグＩｎＡａ
単原子層である。・
この超格子薄ｙＸ３１上にノンドーグのＧａＡｌ！Ａｓ
半導体薄膜層３４、ノンドーグのＩ ｎ Ｇａ Ａｓ半
導体薄膜層３５が順次形成されている。FIG. 4 is a sectional view showing a main part of a fourth embodiment of the present invention. In this Figure 4, 31 is InAs
And AI! It is a superlattice thin film consisting of A8, 32 is a non-doped A/As monoatomic layer, and 33 is a doped InAa.
It is a monoatomic layer.・Non-dawg GaAl on this superlattice thin yX31! As
A semiconductor thin film layer 34 and a non-doped In GaAs semiconductor thin film layer 35 are sequentially formed.
以上の第１図ないし第４図のｑ！ｒ笑施実施おいて、ド
ーパントとしてはＭＢＥ法で主にｎｉｌド一ノクントと
して使用されているシリコン（Ｓｔ）でアク。q! in Figures 1 to 4 above! In carrying out this process, silicon (St), which is mainly used as a nil dopant in the MBE method, is used as a dopant.
Ｇａ ＡＩ Ａｓ層には３Ｘ１０１８ｍ−３以上添加す
るのか困難であったのに対し、 ＩｎＡｌ！Ａｓ層に
はＩ Ｘ １０’ｍ−’程度添加するのが容易であシ、
第３図のように不純物２２をＩｎＡｌ！Ａｓ半導体薄膜
層２１にプレーナドーグすることにより、また、第４図
のように超格子薄膜３１の構造にすることにより、さら
に高濃度にすることができる。While it was difficult to add more than 3X1018m-3 to the GaAIAs layer, InAl! It is easy to add about I x 10'm-' to the As layer;
As shown in FIG. 3, the impurity 22 is replaced with InAl! A higher concentration can be achieved by planarizing the As semiconductor thin film layer 21 or by creating a superlattice thin film 31 structure as shown in FIG.
ヘテロ接合型電界効果半帰休装置の要因を決める移動度
、飽和速度などを劣化させることなく。Without deteriorating the mobility, saturation speed, etc. that determine the factors of heterojunction type field effect semi-vacuum devices.
チャンネル層に２ Ｘ １０’ｃＩｎ−”以上の中ヤリ
アを供給することが可能である。It is possible to provide a medium layer of 2 x 10'cIn-'' or more in the channel layer.
この発明に適用する結晶成長法としては、ＭＢＥ法に限
らず、ＭＯ−ＣＮＤ法などによって実現できることはも
ちろんである。The crystal growth method applied to this invention is not limited to the MBE method, but can of course be realized by the MO-CND method or the like.
（発明の効果）
以上詳細に説明し友ように、この発明によれば、信頼性
が高いＧａＡｓ半導体基板上に格子定数不整合によるミ
スフィツト転位が発生しない組成比、膜厚に制御してキ
ャリア供給層となるＩ ｎ Ａｔ Ａｓ半導体薄膜層と
、チャンネル層となるＩ ｎ Ｇａ Ａｓ半導体薄膜層
とを形成し、その間にスペーサ層となるＧａＡ／Ａｓ半
導体薄膜層を形成するようにし友ので、化合物半導体の
うちで最も信頼性の高いＧａ Ａｓ半導体基板を用いる
ことができ、ＧａＡｓ／ＧａＡｌ！Ａａ系に比べ２倍以
上の高い電流駆動力ｔｍ ｔ−持つヘテロ接合ＦＥＴを
提供できる。(Effects of the Invention) As described above in detail, according to the present invention, carriers can be supplied to a highly reliable GaAs semiconductor substrate by controlling the composition ratio and film thickness such that misfit dislocations due to lattice constant mismatch do not occur. A compound semiconductor is formed by forming an In At As semiconductor thin film layer as a layer, an In Ga As semiconductor thin film layer as a channel layer, and a GaA/As semiconductor thin film layer as a spacer layer between them. Among them, the most reliable GaAs semiconductor substrate can be used, and GaAs/GaAl! It is possible to provide a heterojunction FET having a current driving force tm t- that is more than twice as high as that of the Aa type.
第１図はこの発明のヘテロ接合電界効果半導体装置の一
実施例の要部を切断して示す断面図、第２白ないし第４
図はそれぞれこの発明の他の実施例の要部を切断して示
す断面図、第５図はＩｎ ＡＩ Ａｓ膜の特性図、第６
図はＩｎＧａＡｓ膜の特性図である。
１．１１・・・半絶縁性Ｇａ Ａｓ基板、２・・・ノン
ドーグＧａ ＡＩ Ａｇ半導体薄膜層、３・・・ドーグ
Ｉｎｘ１Ｇａｔ−ＸＩＡ８半導体薄膜層、４，２３・・
・ノンドーグＧａＡ／Ａｓ半導体薄膜層、５・・・ノン
ドーグＩｎｙｔＡＪｔ−ｙｔＡｓ半導体薄膜層、６，１
７・・・ドーグＧａＡｇ半専体薄膜層、１２・・・ノン
ドーグＧａ Ａｓ半導体薄膜層、 １３・・・ドーグＩ
ｎｘ２Ｇａｘ−Ｘ２Ａ８半導体薄膜ノー、ｌ ４−・・
ノンドーグＧａ Ａｌ！ Ａｓ半導体薄膜層、１５−・
・ノンドーグＩｎｙｚＡＩ！を−ｙ２Ａｓ半導体薄膜層
、１６・・・ノンドーグＧａＡ／Ａｓ半導体薄膜層、２
１・・・Ｉ ｎ ｈｅ Ａ１１半導体薄膜層、２２・・
・不純物、２４・・・ノンドーグエｎ Ｑａ Ａｇ半導
体薄膜層、３１・・・超格子薄膜、３２・・・ノンドー
グｈｔｈｓ単原子層、３３−・・ドープＩｎＡｓ単原子
層、３４− ＧａＡｌ！Ａｓ半導体薄膜層、３５・・・
Ｉ ｎ Ｇａ Ａ１１半導体薄膜層。
オ（弔シーＨの１１１９１８毬１−１ロｌり第１図
木端」日の第２Ｉ景ビタ１１／１席なでｆｆ１ｌＡり第
２図
本率哨の第３夫）ｔイチ１の雫ｆＦｌ’ｎ度１再■ｎ第
３図
第４図
ＩｎＧａ Ａｓ ｒＩ莢ｃｒ＋＋’ｒ Ｉａ５第６図FIG. 1 is a sectional view showing a main part of an embodiment of a heterojunction field effect semiconductor device of the present invention;
The figures are cross-sectional views showing main parts of other embodiments of the present invention, FIG. 5 is a characteristic diagram of an In AI As film, and FIG.
The figure is a characteristic diagram of an InGaAs film. 1.11...Semi-insulating Ga As substrate, 2...Non-Dawg Ga AI Ag semiconductor thin film layer, 3...Dawg Inx1Gat-XIA8 semiconductor thin film layer, 4,23...
・Non-dawg GaA/As semiconductor thin film layer, 5...Non-dawged InytAJt-ytAs semiconductor thin film layer, 6,1
7...Dogue GaAg semi-dedicated thin film layer, 12...Non-Dogue GaAs semiconductor thin film layer, 13...Dogue I
nx2Gax-X2A8 semiconductor thin film no, l 4-...
Nondawg Ga Al! As semiconductor thin film layer, 15-.
・Nondog InyzAI! -y2As semiconductor thin film layer, 16...Non-doped GaA/As semiconductor thin film layer, 2
1... In he A11 semiconductor thin film layer, 22...
- Impurity, 24--Non-dogue n Qa Ag semiconductor thin film layer, 31--Superlattice thin film, 32--Non-dogue hths monoatomic layer, 33--Doped InAs monoatomic layer, 34- GaAl! As semiconductor thin film layer, 35...
In Ga A11 semiconductor thin film layer. O (Mourning Sea H's 111918 ball 1-1 roll 1st figure kibata) day 2I view bita 11/1 seat pat ff1lA 2nd figure 3rd husband of the main post) tichi 1 drop fFl'n degree 1 re■n Fig. 3 Fig. 4 InGa As rI capsule cr++'r Ia5 Fig. 6
Claims (3)
るヘテロ接合電界効果半導体装置において、（ａ）Ｇａ
Ａｓ半導体基板上に格子定数不整合によるミスフィット
転位が発生しない組成および膜厚に制御して形成され、
チャンネル層となるＩｎＧａＡｓ半導体薄膜層と、 （ｂ）このＩｎＧａＡｓ半導体薄膜層の上部に格子定数
不整合によるミスフィット転位が発生しない組成および
膜厚に制御して形成され、キャリア供給層となるＩｎＡ
ｌＡｓ半導体薄膜層と、 （ｃ）上記ＩｎＧａＡｓ半導体薄膜層と上記ＩｎＡｌＡ
ｓ半導体薄膜層との間に格子定数不整合によるミスフィ
ット転位が発生しない組成および膜厚に形成され、スペ
ーサ層となるＧａＡｌＡｓ半導体薄膜層と、よりなるヘ
テロ接合電界効果半導体装置。(1) In a heterojunction field effect semiconductor device in which a carrier supply layer and a channel layer are formed separately, (a) Ga
Formed on an As semiconductor substrate by controlling the composition and film thickness so that misfit dislocations due to lattice constant mismatch do not occur,
(b) An InGaAs semiconductor thin film layer that becomes a channel layer, and (b) an InA film that becomes a carrier supply layer and is formed on top of this InGaAs semiconductor thin film layer by controlling the composition and film thickness so that misfit dislocations due to lattice constant mismatch do not occur.
(c) the InGaAs semiconductor thin film layer and the InAlA
1. A heterojunction field effect semiconductor device comprising a GaAlAs semiconductor thin film layer, which is formed to have a composition and thickness such that misfit dislocations due to lattice constant mismatch do not occur between the semiconductor thin film layer and the s semiconductor thin film layer, and which serves as a spacer layer.
ープされることを特徴とする特許請求の範囲第１項記載
のヘテロ接合電界効果半導体装置。(2) The heterojunction field effect semiconductor device according to claim 1, wherein the InGaAs semiconductor thin film layer is planarly doped with impurities.
ｎＡｓ層のみにｎ型不純物を添加したことを特徴とする
特許請求の範囲第１項記載のヘテロ接合電界効果半導体
装置。(3) The InGaAs semiconductor thin film layer has a superlattice structure and I
2. The heterojunction field effect semiconductor device according to claim 1, wherein an n-type impurity is added only to the nAs layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11911487A JPS63284869A (en) | 1987-05-18 | 1987-05-18 | Heterojunction field-effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11911487A JPS63284869A (en) | 1987-05-18 | 1987-05-18 | Heterojunction field-effect semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63284869A true JPS63284869A (en) | 1988-11-22 |
Family
ID=14753269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11911487A Pending JPS63284869A (en) | 1987-05-18 | 1987-05-18 | Heterojunction field-effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63284869A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075744A (en) * | 1990-12-03 | 1991-12-24 | Motorola, Inc. | GaAs heterostructure having a GaAsy P1-y stress-compensating layer |
| US5306924A (en) * | 1992-03-12 | 1994-04-26 | Kokusai Denshin Denwa Kabushiki Kaisha | Semiconductor device with strained-layer superlattice |
-
1987
- 1987-05-18 JP JP11911487A patent/JPS63284869A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075744A (en) * | 1990-12-03 | 1991-12-24 | Motorola, Inc. | GaAs heterostructure having a GaAsy P1-y stress-compensating layer |
| US5306924A (en) * | 1992-03-12 | 1994-04-26 | Kokusai Denshin Denwa Kabushiki Kaisha | Semiconductor device with strained-layer superlattice |
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