JP3299188B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a contact layer structure for reducing a contact resistance when forming an ohmic electrode in a III-V compound semiconductor device.

In other words, the present invention is a technique that can be used to effectively reduce the source resistance required for high-speed operation of a high electron mobility transistor and to improve the transistor characteristics. is there.

[0003]

2. Description of the Related Art Generally, III-V compound semiconductor devices are formed on a III-V compound semiconductor substrate.
Recently, for high-speed operation, a semiconductor device has been proposed in which InP is used for a substrate and a high electron mobility transistor structure composed of InAlAs, InGaAs or the like is formed thereon.

FIG. 1 shows a basic structure of a high electron mobility transistor. In this high electron mobility transistor, first, a non-doped InAlAs semiconductor layer 12 and a non-doped I
nGaAs semiconductor layer 13, undoped InAlAs semiconductor layer 14, In doped with n-type impurities in bulk
AlAs semiconductor layer 15, non-doped InAlAs semiconductor layer 16, InAl doped with n-type impurities in bulk
An As semiconductor layer 17 and an InGaAs semiconductor layer 18 bulk-doped with n-type impurities are sequentially deposited, and the n-type InAlAs semiconductor layer 17 and the n-type InGaAs semiconductor layer 18 are non-doped InAlAs.
The semiconductor layer 16 is divided into two regions by a recess groove, and the non-doped InAlAs semiconductor 16 is formed.
A Schottky electrode 20 is formed thereon as a first electrode, and ohmic electrodes 21 and 22 are formed as a second electrode on the n-type InGaAs semiconductor layer 19 so as to sandwich the Schottky electrode 20 therebetween. It is.

In the case of the above-mentioned layer structure, non-doped InAl
As semiconductor layer 12 is a buffer layer, undoped InG
aAs semiconductor layer 13 is an electron transit layer, non-doped InA
The lAs semiconductor layers 14 and 16 are a spacer layer 14 and a barrier layer 16, respectively, the n-type InAlAs semiconductor layer 15 is an electron supply layer, the n-type InAlAs semiconductor layer 17 and the n-type InGa
The As semiconductor layer 18 functions as a contact layer for reducing resistance, and the Schottky electrode 20 functions as a gate electrode, and the ohmic electrodes 21 and 22 function as a source electrode and a drain electrode, respectively.

In order to improve the current gain cut-off frequency (ft) and conduction conductance (g _m ) of a high electron mobility transistor, it is necessary to reduce the source resistance. A
In the case of an lGaAs / GaAs high electron mobility transistor, an ohmic electrode is formed by sintering an alloy layer of AuGe and a semiconductor to the channel layer, but the InAlAs / InGaAs high electron mobility transistor shown in FIG. In this case, a non-alloy ohmic electrode is used to form an ohmic electrode because InGaAs and AuGe react at a low temperature and sometimes cause a short circuit between the electrodes due to surface migration.

In order to form a non-alloy ohmic electrode, band discontinuity (ΔEc) existing at the interface between n-InGaAs and non-doped InAlAs as a barrier layer is required.
Must be effectively reduced, and for this purpose n
An InAlAs semiconductor layer 17 doped with a type impurity is inserted. By inserting this layer, InAlAs
The thickness of the depletion layer extending to the layer is reduced, and the contact resistance is reduced by increasing the tunnel current. However, in order to reduce the resistance, a thick n-InAlAs, n-InGaAs
When the s layer is used, the cap layer conduction 32 shown in the figure becomes dominant, and the contact conduction 31 to the two-dimensional electron gas is reduced. In such a state, the contact resistance depends on the distance between the electrodes. Therefore, in order to reduce the thickness of the depletion layer in the cap layer, the doping concentration of Si is increased as much as possible, and an extra neutral region is formed. It is important to make it thin so that it does not. In fact, by molecular beam epitaxy (MBE), the bulk doping concentration is 1 × 10 ¹⁹ c
When a contact layer designed to have a film thickness of 150 ° and 120 °, respectively, is formed using m ⁻³ InAlAs and InGaAs crystals, the contact resistance is about 0.08Ω ·
mm, which is a very low value, and a contact with the two-dimensional electron gas can be formed non-alloy.

As described above, in order to reduce the contact resistance, it is important to increase the Si doping concentration as much as possible and to design the thickness of the cap layer so that an extra neutral region is not formed. Metal organic chemical vapor deposition (MOVPE) or MBE is generally used for crystal growth of compound semiconductors. In MOVPE, however, Mn is contained in InAlAs crystal.
There is a problem that bulk doping cannot be performed at a higher concentration than the BE method. When InAlAs is doped with Si,
In MBE growth, doping of 1 × 10 ¹⁹ cm ⁻³ is possible, while in MOVPE, 4 to 5 × 10 ¹⁸ cm ^{−3.
At -3} , doping saturates. As a result, 1 × 10
^{At 19} cm ^-3 , the thickness of the depletion layer, which is about 83 °, is 5 × 10 ¹⁸
At cm ^-3 it increases to 118 °. On the other hand, since the tunnel current changes exponentially with the thickness of the depletion layer, the decrease in the doping concentration causes the tunnel current to decrease,
As a result, the contact resistance increases.

For the above reasons, when the high electron mobility transistor structure as shown in FIG. 1 is grown by using the MOVPE method, the contact resistance becomes larger and the source resistance becomes larger than when the transistor is grown by the MBE method. It was the present situation that the number increased.

[0010]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and has as its object to reduce the contact resistance at the time of forming an ohmic electrode which affects the operation performance of a semiconductor device. I do.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
Formed on an InP substrate, III-V Group consists compound semiconductor, for forming a low-resistance electrode, including a semiconductor heterojunction n-InGaAs / n-InAlAs structure
InAlAs / InGaAs high with the contact layer
In the semiconductor device is a electron mobility transistor, the semiconductor layer der the wide gap side of the semiconductor heterojunction
The impurity is added in bulk to the n-InAlAs layer , and the n-type impurity is added to the wide-gap side semiconductor layer in the form of one or more sheets.
And a layer in which the n-type impurity is added in a sheet shape.
The distance between the contact layer and the heterojunction is
When there is no layer where the pure substance is added in a sheet form,
The film thickness below which the n-InAlAs layer of the contact layer is depleted
It is characterized by being within .

[0012]

[0013]

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a contact layer composed of InGaAs / InAlAs doped with n-type impurities in bulk is formed on a high electron mobility transistor, and n-type impurities are added to the n-InAlAs layer. It is an object of the present invention to perform planar doping into the depletion layer generated in the above.

The high contact resistance of the contact layer grown by the MOVPE method as described above is due to InAl
This is because the bulk doping characteristic of As saturates around 5 × 10 ¹⁸ cm ⁻³ , and in order to solve this problem, it is necessary to further dope Si into the InAlAs crystal.

The doping method of the above-mentioned impurities includes:
There are a bulk doping method and a planar doping method.
The planar doping method is a method in which doping is performed in an atomic layer. Generally, a method of supplying a dopant gas in a state where a group V source gas is supplied to interrupt growth and prevent surface roughness is employed. ing. In addition, MOV
When performing Si planar doping on InAlAs by the PE method, it is possible to dope up to around 5 × 10 ¹³ cm ⁻² at the maximum concentration, which is considered to be effective in reducing contact resistance.

In the MOVPE method, doping is generally performed using disilane (Si ₂ H ₆ ) or silane (SiH ₄ ) as a dopant gas. For example, when InGaAs is doped, as in MBE, 10 ¹⁹ cm
⁻³ doping is possible, and only in the case of InAlAs, the doping concentration decreases. As previously mentioned,
To reduce the contact resistance, it is important to increase the Si doping concentration as much as possible and to design the thickness of the cap layer so that an extra neutral region is not formed. MBE
1 × for InAlAs and InGaAs
Considering the case of doping at 10 ¹⁹ cm ^-3 , n-
The thicknesses of the depletion layers formed in the InGaAs layer and the n-InAlAs layer are about 73 ° and 83 °, respectively.
Both nAlAs are considered to be in the range of 100-200 °. However, when the MOVPE method is used as described above, since the maximum doping concentration is 5 × 10 ¹⁸ cm ⁻³ ,
The thickness of the depletion layer of InAlAs is about 118 °.

Next, consider the case where planar doping is performed near the center of the depletion layer. The band profile is linearly approximated to simplify the model, and the Fermi level (Ef) and InAlAs
Is assumed to be the same in the flat state, the energy difference between Ec and Ef at the center of the depletion layer formed in n-InAlAs is ΔΔ of InGaAs and InAlAs.
It is half (about 0.25 eV) of Ec. Further, the planar doping is performed near the center of the depletion layer, and the planar doping concentration required to reduce Ec to Ef at that position is estimated to be about 2.8 × 10 ¹² cm ⁻² . That is, the bulk doping concentration is 5 × 10 ¹⁸ cm ⁻³
However, if a certain concentration or more of planar doping is performed at the center of the depletion layer, the thickness of the depletion layer is less than half (about 60
Å), which means that the contact resistance can be reduced more than the bulk doping of 1 × 10 ¹⁹ cm ⁻³ .

Next, the contact layer structure was actually grown by MOVPE. The substrate temperature is 630 ° C. At this time, bulk doping of 1 × 10 ¹⁹ cm ⁻³ was performed on InGaAs, and the film thickness was set to 120 °. InAlAs was subjected to bulk doping of 5 × 10 ¹⁸ cm ⁻³ to have a film thickness of 150 °. Planar doping is 6 nm from the n-InGaAs / n-InAlAs interface.
This was performed in the n-InAlAs side depletion layer below 0 °, and the planar doping concentration was 2.8 × 10 ¹² cm ⁻² . The contact resistance is TLM (Transmission L
(ine Model) measurement.

As a result, in the present invention in which the planar doping is performed, the contact resistance is reduced to 0.06 Ω · mm, and the MB in which the bulk doping of 1 × 10 ¹⁹ cm ^-3 is performed.
It was found that the contact resistance was further reduced from the result of E. For comparison, a case where planar doping was not used was also evaluated. At that time, the contact resistance was about 0.15 Ω · mm, which was about twice the result of the MBE growth described above.

In contrast to the prior art in which the contact resistance is controlled by the bulk doping concentration, the present invention uses both bulk doping and planar doping and adjusts the planar doping position to effectively reduce the contact resistance. The difference is reduced.

The operation of the present invention relates to a contact layer structure for reducing a contact resistance when forming an ohmic electrode in a III-V compound semiconductor device. In other words, by utilizing the present invention, the source resistance required for operating the high electron mobility transistor at high speed can be effectively reduced even in the MOVPE method, which can be used to improve the transistor characteristics.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which a high electron mobility transistor composed of an InAlAs crystal and an InGaAs crystal is grown on an InP substrate and then n-In.
The layer structure when a contact layer having a GaAs / n-InAlAs structure is grown and planar doping is performed in the n-InAlAs layer for the purpose of reducing the contact resistance is shown. In the figure, 101 is an InP substrate,
102 is an InAlAs buffer layer, 103 is InGa
As channel layer, 104 is a spacer layer of InAlAs,
105 is a carrier supply layer obtained by bulk doping Si into InAlAs, 106 is a barrier layer of InAlAs, 10
Numeral 7 denotes an n-InAlAs contact layer doped with Si bulk, and numeral 108 denotes n-I doped with Si bulk.
This is an nGaAs contact layer. The planar doping 109 was performed in the n-InAlAs contact layer 107, and the position was 60 ° below the n-InGaAs contact layer 108.

Next, the structure shown in FIG.
After growing by using the E method and evaporating AuGe as an ohmic electrode, TLM measurement was performed. The results are shown in FIG.

As for the growth conditions, the growth temperature was 630 ° C., and trimethylindium (TMI) and trimethylaluminum (TMA) were used as group III source gases for the growth of InAlAs. In addition, TMI and triethylgallium (TEG) were used for the growth of InGaAs. Arsine (AsH ₃ ) and phosphine (PH ₃ ) were used as group V source gases, and disilane was used for doping of Si.

Further, the semiconductor layer 107 of n-In
The AlAs layer was subjected to bulk doping of 5 × 10 ¹⁸ cm ⁻³ , and its thickness was set to 150 °. Also, n- of 108
The InGaAs layer was subjected to bulk doping of 1 × 10 ¹⁹ cm ⁻³ to have a thickness of 120 °. The sheet resistance (Rs) estimated from FIG. 3 is 113 Ω / □, and the contact resistance (Rc) is 0.06 Ω · m as shown in FIG.
m.

Further, for comparison, a sample was prepared by the MOVPE method using the sample structure shown in FIG.

Further, the MBE method was applied to the 10 shown in FIG.
1 × 10 ¹⁹ in the n-InAlAs layer which is the semiconductor layer of No. 7
A sample having a bulk doping of cm ^-3 was prepared. The same TLM measurement as described above was performed, and the obtained contact resistance is shown in FIG.

As shown in FIG. 4, the sample without planar doping grown by the MOVPE method had the highest contact resistance (a), which was 0.15 Ω · mm. Also,
In the conventional structure manufactured by using the MBE method, the contact resistance (b) was 0.08 Ω · mm.

From the results shown in FIG. 4, when the planar doping is not performed by using the MOVPE method, the contact resistance is about twice that of the sample manufactured by the MBE method.
It was found that the use of the present invention reduced the contact resistance of the MOVPE method as well as that of the MBE method. Specifically, according to the present invention, even in the MOVPE method in which doping is saturated at about 5 × 10 ¹⁸ cm ⁻³ ,
This shows that a contact layer equivalent to that obtained by doping at 0 ¹⁹ cm ⁻³ can be formed.

Further, at 1 to 5 × 10 ¹⁸ cm ^-3 , n-In
FIG. 5 shows the results obtained by changing the bulk doping concentration of AlAs and examining the planar doping concentration at which the contact resistance becomes about 0.08 Ω · mm. At this time, n-InA
Except for the lAs bulk doping concentration and the planar doping concentration, all were the same as the experiment performed in FIG.

As shown in FIG. 5, in order to keep the contact resistance constant, it is necessary to increase the planar doping concentration as the bulk doping concentration decreases.

Further, by performing the planar doping at a higher concentration, the effect of reducing the thickness of the barrier layer through which the tunnel current flows can be obtained, which can be used for further reducing the contact resistance. Further, the contact resistance can be further reduced by bringing the planar doping position closer to the n-InGaAs side and increasing the planar doping concentration.

Naturally, various design changes can be made in the present invention, and it goes without saying that they belong to the scope of the present invention. For example, the contact resistance can be reduced by using other growth methods such as the MBE method and the MOMBE method. Further, two or more planar doping layers may be inserted, whereby the contact resistance can be further reduced.

[0035]

The present invention relates to a structure of a contact layer structure for reducing a contact resistance when forming an ohmic electrode in a group III-V compound semiconductor device. In the MOVPE method, a higher concentration of S is added to the InAlAs crystal compared to the MBE method.
There was a potential problem that could not dope i. The present invention has solved this problem by devising doping of the contact layer. Since the MOVPE method is a promising crystal growth method in the manufacture and mass production of semiconductor devices, the present invention has a great effect of promoting the practical use and application of various semiconductor devices.

[Brief description of the drawings]

FIG. 1 shows a layer structure when a high electron mobility transistor is formed on an InP substrate.

FIG. 2 shows an embodiment of the present invention, in which a high electron mobility transistor is formed on an InP substrate and n-In
Layer structure when planar doping is performed in an AlAs contact layer for the purpose of reducing contact resistance.

FIG. 3 is a diagram showing a TLM evaluation result of the structure shown in FIG. 2;

FIG. 4 is a view showing the effect of the present invention and comparing the result of the present invention with the result of MOVPE without planar doping and the result of MBE.

FIG. 5 is a diagram showing a relationship between a planar doping concentration required to make contact resistance constant and a bulk doping concentration of an n-InGaAs contact layer.

[Explanation of symbols]

Reference Signs List 11 InP semi-insulating substrate, 12 non-doped InAlAs semiconductor layer, 13 non-doped InGaAs semiconductor layer, 14 non-doped InAlAs semiconductor layer, 15 InAlA doped with n-type impurities in bulk
s semiconductor layer, 16 non-doped InAlAs semiconductor layer, 17 InAlAs bulk doped with n-type impurities
Semiconductor layer, InGaAs bulk doped with 18 n-type impurities
Semiconductor layer, 20 Schottky electrode, 21 ohmic electrode, 22 ohmic electrode, 31 contact conduction to two-dimensional electron gas, 32 cap layer conduction, 101 InP substrate, 102 InAlAs buffer layer, 103 InGaAs channel layer, 104 InAlAs spacer layer 105, a carrier supply layer in which InAlAs is bulk-doped with Si; 106, a barrier layer of InAlAs; 107, n-InAlAs in which Si is bulk-doped
Contact layer, n-InGaAs bulk-doped with 108 Si
Contact layer, 109 planar doping.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-297385 (JP, A) JP-A-4-271129 (JP, A) JP-A-11-214676 (JP, A) JP-A-11- 274475 (JP, A) JP-A-9-64336 (JP, A) JP-A-9-51091 (JP, A) JP-A 8-14873 (JP, A) JP-A 8-55979 (JP, A) JP-A-7-183493 (JP, A) JP-A-7-38089 (JP, A) JP-A-7-38088 (JP, A) JP-A-6-120258 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/338 H01L 29/812

Claims (1)

(57) [Claims] 1. A formed on an InP substrate, made of a compound semiconductor of a group III-V, for forming a low-resistance electrode-free containing a semiconductor heterojunction n-InGaAs / n-I
InAlAs / having an nAlAs structure contact layer
In the semiconductor device is InGaAs high electron mobility transistor, the semiconductor layer having a wider gap side of the semiconductor heterojunction
N to a n-InAlAs layer impurities are bulk to the addition, and the semiconductor layer of the wide-gap side
A layer in which the n-type impurity is added in the form of a sheet, wherein the n-type impurity is added in the form of one or more sheets.
And the distance between the heterojunction of the contact layer and the n-type
If there is no layer to which impurities are added in sheet form,
Thickness at which the n-InAlAs layer of the contact layer is depleted
A semiconductor device characterized by being within .