JPH02252380A - Timing signal generation circuit - Google Patents

Abstract

PURPOSE:To stably generate a timing signal by re-starting a counting means as considering under-mentioned time difference to be a starting time of counting when a time counting operation exceeds time corresponding to the regular arriving interval of a synchronizing signal and reaches the prescribed time. CONSTITUTION:At every first time corresponding to the arriving period of the synchronizing signal SYNC, a ten-bit counter 21 receives a clear pulse CLR to show the arrival of this synchronizing signal, and is operated to be cleared, and time-counts the time from '0' to ''910'. A decoder 25 monitors the count value of the ten-bit counter 21 counting the time after exceeding the first time '910', that is, the arriving period of this synchronizing signal, and detects a second time exceeding the first time '910', for instance, the point of time when the above-mentioned count value becomes '920'. Then, the decoder 25 preset-starts the counter 21 when this second time '920' is detected, and presets a counting start initial value '10' set beforehand according to the above- mentioned second time in the ten-bit counter 21. As the result, the counter 21 re-starts the counting operation of a clock signal CLK at the above-mentioned preset timing as considering the above-mentioned counting start initial value '10' to be a standard.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention effectively compensates for synchronization signals included in video signals used for image reproduction, and compensates for various timing signals necessary for image reproduction. The present invention relates to a timing signal generation circuit that can stably generate a timing signal.

[Prior Art] Recently, various electronic still cameras have been developed that record electronically imaged video signals using solid-state imaging devices such as CCDs on floppy disks (for example, still video floppy disks, 5VF), etc. . This type of electronic still camera is used for boat fishing: - About 50 recording tracks are formed concentrically on the above-mentioned floppy disk, and one electronic still image (still video signal) is recorded on each recording track. It becomes. To record this electronic still image in the SVF, for example, only one field image of one frame image composed of an odd field and an even field is obtained, and its color signal components are recorded as a color difference signal (R-Y). and (B-Y) are extracted alternately every other horizontal scanning line as a color difference line sequential signal. It is of course possible to record the entire frame image, but according to the field recording described above, the S
It becomes possible to record a large number of electronic still images in the limited recording capacity of the VF.

By the way, the reproduction (image reproduction) of video signals recorded on a floppy disk (SVF) is performed under head access control (movement control of the magnetic head in the radial direction of the floppy disk) by specifying the recording track number. This video signal is read out and subjected to predetermined signal processing to produce a TV double signal, such as an NTSC signal or a Y
This is done by converting it into a C signal and a C signal) and feeding it to a TV receiver.

FIG. 15 is a diagram showing a schematic configuration of this type of video signal reproduction system circuit, in which 1 is a floppy disk rotationally driven by a spindle motor 2, 3 is a floppy disk l
This is a magnetic head that writes video signals to and reads them. Access control of the magnetic head 3 to the above-mentioned floppy disk 1 is performed by driving an access mechanism (not shown) under the control of the system controller 4. Further, the spindle motor 2 is driven by a motor drive circuit 5. The system controller 4 controls the operation of the motor drive circuit 5 to rotate the floppy disk 1 at a predetermined rotation speed and with rotational synchronization established.

Under such control, the video signal (reproduced RF signal) read out from the floppy disk l via the magnetic head 3 passes through the preamplifier 6, where the level of the reproduced signal is kept constant, and then the video signal is reproduced. It is taken into the main body of the system circuit. This constant control of the reproduced video signal level is performed because the relative moving speed between the floppy disk l and the magnetic head 3 is different between the inner recording track and the outer recording track of the floppy disk l. This is a process to compensate for changes.

The YC separation circuit 7 uses the difference in signal frequency components to separate the video signal read from the floppy disk 1 into a luminance signal component Y, which is a luminance signal, and a color signal component C, which is a chrominance signal. It is separated into This chrominance signal is used as a color difference signal (R-Y
) and the color difference signal (B-Y) are obtained as a color difference line sequential signal that is alternately output every horizontal scanning period. By the way, line sequentialization of this color difference signal is performed on the floppy disk l mentioned above.
This is done for the purpose of reducing the storage capacity of color difference signal components.

Specifically, for example, for the IH-th, the IH-th signal (R-Yl) of the color difference signal (R-Y) system is extracted, and for the next 2H, the 2H-th signal (R-Yl) of the color difference signal (B-Y) system is extracted. signal (R-Y2), and then the color difference signal (R-Y2) again at the next 3H.
) system, the color difference signal (R-Y3) is extracted every horizontal scanning (IH) period.
) and the color difference signal (B-Y) are alternately extracted to perform line sequentialization.

The luminance signal component Y1 thus separated by the YC separation circuit 7 and the color difference signal (R-Y)/(B-Y) which has been converted into color difference line sequential as described above are each sent to a demodulator 8.9. After being demodulated through the signal processing circuit, the signals are input to two processing circuits 101ll for luminance signals and chrominance signals, respectively. Each of these process circuits 10 and 11 performs dropout compensation for input video signals and skew correction during playback of field-recorded images, and the process circuit 10 for luminance signals performs pseudo frame processing, etc. The color signal processing circuit 11 performs color difference signal separation processing, simultaneous processing, and the like.

Each signal processing operation in these process circuits 10 and 11 is performed using various timing control signals generated by the system controller 4, such as clamp pulse CP, skew pulse SKEw, and line index pulse LI.
These operations are executed in accordance with control signals such as ND.

The luminance signal Y, which is output after being subjected to predetermined signal processing in the luminance signal processing circuit 1O, is input to the adder 12 and is added with the reproduction synchronization signal given from the system controller 4. It is output as a so-called brightness signal Y for TV monitor output. Further, the two color difference signals consisting of (RY) and (B-Y) which are outputted after being subjected to predetermined signal processing in the color signal process circuit 11 are given to the color encoder circuit 13 and output from the color signal processing circuit 11. Ranking control etc. are performed. A signal generated by performing predetermined signal processing in the color encoder circuit 13 is output as the color signal C for output to the TV monitor.

The addition $14 which inputs these color signals C and the luminance signal Y respectively inputs the NTSC signal according to these signals.
It generates and outputs a C signal. This NT is standard
By inputting the SC signal to the TV receiver, image reproduction of the video signal read from the floppy disk I is performed.

Now, the system controller 4 controls the signal processing operations, etc. in each of the process circuits 10 and 11 described above.
is separated from the rotation synchronization signal PG obtained once per rotation from the spindle motor 2 in synchronization with the rotation of the floppy disk l, and from the output of the demodulator 8 for the Y signal via a synchronization signal separation circuit 15. Extracted synchronization signal 5Y
Generates various control signals according to the NC.

That is, the timing signal generation circuit section in the system controller 4 has a capacity of 14.3 M as shown in FIG. 16, for example.
10 bits (2”) to count the Hz clock signal CLK
) A counter 1B, a one-shot pulse circuit 17 that resets and controls the counting operation by the counter 1B according to the synchronization signal 5YNC, and a count value (10 bit data) of the synchronization signal 5YNC by the counter 1B. The control signal generation circuit 18 mainly includes a control signal generation circuit 18 that generates a timing signal corresponding to each timing.

The one-shot pulse circuit 17 inverts and inputs the synchronization signal 5YNC separated and extracted by the synchronization signal separation circuit 15 via the inverter 19, and synchronizes with the falling edge (leading edge of the horizontal synchronization signal) of the synchronization signal 5YNC. That is, it generates and outputs a clear pulse CLR that resets the counter 16 in synchronization with the input time of the synchronization signal 5YNC. The counter IB resets its count value to 0" by the clear pulse CLR synchronized with the synchronization signal 5YNC,
Counting of the clock signal CLK is started based on this reset timing.

Specifically, the 10-bit counter 16 receives the clear pulse CLR generated by the arrival of the periodically inputted synchronization signal 5YNC, and resets its count value each time it receives the clock signal of 14.3 Mtlz. 01
□Execute counting operation for K. Since the synchronization signal, especially the horizontal synchronization signal, arrives at a cycle of 63.5 μSee, the clock signal CLK is counted from [0] to [910], for example, every horizontal scanning period in synchronization with this.

The control signal generating circuit 18 inputs the count value (10-bit data indicating a value up to 2') of the counter IB which is reset-controlled and counts the clock signal CLK as described above, and receives each signal indicated by the count value. According to the timing, various timing signals (control signals) necessary at that time are generated. Specifically, the control signal generation circuit 18 checks the count value from [0] to [9101 by the counter IB using, for example, a decoder, and generates the output signal at each timing according to the timing from the synchronization signal indicated by the count value. Various control signals such as the clamp pulse CP, skew pulse 5KEW, and line index pulse LIND, which are predetermined in advance, are sequentially generated. In this way, at each predetermined time point, the control signal generation circuit 18 executes the signal processing by the process circuits 10, 11, etc., according to various control signals generated corresponding to each time point. do. Therefore, it can be said that the timing signal generation circuit section in the system controller 4 plays a very important role in regulating the processing operations of the image signal reproduction system described above.

[Problems to be Solved by the Invention] However, due to scratches on the floppy disk 1 or defective head touch, the synchronization signal 5, which should originally arrive periodically,
When YNC is missing as shown in Figure 17 (X in the figure),
Clear signal CL for the counter IB at that time
H is no longer generated.

Then, the counter 1B is no longer reset at the original reset timing corresponding to one horizontal scanning period, and the control signal generation circuit 1B, which operates in response to the counted value, is no longer able to generate the various control signals described above at the normal timing. In addition, not only when such a synchronization signal 5YNC is missing, but also when noise caused by the aforementioned scratches on the floppy disk 1 or poor head touch is included in the human input signal as shown in Fig. 17 (Fig. (N), the one-shot pulse circuit 17 generates the clear signal CLR at the time when this noise is input. There is a problem that the counter 1B is reset inadvertently by this clear signal CLH. In this case as well, the control signal generation circuit 18 will no longer be able to generate control signals at regular timing.

The present invention has been made in consideration of these circumstances, and its purpose is to synchronize various control signals necessary for image reproduction processing with the synchronization signal and generate them at accurate timing, for example. An object of the present invention is to provide a possible timing signal generation circuit.

[Means to solve the problem]

The present invention provides a counting means that resets and starts the timekeeping operation when a synchronization signal arrives, and resets and restarts the timekeeping operation when a subsequent synchronization signal arrives, and a progress process of the timekeeping operation by the counting means. a timing signal generating means for generating a predetermined timing signal corresponding to a predetermined time point (for example, various control signals at predetermined timings synchronized with a synchronization signal necessary for image reproduction processing) at a predetermined point in time. Regarding the circuit, when the time measurement operation by the counting means reaches a predetermined second time exceeding the first time corresponding to the regular arrival interval of the synchronization signal, for example, this time point is set as the count value by the counting means. compensation means for restarting the counting means by presetting a time corresponding to the difference between the second time and the first time as a starting time, for example, as an initial count start value for the counting means; It is characterized by having the following.

[Function] According to the circuit of the present invention configured as described above, if the synchronization signal is lost for some reason and as a result, the counting means is not reset at the original cycle of arrival of the synchronization signal, the above-mentioned From the timekeeping information by the counting means, it is detected that the timekeeping operation has reached a predetermined second time that exceeds the first time corresponding to the regular arrival interval of the synchronization signal.

In this case, for example, an initial count start value for the counting means is preset using the time corresponding to the difference between the second time and the first time as the starting time. As a result, the counting means restarts its timekeeping operation based on the initial counting start value, so that the time measured after the preset timing is compensated as being synchronized with the arrival cycle of the synchronization signal. .

Therefore, even if the synchronization signal is missing, the predetermined timing signal (control signal ) can be generated accurately.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a timing signal generation circuit according to an embodiment. This embodiment circuit is incorporated, for example, as part of the functions of the system controller 4 in the video signal reproduction system circuit shown in FIG. 15 mentioned above.

In FIG. 1, 21 is a 10-bit counter that counts the tally signal CLK of 14.3 MIIz, for example.
The control signal generation circuit 22 executes the timekeeping operation by cyclically counting the value up to [2”].The control signal generation circuit 22 performs a timekeeping operation according to the output of the 10-bit counter 21 [timekeeping information indicated by 10-bit data]. At each predetermined time point, a control signal corresponding to that time is generated.The control signal generated from the control signal generation circuit 22 is transmitted to, for example, the process circuit 10 in the video signal reproduction system circuit.
Clamp pulse CP, skew pulse 5KFJ, and line index pulse LI that control the signal processing operations of 11.
ND, also a blanking pulse BLP that controls the signal processing operation of the color encoder 13, and a burst flag B.
Consists of P etc.

The one-shot pulse circuit 23 inverts and inputs the synchronization signal 5YNC separated and extracted by the synchronization signal separation circuit 15 of the video signal reproduction circuit shown in FIG. That is, the clear pulse CLR is generated and outputted in synchronization with the signal input time point when the leading edge of the synchronization signal 5YNC is detected. The clear pulse CLH synchronized with this synchronization signal 5YNC causes the
The 0-bit counter 21 is reset, and the 10-bit counter 21 starts counting operation (timekeeping operation) for the clock signal CLK using this reset timing as a reference.

In this counting operation, the count value at the reset timing is set to [0], and each time the clock signal CLK is input,
This is performed by incrementing the count value by [11, [2], . . . By the stepwise operation of the 10-bit counter 21 (counting operation of the clock signal CLK), the counted value is outputted as information indicating the elapsed time from the reset timing.

This information output is expressed as 10-bit data and indicates the clock time up to [21°].

The control signal generation circuit 22 generates and outputs various timing signals as described above, depending on the elapsed time from the arrival time of the synchronization signal 5YNC, which is indicated by such 10-bit time information.

Here, the feature of this embodiment circuit is that, in addition to the above-mentioned basic configuration, a specific count value by the 10-bit counter 21 is detected, and when this specific count value is detected, the 10-bit counter 21 is Preset control and the corresponding 1
The present invention is characterized in that a decoder 25 is provided for presetting a predetermined counting start initial value in the 0-bit counter 21.

That is, the 10-bit counter 21 is cleared at every first time corresponding to the arrival period of the synchronization signal 5YNC, which normally arrives periodically, in response to a clear pulse CLR indicating the arrival of the synchronization signal, and is cleared [0]. C910]. The decoder 25 monitors the count value of the 10-bit counter 21 which is operating beyond the first time [9101, which is the arrival period of this synchronization signal, and 2, for example, the point in time when the count value becomes [920] is detected.

When the second time [9201] is detected, the decoder 25 presets and starts the 10-bit counter 21, and sets the counting start initial value that has been set in advance according to the second time to the 10-bit counter 21. Preset to . The initial value for starting counting is determined as a value [10] corresponding to the difference between the first time and the second time. As a result, the 10-bit counter 21 restarts the counting operation of the clock signal CLK using the counting start initial value [10] as a reference at the preset timing. Therefore, in this case, as shown in FIG. 2 which schematically shows the operation timing of the embodiment circuit, the 10-bit counter 21 converts its count value to [918],
[919], [920] and [10]
], the counting operation starts again from this preset value [10] and the counted value is [111, [12]
,... and so on.

To explain this processing operation in more detail, as shown in FIG. 2, the synchronizing signal 5YNC is input at a predetermined period corresponding to, for example, one horizontal scanning period in image reproduction, but the timing may change due to some reason. Sync signal 5Y
If NC is missing, clear pulse CLI? Since synchronization signal 5YNC does not arrive, is not emitted, so the second
As shown in the enlarged view of the time axis, the 10-bit counter 21 continues counting the clock signal CLK beyond the first time [910], which is the original reset timing.

As a result, the count values are [9111, [912].

...and continues to increase. Then, when the count value reaches the count value [9201] which is the preset second time, specifically, when it reaches the count value [919] which is one timing before that, the decoder 25 sends the signal to the 10-pitz counter 21. outputs the preset signal Set, and at the next timing [92
0], the counting start initial value [10] is preset in the 10-pit counter 21. With this preset, 1
From the second time [920], the 0 bit counter 21 changes its value to [10] and then outputs the clock signal CL.
The counting of K is restarted and the counted value becomes [111, [12].

...and progressing. .

However, the time information obtained by the counting operation resumed in this way is synchronized because the initial counting start value is determined to correspond to the difference between the first time and the second time. The time information is the same as the time information when the clock signal CLK is reset at the first time [910] by the arrival of the signal 5YNC and the counting of the clock signal CLK is restarted. In other words, the time information after the preset timing indicated by the count value of the 10-bit counter 21 is the same as the time information indicated by the count value of the 10-bit counter 21 when the reset timing is defined by the arrival of the synchronization signal 5YNC. It indicates information. As a result, it becomes possible to effectively compensate for the loss of the synchronization signal 5YNC and to precisely define the time reference for obtaining various signals that are generated and output in synchronization with the synchronization signal.

However, it is impossible with this embodiment circuit to compensate for the counting time from [0] to [9], which is the time information up to the second time [920] mentioned above. Therefore, in such a case, for example, the second time is set as [915],
The error range may be reduced by setting [5] as the initial value for starting counting. Furthermore, if it is not necessary to generate and output a control signal in these time ranges, it becomes possible to operate the circuit while substantially ignoring this error time.

According to the embodiment circuit configured as described above, even if the arrival period of the synchronizing signal 5YNC has elapsed, the synchronizing signal 5YN is still
Even if a so-called synchronization signal is missing without the arrival of C, this is detected from the output of the counter 21 that measures the time information, and the counter 21 is forced to a predetermined initial value for starting counting. By presetting and restarting the counting operation, it is possible to accurately recover the time information. As a result, it is possible to accurately generate and output various control signals synchronized with the synchronization signal of a predetermined period at respective timings, regardless of the omission of the synchronization signal 5YNC, and to stabilize the image signal reproduction processing operation. Become.

In this example circuit, the second time is set as [920] for the first time [9101], but the value can be determined according to the circuit specifications, and of course, the above-mentioned counting The starting initial value may also be determined according to the difference between the first time and the second time. Furthermore, it is of course possible to realize the function of the decoder 25 on the control signal generation circuit 22.

By the way, although the circuit of the embodiment described above is extremely effective in compensating for the loss of a synchronizing signal, it cannot cope with an involuntary reset operation of the 10-bit counter 21 due to the mixing of noise. Therefore, when constructing the above-mentioned timing signal generation circuit, a preprocessing circuit as shown in FIG. 3, for example, is also used.

This preprocessing circuit is provided at the input stage of the synchronizing signal 5YNC separated and extracted by the synchronizing signal separation circuit 15 shown in FIG. 15 described above to the timing signal generating circuit shown in FIG. 1 described above. This preprocessing circuit uses synchronization signal 5Y
At the time of NC input (arrival), a guard pulse CP of a predetermined time width, for example, 58μSee width, is generated from the arrival timing (trailing edge timing) of this synchronization signal 5YNC.
The multivibrator 2B that generates the synchronous signal 5YNC, the input period of the guard pulse CP emitted from the multivibrator 26, and the one-shot pulse circuit 2 of the synchronization signal 5YNC.
3, and a gate circuit (OR circuit) 27 that prohibits human power from being applied to 3. Pulse width 5 of the above guard pulse CP
Since the input period of the synchronization signal 5YNC is usually about 63.5μSee, the input period of the synchronization signal 5YNC is set to 8μSee so as not to interfere with the input of the next synchronization signal 5YNC.
It is determined to remove only the noise N within the arrival time interval of the synchronization signal.

Using such a guard pulse CP, the input period of the synchronization signal 5YNC to the one-shot pulse circuit 23 is limited,
Since the input synchronization signal 5YNC is allowed to be input to the one-shot pulse circuit 23 only for a predetermined time width in anticipation of the arrival timing of the synchronization signal 95YNC that periodically arrives, the input of the noise N as shown in FIG. can be effectively prevented.

It also prevents malfunction of the one-shot pulse circuit 23 due to noise N, prevents the reset operation of the 10-bit counter 21 at an undesired timing, and stabilizes the generation operation of various control signals from the control signal generation circuit 22. It becomes possible to aim for.

However, when the video signal subjected to image reproduction processing by the video signal reproduction system circuit is an electronic still image signal recorded in the field, the following problem occurs. That is, reproduction of field-recorded image signals is performed continuously twice in relation to the image display scan: during odd-numbered field scanning and during even-numbered field scanning. Even field scanning starts with a 1/2 horizontal scanning period difference compared to odd field scanning. Therefore, a shift occurs in the period of the horizontal synchronizing signal at the timing of switching from odd field scanning to even field scanning.

At the time of field switching when the period of the synchronization signal becomes discontinuous in this way, the input control of the input synchronization signal 5YNC by the guard pulse GP described above and the initial value for forced counting start of the 10-bit counter 21 by the decoder 25 described above are performed. When preset control is performed, a shift occurs in the synchronization timing during even field scanning, as the signal timing is shown in FIG.

That is, as the field scan is switched, the synchronization signal arrival period at that timing changes. For example, when the arrival period of the synchronization signal 5YNC becomes (1/2+1)H,
The decoder 25 detects this as a loss of the synchronizing signal 5YNC, and forcibly presets the 10-bit counter 21. For this reason, the synchronization timing after the field scanning switching point deviates by 1/2H from the original synchronization timing during even field scanning. And the subsequent synchronization timing remains the same l/2
This results in a state where a shift of H has occurred. As a result, the control signal is not generated at the correct timing in synchronization with the original synchronization signal.

The embodiment circuit shown in FIG. 6 is configured to deal with such a problem, and the period in which the period of the synchronization signal described above is disturbed occurs at the point when even field scanning starts with the end of odd field scanning. This is done with a focus on the fact that

This circuit controls the control signal generation circuit 2 according to the elapsed time information from the input timing (leading edge timing) of the synchronization signal 5YNC by the 10-bit counter 21.
Guard pulse C with a pulse width of 58μSee mentioned above in 2.
Generate P. And this guard pulse CP
Using this, the gate circuit 28 prevents the clear pulse CLH output from the one-shot pulse circuit 23 from being input to the 10-bit counter 21 during an undesired period.

Specifically, the control signal generating circuit 22 generates and outputs the guard pulse CP over a time width from counting time [15] to [896], as shown in the timing diagram of FIG. 7, for example. Then, this guard pulse CP is applied to the gate circuit 28 to generate a clear pulse CL outputted from the one-shot pulse circuit 23 at an undesired timing.
The passage of H is blocked and controlled. Such guard pulse CP
Clear pulse CL to 10-bit counter 21 using
By blocking the input of R, the reset operation of the 10-bit counter 21 caused by noise arriving at an undesired timing can be prevented in advance and reliably.

Basically, in a timing signal generation circuit that operates by generating such a guard pulse CP, the circuit shown in FIG. Using the rotation synchronization signal (PG multiplication signal) obtained with the start of scanning, the guard pulse CP is applied to the gate circuit 28 using the gate circuits 29 and 30, and the guard pulse CP is forcibly applied to the 10-bit counter 21. The main difference is that the input of each preset signal is prohibited.

That is, by utilizing the fact that the period in which the arrival period of the synchronization signal is discontinuous is the PG double signal input period, which is the switching point of the field scan, the above-mentioned field scan switching indicated by the PG double signal input period is performed. Over a predetermined period, the removal control operation for the clear pulse CLR (erroneous clear pulse generated due to noise) by the guard pulse CP described above is stopped, and the above-mentioned 1.
A feature of the present invention is that the forced preset control operation for the 0-bit counter 21 is also stopped.

According to the timing signal generation circuit configured as shown in FIG. 6, which prevents the output of the guard pulse GP and the output of the forced preset signal during the period in which field scanning is switched using the PC signal. For example, as shown in Fig. 8, which shows the timing relationship of the main signals at the time of field scanning switching, even if the period of the synchronizing signal 5YNC changes with the field scanning switching, 1
Since forcible preset operations and the like for the 0-bit counter 21 are prohibited, it becomes possible to correctly detect the synchronization timing.

Specifically, as the field scan is switched, the arrival period of the synchronization signal at the time of the switch is (1/2 +
1) Even if it becomes long as H, the above-mentioned 1 in between
Since synchronization timing compensation is not performed by forcibly presetting the 0-bit counter 21, it is possible to reliably reproduce and detect synchronization timing after a periodic change. Then, after the PC signal disappears, the
It becomes possible to perform a synchronization timing compensation operation by forcibly presetting the 0-bit counter 21.

Furthermore, even if the synchronization signal arrival cycle at the time of switching is 1/2H as shown by the broken line in Fig. 8 due to field scanning switching, and then the synchronization signal arrives at the IH cycle. , 172H and the synchronization signal inputted at a short cycle are the guard pulses G mentioned above.
Since the clear pulse CLR indicated by the synchronization signal 5YNC that arrives in this short cycle is not removed inadvertently by P, the clear pulse CLR is input to the 10-bit counter 21 as it is. Therefore, in this case, the 10-bit counter 21 will be reset without counting the time corresponding to IH, but will start counting the time corresponding to IH from the time of input of the subsequent synchronization signal 5YNC. The synchronization timing will be correctly detected for reproduction.

Therefore, by such a simple measure, that is, only by prohibition control using the PG multiplied signal of the timing control operation, it becomes possible to effectively perform synchronization timing regeneration corresponding to the change in the period of the synchronization signal 5YNC.

By the way, in the above explanation, compensation for the loss of the synchronization signal 5YNC that arrives at a predetermined period and compensation for malfunction of synchronization timing regeneration due to noise at an undesired timing have been described.

It is not always the case that the noise is input only at timings other than the synchronization signal period. For example, as shown in FIG. 9, it is naturally possible that noise may be mixed into the synchronization signal period.

Incidentally, when noise is removed by generating a guard pulse CP in a preprocessing circuit as shown in FIG. 3, as shown in FIG. Nl.

Assuming that N2 is mixed in, for example, a guard pulse GP is generated for a predetermined period (for example, 58 μSee) from the timing of noise Nl mixed in.

The synchronization signal 5Y is generated by the output of this guard pulse CP.
Passage blocking control is performed after the timing of the noise N1 of the NC being mixed in, so for example, the output synchronization signal 5
The ync pulse width becomes unintentionally narrow.

Moreover, since the guard pulse CP is generated based on the mixing timing of the noise Nl, the guard period is shifted forward in time. As a result,
Guarding against noise at the trailing edge of one horizontal scanning period becomes weaker, and if noise N3 mixes into the trailing edge of one horizontal scanning period, for example, as shown in FIG. 9, there is a risk that it will be erroneously detected as a synchronization signal. This occurs.

In this respect, as in the embodiment circuit shown in FIG. If the guard pulse GP generated according to the time information measured by the 10-bit counter 21 is used after resetting the 10-bit counter 21, the problem as seen in the preprocessing circuit shown in FIG. 3 will not occur. . This is because the 10-bit counter 21 uses the leading edge of the synchronizing signal 5YNC as a synchronization timing, and starts its time counting operation based on this timing. The control signal generating circuit 22 generates the guard pulse CP according to the time information from the 10-bit counter 21. Therefore, since the guard pulse CP itself is always emitted in a predetermined time width region based on the arrival timing of the synchronization signal 5YNC, the generation timing of the guard pulse CP will not change due to noise N mixed within the synchronization signal period ( , there is no fear of malfunction due to the noise N.

Therefore, according to the embodiment circuit shown in FIG. 6 described above, even if noise is introduced during the synchronization signal period, various control signals synchronized in timing with the synchronization signal can be accurately processed without being affected by the noise. It has the advantage that it can be generated. On top of that, during a steady period excluding the field scanning switching time, that is, during a period when no PC signal is input, the forcible preset control of the 10-bit counter 21 and noise N removal processing using the guard pulse GP are performed. It becomes possible to reliably and accurately reproduce the synchronization timing and generate various control signals at the correct timing.

By the way, one of the important processing functions in this type of timing signal generation circuit is to process the input synchronization signal 5YNC.
It has the ability to play correctly. Namely, synchronization signal 5YNC
Various control signals are generated at predetermined timing for each horizontal scanning line in synchronization with the horizontal synchronization signal in the video signal, and the image reproduction processing for the video signal is performed with high precision. Processing is required to correctly reproduce and restore the data and combine it with the output video signal.

The synchronization signal of the video signal used for image display takes the form of a composite of various synchronization signals as shown in the standard, and for example, as shown in FIG. During the horizontal synchronization signal H5sync, 1/2
It is constructed by inserting an equalization pulse EQ with an H period, a vertical synchronizing signal V5sync whose signal level is inverted with a 1/2H period, and the like. The generation of the control signals at various timings described above is achieved by detecting the horizontal synchronization component of such a signal sequence and generating a clear pulse CLR at the leading edge of the horizontal synchronization component.
This is done under timing control in which the time counting operation by the bit counter 21 is reset.

However, in order to correctly reproduce the synchronizing signal 5YNC consisting of a signal sequence of various pulse widths by removing the noise mixed therein, it is impossible to use the guard pulse CP described above.For example, as shown in FIG. It is necessary to generate guard pulses CP of various pulse widths as shown in FIG. - For boat fishing, 58.8 μsec or 27.1 μsec depending on the type of synchronization signal.
, 29.5μsec, 4.7μsec.

It is necessary to generate and output a guard pulse GP having a pulse width of 61.2 μsec in accordance with the synchronization signal timing of each of the various synchronization signals described above.

However, it is extremely difficult to generate guard pulses GP with various pulse widths under such fine timing control, and the configuration of the control circuit for generating the guard pulses CP must also be considerably complicated. can not deny.

Therefore, in the present invention, we focused on the pulse width of various synchronization signals, and reproduced the synchronization signal 5YNC as shown in FIG.
(Restoration and playback) processing is performed.

That is, the L period inspection circuit 32 manually inputs the synchronization signal 5YNC separated and extracted by the synchronization separation circuit 15 shown in FIG. The pulse width of the synchronization signal is checked according to the information. This pulse width test is performed not only on the horizontal synchronization signal H5ync mentioned above, but also on
This is also done for the vertical synchronization signal V5sync and equalization pulse EQ, respectively.

When the type of synchronization signal is identified through this pulse width detection process and the trailing edge is detected, the one-shot pulse circuit 33 is activated to generate and output a synchronization set pulse HSET indicating the timing of the trailing edge. ing. The RS flip-flop, which is constructed by cross-connecting two NAND circuits 34 and 35, is generated when the one-shot pulse circuit 23 provided at the input stage of the synchronization signal detects the leading edge of the synchronization signal. Clear pulse C
A reset operation is performed by inputting LR as a synchronous clear pulse HCLR. Then, the synchronous set pulse HSET generated and outputted by the one-shot pulse circuit 33 in the above-mentioned period check circuit 32 is inputted to perform a set operation. In this manner, the RS flip-flop that performs set and reset operations generates and outputs an output synchronizing signal S3'ne that accurately reproduces the leading and trailing edges of the input synchronizing signal 5YNC.

In other words, the above-mentioned period check circuit 32 judges the signal level of each predetermined synchronization signal at a predetermined timing according to the time information measured by the above-mentioned 10-bit counter 21, and based on the judgment result, the synchronization signal The trailing edge timing of the synchronization signal is determined by identifying the type of the synchronization signal.

That is, in the NTSC standard, the pulse width of the synchronization signal is determined based on each specification, and when the clock signal CLK with the above-mentioned period is used as a reference, the horizontal synchronization signal; H8ync ・= 58 to 73
elk equalization pulse; EQ...29~37 el
k vertical synchronization signal; VSync-375~401 el
It is defined as k.

Therefore, the above-mentioned period checking circuit 32 checks whether the signal level is "Lo" at the position immediately before each of these timings, and also checks whether a trailing edge of the synchronization signal exists in each of the above-mentioned timing periods. is inspected to find the correct trailing edge timing for each type of synchronization signal.

Specifically, as shown in FIG.
8 to 73] clock, so the immediately preceding [44
], [4g], and [52] It is checked whether the synchronization signal level is "L2" at the timing of the clock.

Similarly, since the pulse width period of equalization pulse EQ is [29 to 37] clocks, the synchronization signal level is "Lo" at the timing of [IB], [20], and [24 clocks immediately before that. We are checking whether or not.

And the pulse width period of the vertical synchronization signal V5ync is [3
75-401] Since it is a clock, the [
224], [288], and [352] It is checked whether the synchronization signal level is "Lo" at the clock timing.

As a result of these tests, when the signal level at each timing mentioned above is "L" level, next we check whether the signal level became "H" within each period mentioned above, that is, if the trailing edge of the synchronization signal Check whether it is detected. In addition, considering the margin for jitter of the synchronization signal, horizontal synchronization signal; H8sync-51~7Q elk equalization pulse; EQ...23~43 elk vertical synchronization signal; VSync -387~407 synchronization signal in the elk range The test is to see if the trailing edge of is detected.

To explain synchronization signal reproduction by such pulse width detection using the horizontal synchronization signal H5ync as an example, for example, L
The period check circuit 32 and the one-shot pulse circuit 33 are constructed as shown in FIG.

The three D flip-flops 40, 41, and 42 receive the input synchronization signal 5YNC as data input, and according to predetermined timing information from the input timing (leading edge timing) of the synchronization signal 5YNC measured by the 10-bit counter 21 described above. Latch input data. Here D
As described above, the flip-flops 40, 41, and 42 each latch the input data at the timing of the [44], [4g], and [52] clocks, and store and save the data level at that time.

The NOR circuits 43, 44, 45 perform NOR processing on the latch outputs of the D flip-flops 4G, 41, 42, two by two, and their outputs are connected to the OR circuit 46 (which exhibits an AND function with negative logic). taken out through.

The circuit constituted by these NOR circuits 43, 44, 45 and OR circuit 46 realizes a so-called majority logic function, and the circuit constituted by the above-mentioned three D flip-flops 40.4.
1.42, the synchronization signal level at these timings is "L", and the input signal is the horizontal synchronization signal H.
A confirmation signal HOK indicating that the conditions for 5sync are satisfied is output.

That is, the NOR circuit 43 performs NOR processing on the latched data of the D flip-flops 40 and 42, and outputs an "H" level signal only when "L rubel" data is latched in both of them. , D flip-flop 40.
When "L" level data is latched in one of the terminals 42, the NOR circuit 43 outputs an "H" level signal. Similarly, the NOR circuit 44 outputs "H" data only when L" level data is latched in both D flip-flops 40 and 41, and the NOR circuit 45 outputs "H" data in both D flip-flops 42 and 43. “L” in
'H' data is output only when level data is latched.

At least two of the three D flip-flops 40, 41, 42 are connected by such NOR circuits 43, 44, 45.
When data at "L° level" is latched, a signal at "H# level" is output from any of the NOR circuits 43, 44, 45, and this signal is passed through the OR circuit 4G to the confirmation signal HOK. is output as

In addition, such majority logic processing is performed at the three clock timings [44] and [48L[52] mentioned above.
Confirming this as a horizontal synchronization signal only when all of the data latched in the flip-flops 40, 41, and 42 is at the "L" level is done in view of the extremely strict conditions for confirmation. There is. In other words, at least two of the three timings mentioned above
``When a level is detected, it is based on the fact that there is almost no problem in confirming it as a horizontal synchronization signal from experience.Also, by adopting this kind of majority logic processing, Even if noise N is accidentally detected at the latch timing, the synchronization signal can be confirmed without being affected by the noise N included in the synchronization signal period.

On the other hand, the RS flip-flop, which is constructed by cross-connecting NAND circuits 47 and 48, is set at a timing [51] that is set in consideration of the jitter margin for checking the trailing edge of the synchronization signal mentioned above. , and is reset at timing [79], and outputs an "H" level signal over these timing periods [51] to [79]. The D flip-flop 49 which receives the above-described input synchronization signal as a clock input latches the output data of the RS flip-flop at the rising timing of the input signal. The confirmation signal HOK obtained as described above is generated by this D flip-flop 4.
It is used as an enable signal to control the latch operation of 9.

Therefore, the D flip-flop 49 receives the confirmation signal HOK.
It operates only when the synchronizing signal is input, that is, when it is confirmed that the level of the synchronizing signal is "L" at a timing slightly preceding the trailing edge timing of the synchronizing signal. Then, the timing period [51] to [
79], when the trailing edge indicated by the rising edge of the input synchronization signal is input, the D flip-flop 4
9 is performed and a signal of H" level is output.

By controlling the operation of the flip-flop 49 in this way,
The input synchronization signal rises during the timing period [51] to [79], which is a timing period in which the trailing edge of the synchronization signal H5ync can exist, and is set in consideration of the margin for jitter, and is immediately before the trailing edge. Only when it is confirmed that the level of the synchronization signal is “L” at timings [44], [48], and [52], “
A high level signal is output.

Thus, the one-shot pulse circuit 33 includes a D flip-flop 50 that delays the output of the D flip-flop 49 by one timing according to the clock signal CLK, an inverted output of the D flip-flop 5o, and an output of the D flip-flop 49. NAND circuit 5 that logically processes
1.

According to such a configuration, as shown in FIG. 14, when the trailing edge edge of the input synchronizing signal is correctly detected, the output of the D flip-flop 49 and its output are delayed by one timing. The inverted output of the D flip-flop 50 is subjected to NAND processing, and as a result, the one-shot pulse circuit 33 outputs a set pulse HSET indicating the trailing edge timing of the synchronizing signal.

Therefore, as described above, the two NAND circuits 84 and 35 are cross-connected, and the one-shot pulse circuit 23 detects the leading edge of the synchronization signal and converts the clear pulse CLR generated into the synchronization clear pulse HCLI? By using the set pulse HSET to set the flip-flop that has been manually reset, the input synchronization signal 5YNC is output from this RS flip-flop.
Output synchronization signal 5y that correctly reproduces the leading and trailing edges of
It becomes possible to generate and output nc.

Note that although the inspection operation of the horizontal synchronization signal H5sync and an example of its circuit configuration have been described here, the inspection can be similarly performed for the equalization pulse EQ and the vertical synchronization signal V5sync.

Specifically, the above-mentioned D flip-flop 40, 41°4
2, NOR circuits 43, 44, 45, and OR circuit 4B, as well as pulse width inspection circuits composed of NAND circuits 47, 48, and D flip-flops 49, are also configured for equalization pulse EQ and vertical synchronization signal V5sync, respectively. I'll keep it.

When checking the equalization pulse EQ, the above-mentioned 3.
The timings for driving the two flip-flops 40, 41, and 42 are clocks [1B], [20], and [24], and the timings for setting the RS flip-flops are clocks [23] and [43]. In addition, when testing the vertical synchronization signal V5ync, the timings for driving the three flip-flops 40, 41, and 42 mentioned above are set to [224], [288], and [352] clocks, and the RS flip-flop is set and operated. The timing is set to [367], [4o7] clock.

By doing so, the pulse widths of the equalization pulse EQ and the vertical synchronization signal V5ync can be tested in the same way as the horizontal synchronization signal H5yne.

These test results are obtained as the output of the flip-flop 49 only in one of the pulse width test circuits set corresponding to each synchronizing signal, depending on the pulse width of the synchronizing signal. , these signals may be applied to the one-shot pulse circuit 33 through the OR circuit 52.

According to the circuit shown in FIG. 11 configured in this manner, various control signals are generated at accurate timings in synchronization with the input timing (leading edge timing) of the horizontal synchronization signal, and the human synchronization signal series It is possible to accurately reproduce and restore synchronization signals of various pulse widths contained therein.

As a result, it is possible to effectively perform various signal processing on video signals used for image reproduction, and to output video signals with accurate synchronization timing using the reproduction synchronization signal S)'ne that has been accurately restored and reproduced. It becomes possible.

It should be noted that the present invention is not limited to each of the embodiments described above. For example, it is of course possible to individually implement the plurality of control processes described in the embodiments.

For example, the embodiment circuit shown in FIG. 6 focuses on the fact that compensating for the synchronization shift using the guard pulse CP at the time when the period of the synchronization signal changes has an adverse effect. The main purpose is to prohibit control using the guard pulse CP, and if only this method is adopted, the 10-bit counter 21
It is also possible to omit forced preset control for.

Furthermore, the main purpose of the embodiment circuit shown in FIG. 11 is to accurately reproduce and restore the synchronizing signal, and therefore, it is necessary to extract only the function of the circuit for reproducing and restoring the synchronizing signal and incorporate it into the successive synchronizing signal reproducing system. Of course, it is also possible. In this case, it goes without saying that the timing may be controlled according to the specifications of the synchronization signal to be reproduced and restored. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, the counter resets and starts the timekeeping operation when a synchronization signal arrives, and resets and restarts the timekeeping operation when a subsequent synchronization signal arrives. using means to generate a predetermined timing signal corresponding to a predetermined point in time in the progress of the timekeeping operation by the counting means, and the timekeeping operation by the counting means corresponds to a regular arrival interval of the synchronization signal. Compensation means for restarting the counting means when a predetermined second time exceeding the first time has been reached, the time corresponding to the difference between the second time and the first time is set as the starting time. Therefore, even if the synchronization signal is lost, the synchronization timing can be very easily and effectively ensured. For example, the synchronization signal included in the video signal used for image reproduction In practical terms, it is possible to effectively compensate for and stably generate various timing signals necessary for the image reproduction, and other great practical effects can be achieved.

[Brief explanation of drawings]

The figures show a timing signal generation circuit according to the present invention. FIG. 1 is a schematic diagram of the main part of the circuit of the first embodiment, and FIG. 2 explains the operational functions of the circuit of the embodiment shown in FIG. 1. Figure 3 is a diagram showing an example of the configuration of a compensation circuit for noise, Figure 4 is a timing diagram showing the noise removal effect of guard pulse CP, and Figure 5 is a diagram showing the guard pulse at the time of periodic change of the synchronization signal. A diagram showing an example of malfunction due to pulse CP, FIG. 6 is a diagram showing a schematic configuration of an embodiment circuit equipped with a compensation function for guard pulse GP, and FIG. 7 is a diagram showing generation of guard pulse CP in the embodiment circuit shown in FIG. 6. FIG. 8 is a timing diagram showing an example of the operation of the embodiment circuit shown in FIG. 6, and FIG. 9 is a timing diagram for explaining the operation. FIG. 9 is a timing diagram showing an example of the operation of the embodiment circuit shown in FIG. 6. FIG. This is a timing diagram for Also, FIG. 10 is a signal diagram for explaining the form of the synchronization signal and problems with its reproduction and restoration, FIG. FIG. 11 is a diagram for explaining the principle of reproducing and restoring a synchronizing signal in the embodiment circuit shown in FIG.
FIG. 4 is a timing diagram showing an example of the operation of the circuit shown in FIG. 13. FIG. 15 is a diagram showing a general configuration example of a video signal reproduction system, FIG. 16 is a diagram showing a basic configuration example of a conventional timing signal generation circuit, and FIG. 17 is a diagram showing a basic configuration example of a conventional timing signal generation circuit. FIG. 17 is a signal diagram for explaining defects in the timing circuit shown in FIG. 16 due to omissions and noise. 4... System controller, 10.11... Process circuit, 13... Color encoder, 15... Synchronous signal separation circuit, 1B... 10 bit counter, 17
... one-shot pulse circuit, 18 ... control signal generation circuit, 21 ... 10-bit counter, 22
... Control signal generation circuit, 23... One-shot pulse circuit, 25... Decoder circuit, 26...
Multivibrator, 27.28...Gate circuit (OR circuit), 29.30...Gate circuit (AND circuit)
, 32... L period inspection circuit, 33... One-shot pulse circuit, 84.35... NAND circuit (configuring RS flip-flop), 40.41.42... D flip-flop, 43.44 .45...Nor circuit, 4B
... OR circuit, 47.48 ... NAND circuit (configuring RS flip-flop), 49 ... D flip-flop, 50 ... D flip-flop (1 timing delay), 51 ... NAND circuit, 52...OR circuit.

Claims (1)

[Claims] When the synchronization signal arrives, the timekeeping operation is reset and started,
Counting means for resetting and restarting the timekeeping operation at the time of arrival of a subsequent synchronization signal, and signal generation for generating a predetermined timing signal corresponding to a predetermined time point at a predetermined time point in the progress of the timekeeping operation by the counting means. and when the timekeeping operation by the counting means reaches a predetermined second time that exceeds the first time corresponding to the regular arrival interval of the synchronization signal, this second time and the first time and compensation means for restarting the counting means using a time corresponding to the difference between the two as a starting time.