JPH03107288A - Picture signal reproducing device - Google Patents

Abstract

PURPOSE:To maintain the continuity of a horizontal synchronizing signal, and to prevent deterioration of the signal by giving skew compensation processing to a reproduced picture signal added with a composite synchronizing signal based on a skew compensation gate signal. CONSTITUTION:The composite synchronizing signal Csync phase-synchronized to the composite synchronizing signal separated from the reproduced picture signal is formed, and simultaneously, is supplied to a timing signal generation circuit 115, and the skew compensation gate signal is formed. The formed composite synchronizing signal is supplied to a synchronous signal addition circuit 11, and after adding it to the regenerative picture signal, the reproduced picture signal is given the skew compensation processing based on the skew compensation gate signal. Even after skew compensation, the continuity of the horizontal synchronizing signal is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal reproducing apparatus for reproducing an image signal from a recording medium in which the image signal is recorded for each field.

[Conventional technology]

As a scanning method for current television signals, a 2:1 interlaced scanning method is generally used in which scanning is performed by skipping every other scanning line. Interlaced scanning is performed with scanning lines interlaced with each other every l/60 seconds, and two frames of field images formed by one interlaced scan are used to construct one frame image every l/30 seconds. ing.

In the case of an NTSC television signal, as described above, one frame screen is made up of two field screens, and the one frame screen is made up of 525 scanning lines.

Furthermore, the above-mentioned television signal has a horizontal synchronizing signal added to it every horizontal scanning period and a vertical synchronizing signal every vertical scanning period, and the continuity of the synchronizing signal is maintained at the boundary between each field period. It's dripping.

A still video recording and reproducing apparatus has conventionally been used as an apparatus for recording and reproducing the above-mentioned television signals on a recording medium such as a magnetic disk.

The still video recording and reproducing apparatus rotates a magnetic disk as a recording medium at 3600 rpm, and transmits image signals for one field per track to a plurality of concentric tracks formed on the magnetic disk. A still image signal is obtained by recording and repeatedly reproducing the recorded image signals for one field.

In addition, when reproducing still image signals as mentioned above, in order to correspond to the scanning method of television signals as mentioned above,
Using a 1/2 horizontal synchronization period (1/2H) delay element, the image signal for 1 field is converted to 1/2H excluding the vertical synchronization period.
By alternately switching and outputting the image signal delayed by the delay element and the image signal not delayed every single field period, the continuity of the horizontal synchronization signal is maintained and the above-mentioned interlaced scanning is supported. So-called skew compensation processing is performed to

FIG. 6 is a diagram showing a schematic configuration of a conventional still video reproducing apparatus, and the operation of the conventional still video reproducing apparatus will be described below.

In FIG. 6, a magnetic disk 100 is rotated at 3600 (rpm) by a motor 101, and a magnetic head 100 is rotated by a motor 101.
2 reproduces the signals recorded on the tracks formed on the magnetic disk 100 and supplies them to the reproduction amplifier 103.

The signal reproduced by the magnetic head 102 is amplified to a practical amplitude level by a regenerative amplifier 103, and then supplied to a demodulation circuit 104, where it is demodulated and a composite synchronization signal is added. The image signal corresponding to the input signal is output and supplied to the synchronizing signal separation circuit 105 and the image signal processing circuit 107.

A synchronization signal separation circuit 105 separates a composite synchronization signal from the signal supplied from the demodulation circuit 104, and the separated composite synchronization signal is supplied to a timing signal generation circuit 106 and a synchronization signal addition circuit 108.

By the way, on the circumference of the core of the magnetic disk 100, there is a magnetic piece (P
G bin) 107 is provided, and a magnetic disk 100
As the PG pin 107 rotates, the PG coil 10
8, a pulse signal is output from the PG coil 108, and after the pulse signal output from the PG coil 108 is waveform-shaped in a waveform shaping circuit 109, it is synchronized with the rotational phase of the magnetic disk 100. The signal is supplied to the timing signal generation circuit 106 as a PG pulse signal.

Incidentally, the vertical synchronizing signal added to the image signal recorded on each track on the magnetic disk 100 is 7H±2 in the circumferential direction from the position where the PG bin 107 is provided.
It is recorded so that the position is shifted by H.

The timing signal generation circuit 106 receives the composite synchronization signal supplied from the synchronization signal separation circuit 105 and the waveform shaping circuit 1.
09, a blanking signal B1 and a skew compensation gate signal S are formed, and the formed blanking signal B is sent to the image signal processing circuit 110.
In addition, the skew compensation gate signal S is supplied to a changeover switch 113, which will be described later. The image signal processing circuit 110 performs horizontal and vertical blanking processing on the image signal supplied from the demodulation circuit 104 based on the blanking signal B supplied from the timing signal generation circuit 106 and sends it to the synchronization signal addition circuit 111. supply

The synchronization signal addition circuit 11'1 adds the composite synchronization signal separated by the synchronization signal separation circuit 105 to the image signal for l fields which has been subjected to blanking processing in the image signal processing circuit 110 in the previous stage, and converts it into 1/2H. Delay circuit 1
12, supply to the a terminal of the changeover switch 113, and the 1/2
The H delay circuit 112 delays the supplied image signal by 1/2H period and supplies it to the b terminal of the changeover switch 113.

The changeover switch 113 is connected to the skew compensation gate signal S output from the timing signal generation circuit 106.
Accordingly, by alternately switching the connection between the a terminal side and the b terminal side in the figure every one field period, a frame image signal corresponding to the interlaced scanning method is output from the changeover switch 113 via the output terminal 114. Output.

[Problem that the invention is trying to solve] However,
In the case of the conventional apparatus as described above, the positional relationship between the recording start point of the image signal recorded on the magnetic disk and the PG bin varies from magnetic disk to magnetic disk, and it is difficult to detect the PG bin. When performing skew compensation processing that alternately switches and outputs an image signal delayed by 1/2H and an image signal that is not delayed in synchronization with the PG pulse signal generated by Continuity of synchronization signal is not maintained.

In addition, since the composite sync signal added to the reproduced image signal is reproduced from a magnetic disk, part of the composite sync signal may be missing due to dropouts caused by dust or scratches, or There is a risk of deterioration due to noise intrusion from the magnetic disk, uneven rotation of the magnetic disk, etc.

By the way, in conventional devices, when displaying an image signal reproduced from a magnetic disk by the still video reproduction device as a still image using, for example, a monitor device, the composite image signal added to the reproduced image signal as described above is used. Even if the synchronization signal is degraded, the monitor device is equipped with AFC (Auto
o Frequency Control) circuit, it was possible to display stable still images. When a reproduced image signal is inputted, a normal image signal may not be inputted because the composite synchronization signal has deteriorated.

The present invention eliminates the above-mentioned conventional drawbacks, maintains the continuity of the horizontal synchronization signal even after skew compensation processing, and outputs a composite synchronization signal without deterioration together with the reproduced image signal. The purpose of the present invention is to provide an image signal reproducing device that can perform the following functions.

[Means to solve the problem]

The image signal reproducing apparatus of the present invention is an apparatus for reproducing an image signal recorded on a recording medium, and includes a reproducing means for reproducing the signal recorded on the recording medium, and an image signal reproduced by the reproducing means. a composite synchronization signal separating means for separating a first composite synchronization signal added to the image signal; and a second composite synchronization signal phase-synchronized with the first composite synchronization signal separated by the composite synchronization signal separation means. a composite synchronization signal forming means for forming a signal; adding a second composite synchronization signal in place of the first composite synchronization signal added to the image signal reproduced from the recording medium by the reproduction means;
A device comprising a composite synchronization signal adding means for outputting, and a skew compensation processing means for performing skew compensation processing on the image signal to which the second composite synchronization signal outputted from the composite synchronization signal addition means is added. It is.

[Effect]

With the above configuration, it is possible to maintain the continuity of the horizontal synchronization signal even when skew compensation processing is performed, and it becomes possible to output a composite synchronization signal without deterioration together with the reproduced image signal.

〔Example〕

Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a still video reproducing apparatus that handles still image signals based on NTSC television signals, as an embodiment of the present invention. In FIG. 1, the same components as in FIG. 6 are given the same reference numerals, and detailed explanations will be omitted.

In the embodiment shown in FIG. 1, the magnetic disk 1 is rotated by a motor 101 in the same way as in the conventional example shown in FIG.
00, the signal reproduced by the magnetic head 102 is amplified by the reproducing amplifier 103, the amplified reproduced signal is demodulated by the demodulation circuit 104, and the synchronizing signal separation circuit 105
, are supplied to the image signal processing circuit 110.

The synchronization signal separation circuit 105 separates a composite synchronization signal (Csync) from the signal supplied from the demodulation circuit 104, and the separated C5sync is sent to the timing signal generation circuit 11.
5.

As described above, in this embodiment, as in the conventional example shown in FIG. C formed in the timing signal generation circuit 115 instead of being added.
It is configured to add 5sync.

FIG. 2 is a diagram showing an example of the configuration of the timing signal generation circuit 115 shown in FIG. 1.

In FIG. 2, 1 is an input terminal for a composite synchronization signal (Csync) reproduced from the magnetic disk 100 in FIG.
Input terminal! C5ync input from (see Figure 3)
is supplied to a comparator 6 and a vertical synchronization signal detection circuit 8, which will be described later.

On the other hand, a clock pulse having a color subcarrier frequency (3.58 MHz) is generated from the reference clock generator 2 and is supplied to the clock pulse input terminal CKH of the horizontal synchronization counter (H counter) 3.

The H counter 3 counts the number of clock pulses input from the clock input terminal CKH, and supplies the count value data (see FIG. 3) to the H decoder 4.

The H decoder 4 sets the level of the output signal DO-D6 to a high level or a low level, respectively, according to the value of the count value data supplied from the H counter 3, and outputs the data selector 6.
supply to.

Incidentally, when the count value data supplied from the H counter 3 shows "226-16=210", the H decoder 4 in FIG. 222”, the output signal D1
is set to high level, and the count value data becomes “226-1=
225'', the output signal D2 is set to high level,
When the count value data shows "226+16=242", the output signal D3 is set to high level, and when the count value data shows "226+4=230", the output signal D4 is set to high level, and the count value data becomes "226". ”, the output signal D5 is set to high level, and when the count value data indicates “113”, the output signal D6 is set to high level, and when the count value data indicates “50”, the output signal HREF ( (see FIG. 3) is set to a high level.

The data selector 5 outputs one of the signals DO to D6 supplied from the H decoder 4 in response to select signals 5o to S2 output from the controller 7, which will be described later, and outputs one of the signals DO to D6 supplied from the H decoder 4. Reset terminal RH
The H counter 3 is reset by supplying the signal to the input terminal CKv of a vertical synchronization counter (V counter) 10, which will be described later.

On the other hand, the output signal HREF of the H decoder 4 is supplied to a comparator 6, which detects the phase difference between the HREF and C5ync supplied from the input terminal 1, and outputs signals CO to C3 according to the phase difference. The level of the controller 7 is set to high level or low level respectively.
supply to.

That is, comparator 6 indicates that the phase of C5ync is HRE.
If it is ahead of F, the output signal C1 is set to high level, and if it is behind, it is set to low level.

In addition, the comparator 6 is connected to the supplied C5ync and HRg.
The level of the output signals CO, C2, and C3 is set to high level or low level, respectively, depending on the amount of phase difference between C3ynC and HREF, and the phase difference between C3ynC and HREF is output from the reference clock generator 2. If the number of clock pulses to be output is 8 clocks or more, the output signal C
O is set to a high level, and when it is 4 to 8 clocks, the output signal C2 is set to a high level, and when it is 0 to 4 clocks, the output signal C3 is set to a high level, and these output signals CO to C3 are set to a high level. The level of is maintained for l horizontal synchronization period.

By the way, C5ync (fourth
As mentioned above, the vertical synchronization signal detection circuit 8 is also supplied with the vertical synchronization signal detection circuit 8 during the vertical synchronization blanking period (b in FIG. 4) in the supplied vertical synchronization signal. This is to detect.

In other words, as shown in Figure 4, the vertical synchronization blanking period (b in Figure 4) has a longer bellow level period than the horizontal synchronization blanking period (a in Figure 4), so the vertical synchronization signal is not detected. The circuit 8 counts the period during which the level of the supplied C5ync is low, and sets the output signal to a high level if the count value indicates a period longer than the horizontal synchronous blanking period (a in FIG. 4). , is supplied to the subsequent delay circuit 9.

The delay circuit 9 converts the output signal of the vertical synchronization signal detection circuit 8 into several H
(H is l horizontal synchronization period), vertical synchronization counter (V
The V counter 10 is reset while the signal supplied from the delay circuit 9 is at a high level.

By the way, an equalization pulse is added to C5ync input from input terminal l, and a timing signal of a different type from other periods is sent to H during the equalization pulse period (C in Figure 4) in C5ync. Based on the count value data of the counter 3 and the V counter 10, the vertical synchronization signal detection circuit 8 detects the vertical blanking period as described above, and the equalization pulse of C5ync is generated by the H decoder 4 and the decoder 11. If the V counter lO is reset during the equalization pulse period, there is a risk that the continuity of the timing signal formed during the equalization pulse period will be lost. Therefore, in this embodiment, as described above, by delaying the output signal of the vertical synchronization signal detection circuit 8 by several H by the delay circuit 9, the V counter 10 is reset at a timing sufficiently delayed from the equalization pulse period of C5ync. It is structured like this.

As mentioned above, the output signal of the data selector 5 is supplied to the clock pulse input terminal CKv of the V counter 10, and the V counter 10 counts the number of times the high level signal is supplied from the data selector 5. The value data is output to the V decoder 11.

■When the count value data supplied from the V counter 10 reaches the number of horizontal synchronization pulses within one field period (i.e., 263), the decoder 11 outputs a pseudo vertical synchronization signal V REF, and also outputs a pseudo vertical synchronization signal V REF. When the count value data supplied from the counter 10 reaches a predetermined count value, the output signal BO is set to high level and is supplied to the controller 7.

By the way, as shown in FIG. 1, the still video reproducing apparatus of this embodiment rotates a magnetic disk 100 by a motor 101, and records one frame per recording track formed concentrically on the magnetic disk 100. The camera is configured to record still image signals for a period of time.

Furthermore, although the motor 101 is controlled by a motor servo circuit or the like so as to rotate at a predetermined rotational speed, since it is impossible to completely eliminate rotational unevenness, There are cases where the recording start position and end position of the image signal do not exactly match, resulting in unrecorded portions or overwritten portions.

In the above case, as shown in d in FIG. 4, there is a switching point between the recording start position and end position of the C5ync still image signal separated from the still image signal reproduced from the magnetic disk 100. At the position corresponding to the point, the period of the horizontal synchronization signal is not IH,
In this part, the phase difference between C5ync and HREF becomes large.

Therefore, in the V decoder 11 of this embodiment, the V counter 10
When the count value data supplied from C5ync reaches a count value corresponding to the vicinity of the switching point (several H period), the output signal B1 is set to high level,
is supplied to the controller 8.

The signal input/output operation of the controller 7 in the embodiment shown in FIG. 2 will be explained below using the operation flowchart shown in FIG.

In Figure 2, C5ync input from input terminal 1
and H REF output from the H decoder 4 are supplied to a comparator 6, where the phase difference between the two signals is detected, and the comparator 6 outputs a signal Co-C5 corresponding to the detected phase difference to the controller 8. (See step ST! in FIG. 5).

On the other hand, the V counter IO counts the output signal of the data selector 5 and outputs count value data according to the count value to the V decoder 11, and the V decoder 11 receives the count value data supplied from the V counter 10 as a predetermined value. When the count value of , the output signals BO and Bl are set to high level, and when the V counter counts "262", BO output from the V decoder 11 becomes high level, and the controller 7 outputs the data. For selector 5, So:1, SL+1. S2: Outputs the 1 select signal, and the data selector 5 indicates that the H counter 3 is '113'.
The output signal D6 output from the H decoder 4 when counted is selectively outputted, and the H counter 3 is reset and the V counter 11 is incremented.

By the above operation, for example, the composite synchronization signal to be handled is NTSC.
When conforming to the standard IH television signal, one field period is "262.5H", so the H counter 3 is set during the normal IH period (of the clock pulse output from the reference clock generator 2). (in terms of 226 clocks), half the period (i.e. 113 clocks)
To reset the H R output from the H decoder 4,
Even at the end of one field period, C5yn
It becomes possible to synchronize with c.

Further, when the V counter lO counts a count value corresponding to the vicinity of the switching point of C5ync, B1 output from the V decoder 11 becomes high level, and the controller 7 receives the C5ync output from the comparator 6.
SO: 0, Sl: 1 . B2
:O and SO:1. Sl:0. A select signal of B2:1 is output alternately every IH period, and the data selector 5 is set to H.
Output signal D2.D output from H decoder 4 when counter 3 counts '225' or '226'
5 is selected and output alternately every IH period to reset the H counter 3 and count up the V counter 10 (see steps ST to ST? in FIG. 5).

Through the above-described operation, the H REF output from the H decoder 4 can be synchronized with C5ync at the position corresponding to the switching point on the magnetic disk 100 in FIG. 1.

Then, when both BO and Bl output from the V decoder 11 are at low level, the controller 7 outputs an output from the comparator 6 according to the direction of the phase shift (leading or lagging) and the amount of phase difference between C5ync and HREF. It outputs select signals SO to S2 corresponding to CO to C3.

First, in comparator 6, C5ync and HREF
When it is detected that the phase difference between the reference clock generator 2 and the reference clock generator 2 is 0 to 4 clocks in terms of the number of clock pulses output from the reference clock generator 2, Co and C2 become low level and C3 becomes high level. , furthermore, when the phase of C5ync is ahead of HREF, C1 becomes high level, and the controller 7 sends SO:O, Sl: to the data selector 6.
1. B2:0 select signal is output, data selector 5 selects and outputs output signal D2 output from H decoder 4 when H counter 3 counts "225", and the phase of C5ync lags behind HREF. If so, CI becomes low level, and the controller 7 outputs a select signal of 5oil, Sl:O, B2:1 to the data selector 5. Selectively outputs the output signal D5 output from the H decoder 4, resets the H counter 3, and increments the V counter 10 (
(See steps ST, -ST, 4 in FIG. 5).

The signal D2 or B5 output from the data selector 5 by the above operation sets the H counter 3 to 1 for the normal reset period (226 clocks in terms of the number of clock pulses output from the reference clock generator 2). Since the reset is performed at a timing shorter by one clock, the H REF output from the H decoder 4 can be brought close to the phase of Cs y rtc and synchronized.

Next, when the comparator 6 detects that the phase difference between C5ync and HREF is 4 to 8 clocks in terms of the number of clock pulses output from the reference clock generator 2, CO becomes low level. , C2 become high level, and furthermore, when the phase of C5ync is ahead of HREF, CI becomes high level, and the controller 7 sends SO:1, Sl:O, B2: to the data selector 5.
The data selector 5 selectively outputs the output signal DI output from the H decoder 4 when the H counter 3 counts "222", and the data selector 5 outputs the select signal of C5yn.
If the phase of c lags behind HREF, C1 becomes low level, and controller 7 outputs SO to data selector 5: O.

Sl:0. The data selector 5 outputs the select signal of B2:1, selects and outputs the output signal D4 output from the H decoder 4 when the H counter 3 counts "230", resets the H counter 3, and outputs the output signal D4 of the V counter lO.
(Step ST8 in Figure 5)
ST9 + 5TIll~ST1. reference).

Through the above operation, the signal D1 or B4 output from the data selector 5 resets the H counter 3 for the normal reset period (226 clocks in terms of the number of clock pulses output from the reference clock generator 2). In order to reset with a timing as short as 4 clocks or as long as 4 clocks, the H REF output from H decoder 4 is set to C5y.
It becomes possible to synchronize close to the phase of nc.

Furthermore, if the comparator detects that the phase difference between C5ync and HRKF- is equal to or more than 8 clocks in terms of the number of clock pulses output from the reference clock generator 2, CO becomes high level. .

In this embodiment, in the comparator 6, C5ync and H
If it is detected that the phase difference with REF is 8 clocks or more in terms of the number of clock pulses output from the reference clock generator 2, noise may be mixed into C5ync or dropout may occur. It is considered as something that has occurred.

Then, when the phase of C5ync is ahead of HREF, C1 becomes high level, the controller 7 outputs select signals of 5olo, Sl:O, B2:0 to the data selector 5, and the data selector 5 goes high. When the counter 3 counts "210", the output signal DO output from the H decoder 4 is selected and output, and when the phase of C5ync lags behind HREF, C1 becomes low level, and the controller 7 selects and outputs the output signal DO output from the H decoder 4. SO: 1. Sl:1. B2: Outputs the O select signal, and the data selector 5 outputs the output signal D3 output from the H decoder 4 when the H counter 3 counts "242".
is selected and output, the H counter 3 is reset, and the V counter 11 is counted up (step S in Fig. 5).
(See T8, 5T20 to STu).

Even if C5ync becomes abnormal due to the above operation, the signal D5 output from the data selector 5 causes the H counter 3 to reset at the normal reset period (reference clock generator 2
Since it is reset by 226 clock pulses (converted to the number of clock pulses output from The H counter 3 is reset at the normal reset period (reference clock generator 2
In order to reset the clock at a timing that is 16 clocks shorter or longer than the number of clock pulses output from the C5sync (converted to 226 clocks), the H REF output from the H decoder 4 should be synchronized close to the phase of C5ync. You will be able to do this.

By the way, each of the above-mentioned operations is performed by the data selector 5,
After one type of signal from DO to D6 is output from the H decoder 4, steps ST in FIG.
C5ync and HRE are returned to comparator 6.
A phase comparison with F is performed, and the above operation is repeated.

The H decoder 4 generates the H as described above.
REF and V REF generated from V decoder 11
are supplied to the timing signal generator 12, where the supplied H REF , V RE
Using the F pulse as a trigger, a composite synchronization signal (Csyn
c) A blanking signal B1 skew compensation gate signal S having a preset pulse width is formed and output.

The blanking signal B thus formed is supplied to the image signal processing circuit 110, the composite synchronization signal C5ync is supplied to the synchronization signal addition circuit 111, and the skew compensation gate signal S is supplied to the changeover switch 113.

The image signal processing circuit 110 is the timing signal generation circuit 11
5 performs horizontal and vertical blanking processing on the image signal supplied from the demodulation circuit 104 based on the blanking signal B supplied from the demodulation circuit 104. Adding the composite synchronization signal C5ync formed in the timing signal generation circuit 115 to the processed image signal for one field, and supplying it to the 1/2H delay circuit 112 and the a terminal of the changeover switch 113; The 1/2H delay circuit 112 delays the supplied image signal by 1/2H period and supplies it to the b terminal of the changeover switch 113.

The changeover switch 113 is configured to alternately switch the connection between the a terminal side and the b terminal side in the figure every one field period in accordance with the skew compensation gate signal S generated by the timing signal generation circuit 115. , the frame image signal is output from the changeover switch 113 to the output terminal 11.
4.

As described above, in this embodiment, instead of adding the composite synchronization signal separated from the image signal reproduced from the magnetic disk to the reproduced image signal that has been subjected to skew compensation processing, as in the conventional case, the reproduced image signal After forming a composite synchronization signal that is phase-synchronized with the composite synchronization signal separated by the above, and also forming a skew compensation gate signal for controlling skew compensation processing, and adding the formed composite synchronization signal to the reproduced image signal. By performing skew compensation processing on the reproduced image signal to which the formed composite synchronization signal is added based on the skew compensation gate signal, the continuity of the horizontal synchronization signal is maintained at the boundary point of each field. At the same time, it becomes possible to prevent deterioration of the composite synchronization signal.

In addition, even if the C5ync changes, the phase of the playback timing signal is not instantaneously corrected (but is configured to be corrected in predetermined amount increments), so it is not disturbed by disturbances such as noise, and is stable. It becomes possible to obtain a reproduction timing signal.

Furthermore, as shown in this example, the circuit configuration is digital, so there is no need for adjustments, stable performance is obtained even with changes in the environment such as temperature and humidity, and the circuit size can be reduced. Since it is small-scale, it is easy to integrate it into an IC, and it becomes possible to reduce the mounting area and number of parts in the device.

In this embodiment, a still video playback device that handles a still image signal based on an NTSC television signal has been described as an example, but the present invention is not limited to this.
A similar configuration can also be used for a device that complies with CAM television signals, and in this case, in order to correspond to each system, the length of the horizontal synchronization period and the length of the vertical synchronization period, that is, The timing for resetting the H counter 3 and v counter 10 in FIG. 2 may be changed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to maintain the continuity of the horizontal synchronization signal even after skew compensation processing, and a composite synchronization signal without deterioration can be output together with the reproduced image signal. It becomes possible to provide an image signal reproducing device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a still video reproducing apparatus that handles still image signals based on NTSC television signals, as an embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of the timing signal generation circuit shown in FIG. 1. 3 and 4 are timing charts showing signal waveforms at various parts of the timing signal generation circuit shown in FIG. 2. FIG. FIG. 5 is an operation flowchart for explaining the operation of the timing signal generation circuit shown in FIG. 2. FIG. 6 is a diagram showing a schematic configuration of a conventional still video playback device. 1...Composite synchronization signal input terminal 2...Reference clock generator 3...Horizontal synchronization counter 4...H decoder 5...Data selector 6...Comparator 7...Controller 8... Vertical synchronization signal detection circuit 9...Delay circuit IO...Vertical synchronization counter 11...V decoder 12...Timing signal generator 2 As shown in the figure

Claims (1)

[Scope of Claims] An apparatus for reproducing an image signal recorded on a recording medium, comprising: reproducing means for reproducing the signal recorded on the recording medium; and a reproduction means for reproducing the image signal from the image signal reproduced by the reproducing means. a composite synchronization signal separating means for separating a first composite synchronization signal added to the signal; and forming a second composite synchronization signal phase-synchronized with the first composite synchronization signal separated by the composite synchronization signal separation means. a composite synchronizing signal forming means for generating a second composite synchronizing signal in place of the first composite synchronizing signal added to an image signal reproduced from the recording medium by the reproducing means;
a composite synchronization signal adding means for adding and outputting a composite synchronization signal; and a skew unit for performing skew compensation processing on the image signal to which the second composite synchronization signal outputted from the composite synchronization signal addition means is added. An image signal reproducing device characterized by comprising compensation processing means.