JPH0225163Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to an eddy current flaw detection device capable of identifying the types of various flaws. The signal to be processed in an eddy current flaw detector originates from changes in the electrical impedance of the flaw detection coil, which is the detection end, and the impedance of the coil is mainly caused by the alternating magnetic field generated by the AC excitation current applied to the coil. Become. This alternating magnetic field generates eddy currents on the surface and directly below the surface of the metal material (hereinafter referred to as the test object) that is placed in close proximity and is the subject of non-destructive testing. When the coil passes through the area due to the relative movement between the test object and the flaw detection coil, the change in eddy current becomes a change in coil impedance, and by converting this into a change in voltage or current. A flaw signal is generated and an eddy current flaw detection operation is performed. It is well known that the magnitude of the real and imaginary parts of the change in coil impedance changes depending on the properties such as the shape, size, and depth of the flaw, and that it also changes depending on the period or frequency of the applied excitation current. . From this point of view, the optimal value of the frequency used in eddy current flaw detection as a non-destructive test of metal materials has been theoretically determined, and it has also been confirmed experimentally, and eddy current flaw detection is performed at the determined optimal frequency. There is. However, in recent years, the requirements for eddy current flaw detection have become increasingly sophisticated, requiring improvements in the ability to distinguish between multiple types of flaws, appropriate emphasis on harmful flaws and harmless flaws, and suppression processing ability. The present invention was devised to meet such requirements, and is an eddy current flaw detection apparatus equipped with an eddy current flaw detection head and a phase detector that discriminates the phase of the output of the head and outputs a flaw signal. The present invention includes low-frequency and high-frequency bandpass transducers to which outputs are input and given a predetermined signal passband suitable for flaw type identification, and an arithmetic circuit that calculates the ratio of the outputs of these transducers. Features. According to this device, multiple types of flaws can be identified according to their properties, and detected flaws can be arbitrarily treated as harmful or harmless for flaw detection. Next, this will be explained in detail with reference to the drawings. An eddy current flaw detection test is performed on a tubular metal body, and the phase-detected flaw signal is plotted with time t on the horizontal axis and amplitude A.
When expressed on the vertical axis, it becomes as shown in FIG. This kind of drawing is done using an oscilloscope (CRT).
In this figure, _C1 is a notch flaw on the inner surface, _C2 is a file scratch on the outer surface, and _C3 is a ring-shaped flaw on the outer surface. These recording waveforms C ₁ , C ₂ ,
At first glance, C ₃ appears to have the same form, but when we analyzed its energy spectrum, we found that it has a distribution as shown in Figure 2. The horizontal axis of FIG. 2 is scaled with the frequency NF which is the normalized flaw signal, and the actual frequency can be read as appropriate using the relative velocity between the flaw detection coil and the object to be inspected.
Further, the vertical axis indicates the normalized output signal amplitude NA.
C ₁ , C ₂ and C ₃ correspond to those in FIG. Note that the characteristics of the spectral distribution form of the flaw signal waveform shown by C ₁ , C ₂ , C ₃ , etc. in Figure 1 change not only depending on the nature of the flaw, but also depending on the mechanical structure and dimensions of the flaw detection coil. . Now, set the passband of a bandpass filter (BPF) with a specific narrowband pass characteristic as shown in A and B in Figure 2, and create the waveform C ₁ in Figure 1.
When the flaw signal of ~C ₃ is passed through these BPFs and its output is determined, the output of the BPF of passband A is C ₁
The output of the BPF _for passband B is C _1a to C _3a for C ₃ to C _1b to C 3b for C ₁ to _{C 3} , specifically as shown in the table below. Although not shown in FIG. 2, white noise has a uniform energy spectrum within the passband.

【table】

[Table] As shown in this table, the ratio A/B is flaw C ₁ ,
They are 2.8, 18, and 1.7 for C ₂ and C ₃ , respectively. If we calculate the ratio of the output voltages of the A-band and B-band extraction results, we can obtain an energy spectrum that is unique to the type of flaw, without being affected by the amplitude of the flaw signal, which changes depending on the size or depth of the flaw. It is possible to accurately determine the type of flaw by capturing the characteristics of the flaw. Furthermore, errors in calculation results are less likely to be caused by interference from small-amplitude background noise. In general, it can be judged that the amplitude of the flaw signal voltage is approximately proportional to the flaw depth, but it varies from those with a large phase detection output voltage, which corresponds to a deep flaw, to those with a small voltage, which corresponds to a shallow flaw, and to each other. As described above, without analyzing the entire frequency spectrum distribution of the signal in detail, the signal components are extracted only in certain ranges A and B, which have characteristics of the spectrum distribution of each flaw signal, and their ratios are determined. A feature of the present invention is that it performs type determination. In order to correctly recognize patterns for all spectral distributions of a signal, a given flaw signal can be processed using multiple BPFs that have extremely narrow bands and whose passbands are continuous. A single continuously variable BPF must be used to measure and record the filter output. Figure 2 shows an example of measurement and recording using a spectrum analyzer with a digital processing function that performs the analysis described above. In automatic flaw detection sites, the target waveforms must be individually selected, designated and input for analysis by the flaw detection tester who has the judgment ability acquired through experience, and is processed continuously. However, the method of the present invention is easy to implement. In this invention, the operation of selecting the above signals individually and inputting them as analysis identification signals is necessary.In this invention, all signals exceeding a prespecified amplitude voltage obtained as the output of the amplitude level discriminator are analyzed. , Examination, Analysis The time period for examination is determined by the relative speed between the flaw detection coil and the test object, etc., and the sampling time is set in advance to have a time width of one cycle of a value corresponding to the frequency spectrum distribution area determined by the speed. It relies on the means of generating by a generator. Unnecessary signals that are not flaw signals and harmless flaw signals can be identified and separated based on the value of the calculation result. For example, in the case of a noise signal voltage on the irregular side, it has uniform frequency energy within the amplification band of the signal processing amplification system. As shown, the calculation results for the flaw signal are 2.8, 18, and 1.7, respectively.
It is. Next, an embodiment of the present invention is shown in FIG. In Figure 3, Ta and Tb are input terminals, 1 is a buffer amplifier, 2 is a phase detector, 3 is a phase shifter, 4 is a buffer amplifier or phase divider, 5 is a voltage discriminator, and 6 is a discrimination critical voltage setter. , 7 is a sampling time (sampling gate pulse) generator, 8 is a time width setter, 9 is a sampling gate, 10 is an analog signal delay circuit, and 11 is a clock pulse generator. Further, 12 is a low-frequency band waver, 14 is a high-frequency band waver, 13 and 15 are signal pass band range setting devices for these wavers, 16 is an amplifier, 17 is an analog arithmetic (divider) unit, 20, 22, 24 are voltage discriminators, 21, 23, 25 are reference voltage generators for discrimination, 26, 27, 28 are relay drivers, rl ₁ ,
rl ₂ and rl ₃ are relay contacts, and Tc to Te are output terminals. To explain the operation, the input terminal Ta receives the output of the flaw detection head H, which has a balancing bridge and a cancellation voltage circuit connected to the legs of the flaw detection coil. The output voltage at the test frequency is processed to be zero and applied via a suitable amplifier. The input signal to this terminal Ta is a modulated wave that undergoes phase and amplitude changes when the flaw detection coil faces a physical irregularity such as a flaw on the test object, and this phase and amplitude modulation occurs between the flaw detection coil and the test object. The duration and the form of change vary depending on the relative velocity of the magnetic field, the magnetic field distribution that changes depending on the mechanical dimensions of the flaw detection coil, and the type or form of the flaw. On the other hand, a constant voltage to be applied to the flaw detection coil and a voltage at a frequency are branched and applied to the input terminal Tb, which serves as a reference voltage for phase detection. The modulated wave applied to the terminal Ta is applied to the phase detector 2 via the amplifier 1, and the reference voltage from the terminal Tb is suitably phase shifted by the phase shifter 3, and is applied to the amplifier or phase divider 4. The signal is then applied to the other input terminal of the phase detector 2. The phase and amplitude modulation of the flaw detection coil excitation current that occurs when the flaw detection coil senses a flaw or the like on the object is demodulated by the phase detector 2, and a low frequency flaw signal in the form of, for example, a one-cycle AC wave is generated. Although not shown, on the output side of the phase detector 2, there are a flaw detection coil excitation frequency (generally a frequency several times higher than the above-mentioned low frequency flaw signal) and a gradual wave frequency that is closer to the flaw frequency obtained from the surface of the object. A filter is provided to remove low frequencies containing direct current that exhibit significant changes. The output of the phase detector 2 is applied to a voltage discriminator 5 which operates for both positive and negative polarities, and the discriminator has a reference voltage for comparison arbitrarily set by a setting device 6,
Regardless of the polarity of the input wave, an output is produced for an input that exceeds the set voltage for the duration of the exceedance.
The output of this discriminator 5 is applied to a sampling gate pulse generator 7 which is connected to a voltage discriminator 5.
It responds to both the rise and fall of the output.
The output pulse width of the generator 7 can be set arbitrarily by the setting device 8. Specifically, the generator 7 is composed of a one-shot multivibrator, and the output pulse width can be changed by changing one or both of its resistance and capacitor using the setting device 8. The output pulses of the generator 7 are applied to a gate 9, the other input of which is applied the output low frequency signal of the phase detector 2 via a delay network 10. In this example, the delay circuit network 10 consists of an A/D converter, a shift register, and a D/A converter, and the delay time is adjusted by adjusting the output frequency of the clock pulse generator for the shift register. As the network, an ultrasonic delay circuit or the like may be used in addition to the above-mentioned shift register or the like. The reason for introducing this delay is that when the voltage discriminator 5 operates, the flaw signal has passed the zero point, so the first rising part of the waveform of the signal input to the bandpass filter, which will be described later, is partially cut off. However, if left as is, the high frequency component of the rising portion of the waveform may mix into the signal in the filter, leading to erroneous calculation results, so this should be prevented. That is, when the voltage discriminator 5 starts operating, the signal has already risen. Therefore, the flaw signal is intentionally delayed and handled so that the flaw signal has not yet risen at the time of activation of the gate pulse activated by the discriminator. The flaw signals extracted given a predetermined sampling time are simultaneously input in parallel to the low and high band BPFs 12 and 14. The BPFs 12 and 14 use the aforementioned passbands A and B as their passbands. The passbands of the low and high frequency BPFs 12 and 14 are manually set by setting devices 13 and 15. BPF
FIG. 5 shows an example of typical waveforms at each section until the analytical calculation signal is obtained at the output terminals 12 and 14. In this Figure 5, 1 is the input signal applied to the terminal Ta, 2
is the reference signal applied to the terminal Tb, 3 is the output of the phase detector 2, 4 is the output of the discriminator 5, 5 is the output of the sampling time generator 7, 6 is the output of the delay network 10, 7 is the sampling gate 9 is the output of the low-frequency band waver 12, and 9 is the output of the high-frequency band waver 14 or the amplifier 16. An amplifier 16 is connected to the output side of the high-frequency BPF 14, which improves the S/N of the output of the BPF 14 with respect to background noise, and increases the absolute value of the extracted signal within the passband of the filter to the BPF 12. This is intended to approximate the value of the output signal of the ratio calculator 17 in the subsequent stage so that the calculation result approaches the integer 1 or 2 and the calculation error is small. Therefore, if the voltage absolute value of the flaw signal amplitude is relatively large and a simple type is required, the amplifier 16 may be omitted. The outputs of the BPFs 12 and 14 are input to a divider 17, and the divider 17 outputs A/B. Divider 1
7 is an analog circuit in this example, but it may also be a digital circuit. Note that when looking at the quotient using an analog calculator, the quotient changes depending on the mutual phase difference between the two types of BPF outputs input to each,
It is not a simple amplitude ratio. This means that a quotient with a delicate content can be obtained depending on the setting of the BPF passband, and the present method is effective in this respect. Note that if a peak value holding circuit is provided at the input terminals of the arithmetic units 12 and 14, the above quotient becomes the same as the result of a simple digital ratio calculation. In the case of digital calculation, as shown in Fig. 4, after the BPF 12 and the amplifier 16, the
D converters 18a and 18b are provided, and a digital arithmetic unit 18 is provided that calculates A/B from the A/D conversion output thereof. The arithmetic unit 18 is also provided with a guide number setting device 19 for determining the digital calculation result. This setting device 19 divides the digital output from the calculator 18 into a plurality of stages and outputs them, and treats each division as a flaw identification result. In the case of the analog method, the output of the arithmetic unit 17 is a plurality of voltage discriminators 20 for the signal voltage of the arithmetic result,
22, 24, and the generator 2 is added to the discriminator.
Reference voltages for discrimination are applied from 1, 23, and 25,
The output of the arithmetic unit 17 is classified into grades. The outputs of the voltage discriminators 20, 22, 24 are relay drivers 26,
27, 28, and the driver contacts one of the relay contacts rl ₁ , rl ₂ , rl ₃ when energized by the discriminator output.
) and outputs the flaw judgment identification results from terminals Tc, Td, and Te. If a logic gate is provided in this circuit to perform mutual interlock, the quotient of the calculation result will be the voltage discriminator 20, 22, 24.
Even if the value indicates a boundary value that causes a plurality of outputs, one of the relays will be activated. In this embodiment, various manual setting devices, especially the repetition frequency of the clock pulse generator 11 for adjusting the delay time of the analog signal, which must be set appropriately using the relative speed between the flaw detection coil and the test object as a parameter, and the signal If the cutoff frequencies of the passband setters 13 and 14 of the plurality of band wavers 12 and 14 for spectrum analysis and extraction are set as shown in FIG. 6, more complete functional operation can be expected. . In this figure 6, 3
0 is a relative speed detection device whose output voltage is passed through the first linearizer 31 to the clock pulse generator 1.
1 to control its output repetition frequency. Further, the above output voltage is applied to the passband setters 13 and 15 of the BPF 12 and 14 via the second and third linearizers 32 and 33, and the passband is automatically activated and functions according to the relative speed. can be done. As explained in detail above, according to the present invention, it is possible to identify the type of flaw by relatively simple means, and it is also possible to easily infer whether the flaw is harmful or harmless, what is the cause of its occurrence, etc. . Moreover, since the identification is carried out automatically, an alarm circuit can be connected to the output terminal, for example Te, to immediately issue an alarm for particularly harmful flaws. Furthermore, since the signals used for arithmetic processing are gated by the gate circuit 9 so that only the defect signal is extracted, there is an advantage that the S/N ratio is improved and the identification result is accurate.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram showing an example of a flaw signal, Figure 2 is a graph showing the results of frequency spectrum analysis of the flaw signal in Figure 1, Figure 3 is a block diagram showing an embodiment of the present invention, and Figure 5. 1 to 9 are diagrams showing signal waveforms of various parts of the circuit of FIG. 3, and FIGS. 4 and 6 are block diagrams showing main parts of other embodiments of the present invention. In the drawing, H is an eddy current flaw detection head, 2 is a phase detector,
12, 14 are low and high frequency band wavers, 20, 2
2 and 24 are circuits that generate flaw type signals, and 9 is a gate circuit.

Claims (1)

[Claims for Utility Model Registration] (1) In an eddy current flaw detection device equipped with an eddy current flaw detection head and a phase detector that discriminates the phase of the output of the head and outputs a flaw signal, the output of the phase detector is input and the type of flaw is detected. What is claimed is: 1. An eddy current flaw detection device comprising: low-pass and high-pass bandpass transducers provided with predetermined signal passbands suitable for identification; and an arithmetic circuit that calculates the ratio of the outputs of these transducers. (2) The eddy current flaw detection apparatus according to claim 1, which is characterized by comprising a circuit that receives the output of the arithmetic circuit, compares it with a preset level, and generates a signal indicating the type of flaw. (3) A gate circuit is provided on the output side of the phase detector, which opens for a certain period of time to pass the output when the output is above a predetermined value, and each of the low-frequency and high-frequency bandpass waveforms is connected to the gate circuit. An eddy current flaw detection apparatus according to claim 1 or 2, characterized in that it is configured to provide an output of .