JPH02250355A - Pattern structure of standard cell - Google Patents

Abstract

PURPOSE:To apply a one-layer aluminum wiring pattern process to a multilayer aluminum wiring pattern process by a method wherein positions of input pins and output pins in a multilayer aluminum wiring process are aligned with positions of the same pins in a one-layer aluminum wiring process. CONSTITUTION:A pattern of an input electrode 13 composed of an aluminum wiring part in a second layer is completely the same shape as a pattern of a gate electrode 11 composed of a polysilicon wiring part at a lower layer; in the same manner, a pattern of an output electrode 14 is the same as a pattern of an output electrode 12 at a lower layer excluding a connecting part to a connecting electrode 5. The gate electrode 11 and the input electrode 13 are wired in an identical input-pin position; the output electrodes 12, 14 are wired in an identical output-pin position. Accordingly, a one-layer aluminum wiring process can be used for a two-layer aluminum wiring process. Thereby the one-layer aluminum wiring process can be used for a multilayer aluminum wiring process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring pattern structure of a standard cell forming a part of an integrated circuit. Regarding structure.

[Conventional technology]

FIGS. 2 and 3 show the wiring pattern structure of a conventional standard cell, that is, an inverter in which a P-channel MO3FETI and an N-channel MO3FET2 are connected in a complementary manner as shown in FIG.

First, FIG. 2 shows an example applied to a standard cell for relatively low-speed operation, and is a diagram showing a pattern structure based on a single-layer aluminum wiring process.

Here, the extraction electrode 3 of the source S1 of FET1, FE
Extraction electrode 4 of source 2S of T2 and both FETI 2
A connection electrode 5 that connects (contacts) the drain ID and 2D of the F is formed with the first layer of aluminum wiring, and
Gate electrode 6 forming gate IG and 2G of ETI and 2
are formed of polysilicon wiring, and these are also used as input electrodes. Further, the output electrode 7 connected to the connection electrode 5 is also formed of polysilicon wiring. A is the input pin position, and B is the output pin position.

In this pattern structure, the extraction electrode 3 is supplied with a power supply VOO, and the extraction electrode 4 is supplied with a power supply V. are applied respectively. In addition,
The electrodes 3 and 6.7 and the electrodes 4 and 6.7 are insulated by insulating films (not shown).

Next, FIG. 3 shows an example applied to a standard cell for relatively high-speed operation, and is a diagram showing a pattern structure based on a 2N aluminum wiring process.

Here, the extraction electrode 3 of the source IS of the FETI, the FE
The extraction electrode 4 of the source 2S of T2, and both FETI, 2
The connection electrode 5 that connects the drain ID and 2D is created using the first layer of aluminum wiring (the above is the same as the example in Figure 2).
Furthermore, gate electrodes 8 constituting both FETIs (gates IG and 2G of FETI 2) are formed of polysilicon wiring.

An input electrode 9 connected to the gate electrode 8 and an output electrode 10 connected to the connection electrode 5 are each formed of a second layer of aluminum wiring.

In this pattern structure, the extraction electrode 3 is supplied with a power supply VIID, and the extraction electrode 4 is supplied with a power supply V. The point that is applied to each is the same as in FIG. 2. In addition, between electrode 3 and 9.10, electrode 4
and 9.10 are insulated by an insulating film (not shown).

As described above, the pattern structure (FIG. 3) based on the two-layer aluminum wiring process was created by a process completely different from the lli aluminum wiring process, without drawing out the polysilicon wiring pattern as input/output electrodes.

[Problem to be solved by the invention]

Therefore, the pattern structure for the IN aluminum wiring process (FIG. 2) could not be used for the two-layer aluminum wiring process (FIG. 3), and vice versa.

In addition, a standard cell with a pattern structure based on a two-layer aluminum wiring process is created completely independently from a standard cell with a pattern structure based on a single-layer aluminum wiring process, so the input/output pin positions A and B and sizes are different. Therefore, when performing automatic placement and wiring, it was necessary to create separate databases for each placement and wiring.

The present invention has been made in view of the above points,
The purpose is to provide a standard cell wiring pattern structure that allows a single layer aluminum wiring pattern process to be applied to a multilayer aluminum wiring pattern process.

[Means to solve the problem]

To this end, the present invention provides, in a standard cell pattern structure having input and output electrodes made of polysilicon wiring formed by a single-layer aluminum wiring process, the input and output electrodes formed of aluminum wiring formed by a multilayer aluminum wiring process from polysilicon. They were formed on the upper layer of the input and output electrodes made of wiring, and the positions of the manual pins and output pins in the multilayer aluminum wiring process were matched to the positions of the same pins in the single layer aluminum wiring process.

〔Example〕

The present invention will be explained in detail below. FIG. 1 is a diagram showing a two-layer aluminum wiring pattern structure of one embodiment.

Components that are the same as those shown in FIGS. 2 to 4 are given the same reference numerals.

In this embodiment, the gate electrodes 11 constituting the gates IG and 2G and the output electrodes 12 connected to the connection electrodes 5 are each formed of polysilicon wiring, and the input electrodes 11 connected to the gate electrodes 11 and wired on the upper surface thereof are formed using polysilicon wiring. The electrode 13 and the output electrode 14 connected to the connection electrode 5 and wired on the upper surface of the output electrode 12 were each formed of a second layer of aluminum wiring.

The input electrode 13 made of the second layer of aluminum wiring has exactly the same pattern as the gate electrode 1 made of the polysilicon wiring in the lower layer, and the output electrode 14 similarly connects to the output electrode 12 and the connection electrode 5 in the lower layer. The pattern is the same except for the connecting part.

Therefore, the input electrode 11 made of the second layer of aluminum wiring
, the one-layer aluminum wiring pattern structure excluding the output electrode 12 and the two-layer aluminum wiring pattern structure shown in FIG. 1 have the same arrangement and size of the picture electrodes 11.12 and the picture electrodes 13. Therefore, in the two-layer aluminum wiring pattern structure, the same automatic placement and wiring as in the one-layer aluminum wiring pattern structure can be performed.

As described above, in this embodiment, the gate electrode 11 and the input electrode 13 are wired to the same manual pin position, and the output electrodes 12 and 14 are wired to the same output pin position, so the one-layer aluminum wiring process is performed using a two-layer aluminum wiring process. Wiring process can be used.

〔Effect of the invention〕

As explained above, according to the present invention, the multilayer aluminum wiring pattern is arranged at the same input pin position and the same output pin position as the single-layer aluminum wiring pattern, so the single-layer aluminum wiring process is added to the multilayer aluminum wiring process. can be used.

As a result, development costs and time for both processes can be reduced, the layout and size of input/output pins can be made the same for both processes, and only one type of database can be used for automatic placement and routing. It has the characteristic of being finished.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the pattern structure of a standard cell according to an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of the pattern structure of a conventional standard cell, and FIG. 4 is a circuit diagram of the standard cell. . 1... P channel MO3FET, 2... N channel MO3FET, 3... Drain extraction electrode (1 layer aluminum wiring), 4... Source extraction electrode (1 layer aluminum wiring), 5... Connection electrode (1-layer aluminum wiring vA), 6... Gate electrode (polysilicon wiring), 7... Output electrode (polysilicon wiring), 8...
Gate electrode (polysilicon wiring), 9... input electrode (
2-layer aluminum wiring), 10... Output electrode (2-layer aluminum wiring), 11... Gate electrode (polysilicon wiring), 12... Output electrode (polysilicon ti)
, 13... Input electrode (two-layer aluminum wiring), 14
...Output electrode (two-layer aluminum wiring). Agent Patent Attorney Tsuneaki Nagao Figure 1 Figure 2 b lj NDS 2G 2D Figure 8

Claims (1)

[Claims] (1) In a standard cell pattern structure comprising input and output electrodes made of polysilicon wiring formed by a single-layer aluminum wiring process, the input electrodes and output electrodes formed of aluminum wiring formed by a multilayer aluminum wiring process are formed of the above polysilicon wiring. A standard cell pattern structure formed on an upper layer of input electrodes and output electrodes, and characterized in that the positions of the input pin and output pin in the multilayer aluminum wiring process are matched to the positions of the pins in the single layer aluminum wiring process.