JPH0512381A - Semiconductor integrated circuit designing device - Google Patents

Abstract

PURPOSE:To set layout which is high in the degree of integration degree without any extra wiring area by judging the connection relation of circuit elements and putting the elements in blocks, and arranging the blocks in parallel. CONSTITUTION:An adjacent circuit block connection alteration part 2 alters the connection relations of circuit blocks, formed by connecting one or plural constituent elements, according to the structure of the circuit so that every four circuit blocks having inverters connected to one terminal of, for example, a NAND gate are connected in parallel. According to this connection relation, a unit circuit composition part 4 composes layout information on the constituent elements in such combinations that constituent element in connection relation are not arranged at a distance. Then a multi-bit parallel arrangement part 6 arranging pieces of composed layout information corresponding to the number of parallel connections in parallel and puts them in blocks, which are connected to similar blocks of constituent elements in connection relations to generate layout information on the circuit to be designed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for designing a layout of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A circuit such as an adder, an ALU, a shift register, a multiplier, etc., which processes a plurality of bits of data in parallel, processes a plurality of bits of data in parallel. There is a circuit having a data path structure for processing a plurality of bits by connecting in parallel circuits corresponding to the number of bits for processing the unit bits. When designing a layout of a semiconductor integrated circuit such as a microprocessor including such a circuit, layout information of a semiconductor integrated circuit (hereinafter referred to as a unit bit processing circuit) that processes a unit bit is prepared in advance by using a data path structure. I'll do it.
Layout information of unit bit processing circuits of a number corresponding to the number of bits to be processed in parallel is arranged in parallel, and layout information of functional blocks such as an adder, an ALU, a shift register, and a multiplier that processes a plurality of bits is generated. Then, the layout information of the functional blocks is connected to complete the layout of the semiconductor integrated circuit of the microprocessor. The semiconductor integrated circuit design device automatically designs a layout of a semiconductor integrated circuit having a structure defined by parameters given by a designer or the like.

FIG. 1 is a block diagram showing a configuration of a conventional semiconductor integrated circuit designing apparatus. In FIG. 1, reference numeral 1 is an instruction parameter input from a terminal or the like to define a structure of a semiconductor integrated circuit to be layout-designed. Is. The unit circuit block information file 3 stores, as unit circuit block information, layout information such as an inverter, a NAND gate, which is a circuit of a processing unit having the smallest arithmetic processing. The multi-bit parallel arranging unit 6 arranges the unit circuit block information stored in the unit circuit block information file 3 in parallel in a number corresponding to the parameter of the circuit whose structure is defined by the instruction parameter 1 and multi-bits. Generate circuit block information. This multi-bit circuit block information is stored in the multi-bit circuit block information file 7.

The layout design unit 8 reads multi-bit circuit block information corresponding to the input instruction parameter 1 from the multi-bit circuit block information file 7, layouts and layouts it, and generates layout information of the semiconductor integrated circuit. The layout information is stored in the layout information file 9.
The layout information stored in the layout information file 9 is subjected to, for example, graphic editing conversion processing or data conversion processing, and is output to a semiconductor integrated circuit manufacturing apparatus or the like. The semiconductor integrated circuit manufacturing apparatus manufactures a semiconductor integrated circuit by generating mask data from given data.

A specific example of the design by the conventional semiconductor integrated circuit designing apparatus having the above-mentioned configuration will be described with reference to the layout design of the circuit shown in FIG. In FIG. 2, 11 is an inverter, and 12 is a NAND gate, which is connected to the input terminals a1 and a2.
OR to output terminal b1, OR with a3 and a4 to b2, OR with a5 and a6
Is output to b3 and the OR of a7 and a8 is output to b4. 3 and 4 are layout information of the inverter 11 and the NAND gate 12 stored in the unit circuit block information file 3, FIG. 3 showing the layout information of the inverter 21 and FIG. 4 showing layout information of the NAND gate 22. ..

In FIG. 3, reference numeral 211 is a gate which is an input line of the inverter 21, 212 is an output line, 213 is an active region forming an N-channel transistor, 214 is an active region forming a P-channel transistor, and 215 is each active region. Area 213,
This is a contact that connects 214 and the output line 212.

In FIG. 4, 221, 222 are input lines, 223 is a gate line, and the gate line 223 is connected to each of the input lines 221, 222 through a contact 215. Reference numeral 224 is an output line, 213 is an active region forming an N-channel transistor, 214 is an active region forming a P-channel transistor, and 215 is a contact connecting each active region 213, 214 and the output line 224. 3 and 4, the power supply line and the GND line are omitted for ease of explanation.

The multi-bit parallel arranging unit 6 develops the layout information 21 of the inverter for 8 bits in parallel and the layout information 22 of the NAND gate for 4 bits in parallel. 5 and 6 show multi-bit circuit block information consisting of layout information of the inverter 11 and the NAND gate 12 developed in parallel. This multi-bit circuit block information is stored in the multi-bit circuit block information file 7. To be done. The placement and routing design unit 8 places and routes the multi-bit circuit block information as shown in FIGS. 5 and 6 to generate layout information as shown in FIG. 7, and stores it in the layout information file 9.

Next, a specific example of the layout design of the circuit shown in FIG. 8 will be described. In FIG. 8, 11 is an inverter, 12 is a NAND gate, and 13 is a wiring, and outputs the NAND of the inverted signal of the input terminal e1 and f1 to the output terminal g1 and the NAND of the inverted signal of the input terminal e2 and f2. The NAND signal of the inverted signal of the input terminal e3 and f3 is output to the terminal g2, and the NAND signal of the inverted signal of the input terminal e4 and f4 is output to the output terminal g4. FIG. 10 shows the layout information 21 of the inverter for 4 bits and the layout information 23 of the wiring for 4 bits by the multi-bit parallel arranging unit 6.
And multi-bit circuit block information in which layout information 22 of 4-bit NAND gates is developed in parallel.

The layout and wiring design unit 8 layouts and wires the multi-bit circuit block information shown in FIG. 10, and generates layout information as shown in FIG. As apparent from the figure, since the layout information 21 and 23 of the inverter 11 and the wiring 13 are separately developed in parallel, the inverter 11 and the wiring 13
And the wiring area 15 must be added between the multi-bit circuit block information of the NAND gate 12.

[0011]

As described above, according to the conventional semiconductor integrated circuit designing device, the unit circuits such as the inverter and the NAND gate are arranged in parallel according to the number of processing bits for each unit circuit, and then the inter-block arrangement is performed. Since wiring is performed, when the layout areas of the unit circuits that are connected are different, when a block in which unit circuits having a small area are arranged in parallel and a block in which unit circuits having a large area are arranged in parallel are arranged adjacent to each other, a useless area occurs. .. In addition, when a plurality of unit circuits are connected to one unit circuit, since each unit circuit is arranged in parallel, one block of the plurality of unit circuits is arranged at a position far from the block of the unit circuit to be connected. Therefore, it is necessary to newly provide a wiring area for connecting both blocks. Therefore, in order to keep the layout area as small as possible and increase the integration degree of the semiconductor integrated circuit, it is necessary to manually change the layout, which complicates the layout design work and increases the design process. There was a problem to do.

The present invention has been made in order to solve such a problem, and an extra wiring area is required by deciding the connection relation of circuit elements and forming them into blocks and arranging them in parallel. It is an object of the present invention to provide a semiconductor integrated circuit design device which can design a layout having a high degree of integration.

[0013]

A semiconductor integrated circuit designing apparatus according to the present invention is configured when a layout design of a circuit having a structure in which a plurality of circuit blocks having the same connection relation of their constituent elements are connected in parallel is performed. Based on the connection relationship between elements and circuit blocks, combine the layout information of the constituent elements in a combination such that the constituent elements in the connection relationship are arranged close to each other, and then combine the layout information by the number corresponding to the number of circuit blocks connected in parallel. It is characterized in that layout information is arranged in parallel and divided into blocks.

[0014]

According to the semiconductor integrated circuit designing device of the present invention, the circuit structure is such that the constituent elements and the circuit block connecting a plurality of constituent elements are connected to each other, for example, an inverter is connected to one input terminal of the NAND gate. The circuit blocks are connected in parallel as 4 units, and based on this connection relationship, the constituent elements in the connection relationship are not arranged at distant positions, instead of being divided into blocks based on the connection relationship. After synthesizing the layout information of the constituent elements with, the synthesized layout information is arranged in blocks in parallel according to the number of parallel connections, and this is similarly divided into blocks of constituent elements in a connection relationship. The layout information of the circuit to be designed is generated by placing the block adjacent to the block.

[0015]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 11 is a block diagram showing the configuration of the semiconductor integrated circuit designing apparatus of the present invention, in which reference numeral 1 is an instruction parameter input from a terminal or the like to define the structure of the semiconductor integrated circuit to be layout-designed. The inter-adjacent-block connection interpreting unit 2 responds to the input instruction parameter 1 by
Connection information between blocks is given to each of a unit circuit synthesizing unit 4, a multi-bit parallel arranging unit 6 and a layout and wiring designing unit 8, which will be described later. The unit circuit block information file 3 stores, as unit circuit block information, layout information such as an inverter, a NAND gate, which is a circuit of a processing unit having the smallest arithmetic processing.

The unit circuit synthesis section 4 reads out the required unit circuit block information from the unit circuit block information file 3 in accordance with the connection information provided from the adjacent block connection interpretation section 2 and synthesizes new unit circuit block information. The combined unit circuit block information is stored in the combined circuit information file 5. The multi-bit parallel arranging unit 6 is stored in the unit circuit block information and the composite circuit information file 5 stored in the unit circuit block information file 3 according to the connection relation information provided from the adjacent block connection interpreting unit 2. The unit circuit block information after synthesis is arranged in parallel by the number corresponding to the parameter of the circuit whose structure is defined by the instruction parameter 1 to generate multi-bit circuit block information, and this multi-bit circuit block information is multi-bit. It is stored in the circuit block information file 7.

The layout and wiring design unit 8 reads out multi-bit circuit information from the multi-bit circuit block information file 7 according to the connection relation information provided from the inter-adjacent-block connection interpretation unit 2 to perform layout and wiring, and the semiconductor integrated circuit of the semiconductor integrated circuit. Layout information is generated, and this layout information is stored in the layout information file 9. The layout information stored in the layout information file 9 is subjected to, for example, graphic editing conversion processing or data conversion processing, and is output to a semiconductor integrated circuit manufacturing apparatus or the like. The semiconductor integrated circuit manufacturing apparatus manufactures a semiconductor integrated circuit by generating mask data from given data.

The operation of the layout design by the semiconductor integrated circuit designing apparatus having the above configuration will be described by taking the case of designing the layout of the circuit shown in FIG. 2 as an example. The inter-adjacent-block connection interpreting unit 2 uses the circuit shown in FIG. 2 in which two inverters 11 and one NAND gate 12 are connected.
It is interpreted as a circuit in which four unit circuit blocks as shown in (4) are arranged in parallel. The unit circuit synthesis section 4 includes an inverter 1
1, the layout information 21 and 22 of each NAND gate 12 is read from the unit circuit block information file 3 to perform placement and routing, and layout information of two inverters 11 and one
The layout information of the NAND gate 12 is combined to generate combined circuit information 101, which is the combined unit circuit block information as shown in FIG.

The multi-bit parallel arranging unit 6 reads the combined circuit information 101 generated by the unit circuit combining unit 4 from the combined circuit information file 5 and uses this combined circuit information 101 as information from the adjacent block connection interpreting unit 2. 4 units are expanded in parallel. Since the circuit of FIG. 2 does not need to expand the unit circuit blocks other than this, reading from the unit circuit block information file 3 is not performed. as a result,
Layout information as shown in FIG. 7 is generated, and this layout information is stored in the multi-bit circuit block information file 7.

The layout and wiring design unit 8 reads the layout information as shown in FIG. 7 from the multi-bit circuit block information file 7 and stores it in the layout information file 9 in accordance with the information from the adjacent block connection interpreting unit 2. Note that FIG.
When connecting the circuit shown in (1) to other circuit components,
The layout and wiring design unit 8 performs layout and wiring, and the instruction parameter 1
The layout information of the semiconductor integrated circuit defined by is stored in the layout information file 9.

Next, the case of generating the layout information of the circuit shown in FIG. 8 will be described. The inter-adjacent-block connection interpreting unit 2 interprets the unit circuit block in which one inverter 11 is connected to one input terminal of one NAND circuit 12 as a circuit in which four unit units are arranged in parallel. Same as above
Layout information as shown in 14 is generated. Compared with the layout information, which is the layout information of the same circuit generated by the conventional semiconductor integrated circuit design device shown in FIG. 9, the layout information of FIG. The degree of integration is higher than that.

Further, FIG. 15 shows the unit circuit block X with X
Two unit circuit blocks Y with a smaller layout area
3 is a conceptual diagram of layout information when Z and Z are connected. FIG. As is clear from the figure, since the synthetic circuit information is generated by synthesizing X, Y, and Z and then the synthetic circuit information is arranged in parallel according to the number of bits, it is not necessary to provide an unnecessary wiring area.

Further, in FIG. 16, the unit circuit block α is
FIG. 3 is a conceptual diagram of layout information when unit circuit blocks β and γ having different layout areas are connected. As is clear from the figure, α1, β1 and γ1
After the synthetic circuit information in which the unevenness of the layout is smoothed is generated by the combination of and the combination of α2, γ2, and β2, the synthetic circuit information is arranged in parallel according to the number of bits.
There are no wasted areas in the layout.

In this embodiment, the case where four units are expanded has been described, but the number of units arranged in parallel is not limited to this. The number of adjacent block circuits is
It is not limited to 2: 1 and 1: 2, but the front stage m and the next stage n
Any combination of (m and n are natural numbers) is possible.

[0025]

As described above, the semiconductor integrated circuit designing device of the present invention is a semiconductor including functional blocks such as an adder, an ALU, a shift register, and a multiplier in which a plurality of circuits having the same element configuration are arranged. In the design of an integrated circuit, after synthesizing a combination of unit circuits in consideration of the connection relationship of elements, a layout in which a required number of these unit circuits are arranged is generated, and an extra wiring area is not provided between the unit circuits. This eliminates the need for a step of manually correcting the layout in order to increase the degree of integration by removing a large wiring area, which simplifies the work of layout design and has an excellent effect of high design efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional semiconductor integrated circuit design device.

FIG. 2 is a circuit diagram showing a configuration of a circuit for layout design.

FIG. 3 is a layout diagram of a unit circuit block of an inverter.

FIG. 4 is a layout diagram of a unit block circuit of a NAND gate.

FIG. 5 is a layout diagram in which inverters are arranged in parallel.

FIG. 6 is a layout diagram in which NAND gates are arranged in parallel.

FIG. 7 is a conceptual diagram of multi-bit circuit block information.

FIG. 8 is a circuit diagram showing a configuration of a circuit for layout design.

FIG. 9 is a layout diagram generated by a conventional semiconductor integrated circuit design device.

FIG. 10 is a conceptual diagram of multi-bit circuit block information by a conventional semiconductor integrated circuit design device.

FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit design device of the present invention.

FIG. 12 is a circuit diagram corresponding to a unit circuit block having a connection relationship to be combined.

FIG. 13 is a layout diagram of the unit circuit block of FIG.

FIG. 14 is a layout diagram of the circuit shown in FIG.

FIG. 15 is a conceptual diagram of layout information generated by the semiconductor integrated circuit design device of the present invention.

FIG. 16 is a conceptual diagram of layout information generated by the semiconductor integrated circuit design device of the present invention.

[Explanation of Codes] 2 Inter-adjacent block connection interpretation unit 3 Unit circuit block information file 4 Unit circuit synthesis unit 5 Synthesis circuit information file 6 Multi-bit parallel placement unit 7 Multi-bit circuit block information file 8 Placement and wiring design unit 9 Layout information file

Claims (1)

Claim: What is claimed is: 1. A semiconductor integrated circuit design device for designing a layout of a circuit in which a plurality of circuit blocks, each having the same connection relation of its constituent elements, are connected in parallel. A means for interpreting the connection relationship between the constituent elements and the circuit block, a means for combining the layout information of the constituent element with a combination of the constituent elements according to the connection relationship interpreted by the means, and a layout combined by the means. A semiconductor integrated circuit designing device, comprising means for arranging information adjacent to each other in a number corresponding to the number of parallel connections to generate layout information of a circuit to be designed.