CN107038267B - Design method of basic unit of FPGA chip - Google Patents
Design method of basic unit of FPGA chip Download PDFInfo
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- CN107038267B CN107038267B CN201610080684.XA CN201610080684A CN107038267B CN 107038267 B CN107038267 B CN 107038267B CN 201610080684 A CN201610080684 A CN 201610080684A CN 107038267 B CN107038267 B CN 107038267B
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention relates to a design method of a basic unit of an FPGA chip, which comprises the following steps: acquiring a basic unit of an FPGA chip; acquiring time sequence constraint information of the input/output port of the basic unit, and finishing the internal physical design of the basic unit according to the time sequence constraint information; acquiring time sequence constraint information of a metal wire to be passed through in the basic unit, and finishing the metal wire wiring according to the time sequence constraint of the metal wire; simulating the wiring result of the metal wire; after the basic unit is determined to be a physically completely independent unit, generating a netlist of the FPGA chip; and producing a tape-out according to the netlist. The invention freely combines chips meeting different requirements and sizes and suitable for various processes through each physically independent basic unit; thereby shortening the production time of the chip, reducing the workload, quickening the time of the chip product on the market and further reducing the cost.
Description
Technical Field
The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to a design method of an FPGA chip basic unit.
Background
A Field Programmable Gate Array (FPGA) is a logic device with rich hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features have led to the widespread use of FPGAs in many areas such as data processing, communications, networking, etc.
The design flow of the FPGA is a process of developing an FPGA chip by using EDA development software and a programming tool. The typical FPGA development process generally includes main steps of function definition/device model selection, design input, function simulation, comprehensive optimization, simulation after synthesis, implementation, simulation after wiring, board-level simulation, chip programming and debugging, and the like.
The production process of the FPGA chip at present comprises the steps of firstly designing a circuit, and making an embedded storage module EMB (embedded storage), a digital sound processor module DSP (digital sound processor), a programmable Logic module PLB (programmable Logic Block), a programmable Logic module PLBR (programmable Logic Block Local memory) with a Local memory and an input/output module I/O (input output) into a complete circuit; then manually drawing the layout of each layer according to the hierarchical requirement, and then carrying out production. Such a production flow, a medium-scale chip, requires five people to complete in three months. For large FPGA chips, the method has no way to do so.
At present, the industry does not find a method for freely combining all basic modules to form an FPGA chip which meets different requirements and sizes and is suitable for various processes.
Disclosure of Invention
The invention aims to provide a design method of a basic unit of an FPGA chip, aiming at the defects of the prior art, the method can design the basic unit in the FPGA chip into a physically absolutely independent unit, so that each independent basic unit can be freely combined to form a chip which meets different requirements and sizes and is suitable for various processes.
The invention provides a design method of a basic unit of an FPGA chip, which comprises the following steps: acquiring a basic unit of an FPGA chip; acquiring time sequence constraint information of the input/output port of the basic unit, and finishing the internal physical design of the basic unit according to the time sequence constraint information; acquiring time sequence constraint information of a metal wire to be passed through in the basic unit, and finishing the metal wire wiring according to the time sequence constraint of the metal wire; simulating the wiring result of the metal wire; after the basic unit is determined to be a physically completely independent unit, generating a netlist of the FPGA chip; and producing a tape-out according to the netlist.
In the above method, the base unit comprises an embedded memory unit, a digital sound processor unit, an input-output unit, a programmable logic block unit, and a programmable logic block unit with a local memory; an auxiliary unit placed in a horizontal direction and an auxiliary unit placed in a vertical direction.
In the above method, the auxiliary units in the horizontal direction include an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input-output auxiliary unit, a programmable logic block auxiliary unit, and a programmable logic block auxiliary unit with a local memory; and the physical size of the auxiliary unit in the horizontal direction coincides with the size of the assisted basic unit.
In the above method, the auxiliary units placed in the vertical direction include a first auxiliary unit, a second auxiliary unit, and a third auxiliary unit; wherein the first auxiliary unit comprises an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input-output auxiliary unit, a programmable logic block auxiliary unit and a programmable logic block auxiliary unit with a local memory; the second auxiliary unit comprises one or more phase-locked loop auxiliary units; and the third auxiliary unit is used for core power-on initialization.
In the above method, the physically completely independent unit means that the input and output ports are distributed around the basic unit, and the connection lines of the basic unit are distributed inside the basic unit.
The invention freely combines chips meeting different requirements and sizes and suitable for various processes through each physically independent basic unit; thereby shortening the production time of the chip, reducing the workload, quickening the time of the chip product on the market and further reducing the cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for designing a basic unit of an FPGA chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of PLB and PLBR basic units in an FPGA chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an EMB or DSP basic unit in an FPGA chip according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an I/O basic unit in an FPGA chip according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an auxiliary unit disposed along a vertical direction in an FPGA chip according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an auxiliary unit disposed along a horizontal direction in an FPGA chip according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a chip with freely combined basic units according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
The invention provides a design method of a basic unit of an FPGA chip, which can design the basic unit in the FPGA chip into a physically absolutely independent unit, so that each independent basic unit can be freely combined to form a chip which meets different requirements and sizes and is suitable for various processes. That is, the method provided by the invention can be used for producing chips, so that one person can make several chips in one day, and the method is more suitable for batch production of large chips.
An embodiment of the present invention will be described below with reference to fig. 1 as an example. Fig. 1 is a schematic flow chart of a method for designing a basic unit of an FPGA chip according to an embodiment of the present invention. As shown, the method includes steps S101-S106:
step S101: acquiring a basic unit of an FPGA chip;
in the above method, the basic unit includes an embedded memory unit emb (embedded storage), a digital sound processor unit dsp (digital sound processor), an input-output unit I/o (input output), a programmable Logic Block unit plb (programmable Logic Block), and a programmable Logic Block unit plbr (programmable Logic Block Local memory) with a Local memory; a secondary unit Seam _ unit placed in the horizontal direction and a secondary unit Spine _ unit placed in the vertical direction.
It should be noted that, here, the FPGA chip is cut into a plurality of basic units according to the physical position and physical shape in the chip; different numbers of basic units are combined together to form an FPGA chip.
In the above method, the auxiliary units in the horizontal direction include an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input-output auxiliary unit, a programmable logic block auxiliary unit, and a programmable logic block auxiliary unit with a local memory; and the physical size of the auxiliary unit in the horizontal direction coincides with the size of the assisted basic unit.
In the above method, the auxiliary units placed in the vertical direction include a first auxiliary unit, a second auxiliary unit, and a third auxiliary unit; wherein the first auxiliary unit comprises an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input-output auxiliary unit, a programmable logic block auxiliary unit and a programmable logic block auxiliary unit with a local memory; the second auxiliary unit comprises one or more phase-locked loop auxiliary units; and the third auxiliary unit is used for core power-on initialization.
The auxiliary unit is also a management unit, and configures and resets the clock of the auxiliary basic unit, for example: the second auxiliary unit is used for assisting the phase-locked loop in the case that one or more phase-locked loops are needed in the chip.
Step S102: acquiring time sequence constraint information of the input/output port of the basic unit, and finishing the internal physical design of the basic unit according to the time sequence constraint information;
it should be noted that the input/output port of each basic unit has its own timing information and constraint requirement. For example: the input interface of each basic unit comprises information such as data reaching time, data delay, data rising time and data falling time, and related constraint requirements; each output interface also has information of output driving capability, output delay, data rising time, data falling time and the like, and related constraint requirements.
In this step, the internal physical design of the basic unit is completed according to the timing constraint information of the input/output port of each basic unit, and attention is paid to the constraint that the metal line level cannot exceed the metal layer number of the current layer.
Step S103: acquiring time sequence constraint information of a metal wire to be passed through in the basic unit, and finishing the metal wire wiring according to the time sequence constraint of the metal wire;
it should be noted that each of the basic cells is located in the interconnections of the upper, lower, left, right, and oblique wires of the chip, and these wires also have their own timing requirements and their own timing constraints.
In this step, the number of metal lines to be passed through in each basic unit, the number of layers, timing information, and constraint requirements need to be determined; the metal lines are routed in accordance with timing constraint information of the metal lines.
Step S104: simulating the wiring result of the metal wire;
it should be noted that, here, the timing simulation is performed on the wiring result of the metal wire; here, the wiring results of each basic cell are subjected to timing simulation.
The time sequence simulation comprises the most complete and accurate delay information and can better reflect the actual working condition of the chip. Because the internal delays of different chips are different, different wiring schemes also have different effects on the delays. Therefore, after wiring, it is necessary to perform timing simulation on each basic unit, analyze the timing relationship, estimate the system performance, and check and eliminate the risk of competition.
Step S105: after the basic unit is determined to be a physically completely independent unit, generating a netlist of the FPGA chip;
in the above method, the physically completely independent unit means that the input and output ports are distributed around the basic unit, and the connection lines of the basic unit are distributed inside the basic unit.
It should be noted that each of the physically completely independent basic units can realize the functions of each basic unit, for example: the EMB can realize single-port and double-port information storage, the DSP performs addition, subtraction, multiplication and division operation, the I/O completes the driving and matching requirements of the chip and an external circuit on input/output signals under different conditions, the PLB can have the functions of 8 lookup tables (LUTs), and the PLBR has the functions of the PLB, a 256Bit memory and a 16 multiplied by 1 shift register; further, the lines passing through the basic unit include lines associated with the basic unit and lines not associated with the basic unit.
In this step, a single-level chip netlist is generated, which includes the physically independent basic units, all the input/output ports of the basic units, and the connection information on the input/output ports of the basic units. The single level here means that the layout of each layer is drawn and then produced according to the layering standard without manual work; but the various basic units which are physically independent can be directly and freely combined according to the needs.
Step S106: and producing a tape-out according to the netlist.
It should be noted that tape-out refers to the fabrication of chips through a series of process steps as a flow line.
Next, the combination of chips is described by taking fig. 7 as an example, and fig. 7 is a schematic diagram of a chip with freely combined basic units according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a PLB and a PLBR, as shown in fig. 2, and fig. 2 is a schematic diagram of a PLB and a PLBR basic unit in an FPGA chip according to an embodiment of the present invention; as shown in fig. 3, fig. 3 is a schematic diagram of an EMB or DSP basic unit in an FPGA chip according to an embodiment of the present invention; by I/O, as shown in fig. 4, fig. 4 is a schematic diagram of an I/O basic unit in an FPGA chip according to an embodiment of the present invention; as shown in fig. 5, an auxiliary unit Spine _ unit is placed along the vertical direction, and fig. 5 is a schematic diagram of an auxiliary unit placed along the vertical direction in the FPGA chip according to the embodiment of the present invention; the FPGA chip is formed by combining auxiliary units Seam _ unit placed along the horizontal direction, as shown in fig. 6, fig. 6 is a schematic diagram of the auxiliary units placed along the horizontal direction in the FPGA chip according to the embodiment of the present invention.
It should be noted that, as shown in fig. 7, the size of the auxiliary unit placed in the horizontal direction matches the size of the assisted base unit in the horizontal direction; the auxiliary unit arranged along the vertical direction is suitable for being used commonly by all the auxiliary basic units; the physical length of the EMB or DSP in the vertical direction is 4 times the physical length of the I/O or PLB or PLBR in the vertical direction.
It should be further noted that fig. 2 is a schematic diagram of a PLB and a PLBR basic unit in an FPGA chip according to an embodiment of the present invention, where the PLB includes a logic unit le (logical element) and a routing resource, and the routing resource is further divided into a routing resource xbar inside the PLB and a routing resource oxbar leading to the outside of the PLB; and the winding resources of PLB and PLBR are the same, so they are not separately shown in the figure. The remaining basic units are similar to the PLB and will not be described again here.
The invention freely combines chips meeting different requirements and sizes and suitable for various processes through each physically independent basic unit; thereby shortening the production time of the chip, reducing the workload, quickening the time of the chip product on the market and further reducing the cost.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A design method of basic units of an FPGA chip is characterized by comprising the following steps:
the FPGA chip is divided into a plurality of basic units;
acquiring time sequence constraint information of input and output ports of each basic unit, and finishing internal physical design of each basic unit according to the time sequence constraint information;
acquiring time sequence constraint information of metal wires to be passed through in each basic unit, and finishing the metal wire wiring according to the time sequence constraint of the metal wires;
simulating the wiring result of the metal wire; performing timing simulation on the wiring result of each basic unit;
after determining that each basic unit is a physically completely independent unit, generating a single-level netlist of the FPGA chip according to the plurality of basic units; the physically completely independent unit means that input and output ports are distributed around a basic unit, and connecting lines of the basic unit are distributed inside the basic unit; the netlist comprises all basic units, all input and output ports of all the basic units and connection information on the input and output ports of all the basic units; the single-level netlist enables all basic units to be directly freely combined according to needs;
and producing a tape-out according to the netlist.
2. The method of claim 1, wherein the base unit comprises an embedded memory unit, a digital sound processor unit, an input output unit, a programmable logic block unit, and a programmable logic block unit with local memory; an auxiliary unit placed in a horizontal direction and an auxiliary unit placed in a vertical direction.
3. The method of claim 2, wherein the auxiliary units in the horizontal direction include an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input-output auxiliary unit, a programmable logic block auxiliary unit, and a programmable logic block auxiliary unit with local memory; and the physical size of the auxiliary unit in the horizontal direction coincides with the size of the assisted basic unit.
4. The method of claim 2, wherein the auxiliary units placed in the vertical direction include a first auxiliary unit, a second auxiliary unit, and a third auxiliary unit; wherein,
the first auxiliary unit comprises an embedded memory auxiliary unit, a digital sound processor auxiliary unit, an input and output auxiliary unit, a programmable logic block auxiliary unit and a programmable logic block auxiliary unit with a local memory;
the second auxiliary unit comprises one or more phase-locked loop auxiliary units;
and the third auxiliary unit is used for core power-on initialization.
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