CN107038267A - A kind of design method of fpga chip elementary cell - Google Patents
A kind of design method of fpga chip elementary cell Download PDFInfo
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- CN107038267A CN107038267A CN201610080684.XA CN201610080684A CN107038267A CN 107038267 A CN107038267 A CN 107038267A CN 201610080684 A CN201610080684 A CN 201610080684A CN 107038267 A CN107038267 A CN 107038267A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/04—Constraint-based CAD
Abstract
The present invention relates to a kind of design method of fpga chip elementary cell, this method includes：Obtain the elementary cell of fpga chip；The timing constraint information of the elementary cell input/output port is obtained, and the internal physical for completing the elementary cell according to the timing constraint information is designed；The timing constraint information for the metal wire to be passed through in the elementary cell is obtained, the metal line wire is completed according to the temporal constraint of the metal wire；Wiring result to the metal wire is emulated；The elementary cell is determined for after physically completely self-contained unit, and produces with this netlist of fpga chip；Flow is produced according to the netlist.The present invention goes out to meet different demands, size and is adapted to polytechnic chip by each physically independent elementary cell, independent assortment；And then shorten the production time of chip, workload is reduced, accelerates chip product Time To Market, and then reduce cost.
Description
Technical field
The present invention relates to the IC design technical field in microelectronic, particularly a kind of design method of fpga chip elementary cell.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA) is a kind of logical device for having and enriching hardware resource, powerful parallel processing capability and flexible reconfigurable ability.These features cause FPGA to obtain increasing extensive use in many fields such as data processing, communication, network.
FPGA design cycle is exactly to develop the process that software and programming tool are developed to fpga chip using EDA.Typical FPGA development process generally comprises function definition/parts selection, designs input, functional simulation, complex optimum, comprehensive post-simulation, realization, wiring post-simulation, the emulation of plate level and the key step such as chip programming and debugging.
The production procedure of current fpga chip is, circuit design is first done, embedded storage module EMB (Embedded storage), Digital Sound Processor module DSP (Digital sound field processor), programmed logical module PLB (Programmable Logic Block), the programmed logical module PLBR (Programmable Logic Block Local memory lram) with local storage and input/output module I/O (Input Output) are made into a complete circuit；Then the artificial requirement according to stratification, each layer of domain is finished, then goes production.Such production procedure, a medium scale chip are, it is necessary to which five people are gone to complete with the trimestral time.For large-scale fpga chip, have no way of doing it at all.
Current industrial quarters, which is not found also, to carry out independent assortment by each basic module, be combined into and met different demands, size and the method for being adapted to polytechnic fpga chip.
The content of the invention
The purpose of the present invention is the defect for prior art, there is provided a kind of design method of fpga chip elementary cell, elementary cell in fpga chip can be designed to physically definitely independent unit by this method so that each independent elementary cell can independent assortment go out to meet different demands, size and be adapted to polytechnic chip.
The present invention provides a kind of design method of fpga chip elementary cell, and this method includes：Obtain the elementary cell of fpga chip；The timing constraint information of the elementary cell input/output port is obtained, and the internal physical for completing the elementary cell according to the timing constraint information is designed；The timing constraint information for the metal wire to be passed through in the elementary cell is obtained, the metal line wire is completed according to the temporal constraint of the metal wire；Wiring result to the metal wire is emulated；The elementary cell is determined for after physically completely self-contained unit, and produces with this netlist of fpga chip；Flow is produced according to the netlist.
In the above-mentioned methods, elementary cell includes embedded memory cell, Digital Sound Processor unit, input-output unit, FPGA module unit and the FPGA module unit with local storage；The auxiliary unit placed in the horizontal direction and the auxiliary unit being placed in a perpendicular direction.
In the above-mentioned methods, auxiliary unit in the horizontal direction includes in-line memory auxiliary unit, Digital Sound Processor auxiliary unit, input and output auxiliary unit, programmable logic block auxiliary unit and the programmable logic block auxiliary unit with local storage；And the size of elementary cell of the physical size of auxiliary unit in the horizontal direction in the horizontal direction with being aided in is coincide.
In the above-mentioned methods, the auxiliary unit being placed in a perpendicular direction includes the first auxiliary unit, the second auxiliary unit and the 3rd auxiliary unit；Wherein, first auxiliary unit includes in-line memory auxiliary unit, Digital Sound Processor auxiliary unit, input and output auxiliary unit, programmable logic block auxiliary unit and the programmable logic block auxiliary unit with local storage；Second auxiliary unit includes one or more phaselocked loop auxiliary units；3rd auxiliary unit, for core power-up initializing.
In the above-mentioned methods, physically completely self-contained unit refers to that the surrounding of elementary cell is dispersed with input/output port, and the line of the elementary cell is distributed in the inside of the elementary cell.
The present invention goes out to meet different demands, size and is adapted to polytechnic chip by each physically independent elementary cell, independent assortment；And then shorten the production time of chip, workload is reduced, accelerates chip product Time To Market, and then reduce cost.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, the accompanying drawing used required in being described below to embodiment is briefly described, apparently, drawings in the following description are only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of design method schematic flow sheet of fpga chip elementary cell provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of PLB and PLBR elementary cells in fpga chip provided in an embodiment of the present invention；
Fig. 3 is the schematic diagram of EMB or DSP elementary cells in fpga chip provided in an embodiment of the present invention；
Fig. 4 is I/O elementary cell schematic diagrames in fpga chip provided in an embodiment of the present invention；
Fig. 5 is the auxiliary unit schematic diagram that is placed in a perpendicular direction in fpga chip provided in an embodiment of the present invention；
Fig. 6 is the auxiliary unit schematic diagram placed in the horizontal direction in fpga chip provided in an embodiment of the present invention；
Fig. 7 is a kind of chip schematic diagram of elementary cell independent assortment provided in an embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiments.
The invention provides a kind of design method of fpga chip elementary cell, elementary cell in fpga chip can be designed to physically definitely independent unit by this method so that each independent elementary cell can independent assortment go out to meet different demands, size and be adapted to polytechnic chip.That is, producing chip with method provided by the present invention, a people can do several chips within the time of one day, more suitable for the batch production of jumbo chip.
Below by taking Fig. 1 as an example, the embodiment of the present invention is illustrated.Fig. 1 is a kind of design method schematic flow sheet of fpga chip elementary cell provided in an embodiment of the present invention.As illustrated, the method comprising the steps of S101-S106：
Step S101：Obtain the elementary cell of fpga chip；
In the above-mentioned methods, elementary cell includes embedded memory cell EMB (Embedded storage), Digital Sound Processor cells D SP (Digital sound field processor), input-output unit I/O (Input Output), FPGA module unit PLB (Programmable Logic Block) and the FPGA module unit PLBR (Programmable Logic Block Local memory lram) with local storage；The auxiliary unit Seam_unit placed in the horizontal direction the and auxiliary unit Spine_unit being placed in a perpendicular direction.
It should be noted that being according to fpga chip is cut into multiple elementary cells by physical location, physical form in the chips herein；The elementary cell of varying number combines composition fpga chip.
In the above-mentioned methods, auxiliary unit in the horizontal direction includes in-line memory auxiliary unit, Digital Sound Processor auxiliary unit, input and output auxiliary unit, programmable logic block auxiliary unit and the programmable logic block auxiliary unit with local storage；And the size of elementary cell of the physical size of auxiliary unit in the horizontal direction in the horizontal direction with being aided in is coincide.
In the above-mentioned methods, the auxiliary unit being placed in a perpendicular direction includes the first auxiliary unit, the second auxiliary unit and the 3rd auxiliary unit；Wherein, first auxiliary unit includes in-line memory auxiliary unit, Digital Sound Processor auxiliary unit, input and output auxiliary unit, programmable logic block auxiliary unit and the programmable logic block auxiliary unit with local storage；Second auxiliary unit includes one or more phaselocked loop auxiliary units；3rd auxiliary unit, for core power-up initializing.
It should be noted that auxiliary unit is also administrative unit, the elementary cell aided in is configured and clock-reset, for example：Second auxiliary unit is that in the case of needing one or more phaselocked loops in the chips, phaselocked loop is aided in.
Step S102：The timing constraint information of the elementary cell input/output port is obtained, and the internal physical for completing the elementary cell according to the timing constraint information is designed；
It should be noted that the input/output port of each above-mentioned elementary cell has respective timing information and constraint requirements.For example：The input interface of each elementary cell, has data to reach the information such as time, data delay and data risings, fall time, and correlation constraint requirements；Each output interface, also has output driving ability, exports the information such as delay and data rising, fall time, and related constraint requirements.
In this step, according to the timing constraint information of each elementary cell input/output port, the internal physical design of elementary cell is completed, now it is noted that the constraint of the metal wire level no more than number of metal of current layer.
Step S103：The timing constraint information for the metal wire to be passed through in the elementary cell is obtained, the metal line wire is completed according to the temporal constraint of the metal wire；
It should be noted that each above-mentioned elementary cell, it is above and below chip, left and right and tiltedly among the interconnection of threading, these metal wires also have the timing requirements of oneself, also there is the temporal constraint of oneself.
In this step, it is thus necessary to determine that bar number, the number of plies, timing information and the constraint requirements for the metal wire to be passed through in each elementary cell；Metal wire is connected up according to the timing constraint information of metal wire.
Step S104：Wiring result to the metal wire is emulated；
It should be noted that being the wiring result progress time stimulatiom to metal wire here；Here it is the wiring result progress time stimulatiom to each elementary cell.
The delay information that time stimulatiom is included is most complete, also most accurate, can preferably reflect the real work situation of chip.Because the internal delay time of different chips is different, different cabling scenarios also bring different influences to delay.Therefore after wiring, by carrying out time stimulatiom to each elementary cell, its sequential relationship, estimating system performance, and inspection is analyzed and elimination race hazard is necessary.
Step S105：The elementary cell is determined for after physically completely self-contained unit, and produces with this netlist of fpga chip；
In the above-mentioned methods, physically completely self-contained unit refers to that the surrounding of elementary cell is dispersed with input/output port, and the line of the elementary cell is distributed in the inside of the elementary cell.
It should be noted that each physically completely self-contained elementary cell can realize the function of each elementary cell, for example：EMB can realize single, double port information storage, DSP carries out addition subtraction multiplication and division computing, I/O completes under different condition chip and external circuitry to the driving of input/output signal with matching requirement, PLB can have 8 look-up table LUT function, and the existing PLB of PLBR function also has the function of 256Bit memories and 16 × 16 × 1 shift register；Also, the line through this elementary cell includes and the related line of this elementary cell, also including the line with this elementary cell onrelevant.
In this step, generation be single level chip netlist, chip netlist includes the link information on above-mentioned physically independent each elementary cell, all input/output ports of each elementary cell and each elementary cell input/output port.Here single level refers to manually go the standard according to stratification again, goes to produce again after each layer of domain is finished；But physically independent each elementary cell, can independent assortment directly as needed.
Step S106：Flow is produced according to the netlist.
It should be noted that flow refers to manufacture chip by series of process step as streamline.
Below by taking Fig. 7 as an example, the combination to chip is illustrated, and Fig. 7 is a kind of chip schematic diagram of elementary cell independent assortment provided in an embodiment of the present invention.
Fig. 7 is by PLB, PLBR, as shown in Fig. 2 Fig. 2 is the schematic diagram of PLB and PLBR elementary cells in fpga chip provided in an embodiment of the present invention；By EMB or DSP, as shown in figure 3, Fig. 3 is the schematic diagram of EMB or DSP elementary cells in fpga chip provided in an embodiment of the present invention；By I/O, as shown in figure 4, Fig. 4 is I/O elementary cell schematic diagrames in fpga chip provided in an embodiment of the present invention；By the auxiliary unit Spine_unit being placed in a perpendicular direction, as shown in figure 5, Fig. 5 is the auxiliary unit schematic diagram being placed in a perpendicular direction in fpga chip provided in an embodiment of the present invention；Combined by the auxiliary unit Seam_unit placed in the horizontal direction, as shown in fig. 6, Fig. 6 is the auxiliary unit schematic diagram placed in the horizontal direction in fpga chip provided in an embodiment of the present invention.
It should be noted that as shown in fig. 7, the size for the auxiliary unit placed in the horizontal direction and the elementary cell that is aided in are coincide in size in the horizontal direction；It is general that the auxiliary unit being placed in a perpendicular direction is adapted to all elementary cells aided in；The physical length of EMB or DSP vertical direction is I/O or PLB or PLBR at 4 times of physical length of vertical direction.
What it is there is also the need to explanation is, Fig. 2 is the schematic diagram of PLB and PLBR elementary cells in fpga chip provided in an embodiment of the present invention, PLB includes logic unit LE (Logic element) and coiling resource, and coiling resource is divided into coiling resource xbar inside PLB and towards the coiling resource oxbar outside PLB again；And PLB is identical with PLBR coiling resource, therefore do not represented individually in figure.Remaining elementary cell is similar with PLB, repeats no more here.
The present invention goes out to meet different demands, size and is adapted to polytechnic chip by each physically independent elementary cell, independent assortment；And then shorten the production time of chip, workload is reduced, accelerates chip product Time To Market, and then reduce cost.
Professional should further appreciate that, the unit and algorithm steps of each example described with reference to the embodiments described herein, it can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate the interchangeability of hardware and software, the composition and step of each example are generally described according to function in the above description.These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel can realize described function to each specific application using distinct methods, but this realization is it is not considered that beyond the scope of this invention.
The step of method or algorithm for being described with reference to the embodiments described herein, can be implemented with hardware, the software module of computing device, or the combination of the two.Software module can be placed in any other form of storage medium known in random access memory (RAM), internal memory, read-only storage (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; the purpose of the present invention, technical scheme and beneficial effect are further described; it should be understood that; it the foregoing is only the embodiment of the present invention; the protection domain being not intended to limit the present invention; within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., should be included in the scope of the protection.
Claims (5)
1. a kind of design method of fpga chip elementary cell, it is characterised in that methods described includes：
Obtain the elementary cell of fpga chip；
The timing constraint information of the elementary cell input/output port is obtained, and institute is completed according to the timing constraint information
State the internal physical design of elementary cell；
The timing constraint information for the metal wire to be passed through in the elementary cell is obtained, according to the temporal constraint of the metal wire
Complete the metal line wire；
Wiring result to the metal wire is emulated；
The elementary cell is determined for after physically completely self-contained unit, and produces with this netlist of fpga chip；
Flow is produced according to the netlist.
2. according to the method described in claim 1, it is characterised in that the elementary cell include embedded memory cell,
Digital Sound Processor unit, input-output unit, FPGA module unit and the FPGA with local storage
Module unit；The auxiliary unit placed in the horizontal direction and the auxiliary unit being placed in a perpendicular direction.
3. method according to claim 2, it is characterised in that the auxiliary unit in the horizontal direction includes insertion
Formula memory auxiliary unit, Digital Sound Processor auxiliary unit, input and output auxiliary unit, programmable logic block auxiliary are single
Member and the programmable logic block auxiliary unit with local storage；And auxiliary unit in the horizontal direction is in the horizontal direction
The size of elementary cell of the physical size with being aided in is coincide.
4. method according to claim 2, it is characterised in that the auxiliary unit being placed in a perpendicular direction includes
First auxiliary unit, the second auxiliary unit and the 3rd auxiliary unit；Wherein,
First auxiliary unit is defeated including in-line memory auxiliary unit, Digital Sound Processor auxiliary unit, input
Go out auxiliary unit, programmable logic block auxiliary unit and the programmable logic block auxiliary unit with local storage；
Second auxiliary unit includes one or more phaselocked loop auxiliary units；
3rd auxiliary unit, for core power-up initializing.
5. according to the method described in claim 1, it is characterised in that the physically completely self-contained unit refers to substantially
The surrounding of unit is dispersed with input/output port, and the line of the elementary cell is distributed in the inside of the elementary cell.
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