JPH03175654A - Standard cell type integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate reduction of the area of all wiring regions and obtain a high density integrated circuit by a method wherein one or a plurality of wiring channel regions are provided in a standard cell. CONSTITUTION:In a standard cell type integrated circuit, arrangements and wirings are provided by using standard cells 1. One or a plurality of wiring channel regions are provided in the standard cell 1. For instance, if one wiring channel region is provided in the standard cell 1, the one wiring channel region 2a in the standard cell 1 is provided in the P-N isolation region of a CMOS and a channel electrode contact 10 and a channel via-hole 11 are provided in the region. With this constitution, the area of the wiring channel part can be reduced compared with the area of a conventional constitution, so that a high density integrated circuit can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to standard cell type integrated circuits, and more particularly to a wiring structure between standard cells.

[Conventional technology]

Conventionally, many integrated circuits using standard cells have been designed and manufactured. When using standard cells, cells are selected from a group of cells registered in a cell library according to circuit connection information, and placed and wired. CA D (C
When using an automatic layout tool that makes full use of ``Aided Design'' technology, the above-mentioned standard cell type integrated circuit can be designed in a short delivery time and with extremely high reliability.

FIG. 4 shows an example of the arrangement and wiring diagram of a standard cell according to the conventional standard cell system. In this example, the standard cell 1 is placed and wired using the second layer of metal wiring. Here, 5
6 indicates a via hole for input, and 6 indicates an output node for output.

Further, an example of the standard cell 1 is shown in the layout diagram of FIG.

Figure 5 shows a CMO 32 hand-powered NAND circuit, with the gate electrode 7 and the second layer metal wiring for both input and output.
Connection is made with metal layer 4. Further, the wiring within the standard cell 1 is performed in the first metal layer 3, which is the first layer of metal wiring. Here, 8 indicates a gate electrode contact, and 9 indicates a diffusion layer contact. As is clear from the specifications of the standard cells in FIG. 5, the mutual connections between the standard cells were performed outside the cells (in the area of the wiring channel 2) as shown in 4'U4.

[Problem to be solved by the invention]

In the conventional 5-quasi-cell integrated circuit described above, interconnection between standard cells was performed outside the cell, so connections between adjacent cells must also be made in the wiring channel region (outside the cell), and therefore the wiring channel This has the drawback of increasing the area and reducing the degree of integration.

[Means to solve the problem]

The standard cell type integrated circuit of the present invention has a structure in which one or more wiring channel regions are provided even inside the standard cell.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout/wiring diagram showing a first embodiment of cell connection using standard cells of the present invention. In this embodiment, the present invention is applied to the connection example according to the prior art shown in FIG.

In this embodiment, the wiring channel region inside the standard cell 1 is for one line. An example of a standard cell in this case is shown in the layout diagram of FIG. One wiring channel 2a region in the standard cell is provided in the PN isolation region of the CMO3. Here, 10 indicates a channel electrode contact, and 11 indicates a channel via hole. According to this embodiment, the wiring channel portion can be made smaller than the conventional example.

FIG. 3 is a layout diagram showing a second embodiment of the present invention of a standard cell in which the number of wiring channels is further increased. In this embodiment, two wiring channels 2b and 2c (which can be used for both input and output) and two wiring channels 2d which can only be used for output are provided.The standard cell shown in FIG. By applying this technology, it is possible to more effectively form high-performance and large numbers of wiring channels.

〔Effect of the invention〕

As explained above, the present invention makes it possible to reduce the overall wiring area by providing a wiring channel inside a standard cell, and to provide a high-density integrated circuit2. Although a two-layer wiring has been described, a wiring structure with three or more layers or a 2.5-layer wiring structure (using a gate electrode layer only for input) has similar effects.

Furthermore, when the standard cell group of the present invention is applied to automatic layout, a high-density integrated circuit that is comparable to manual layout is provided, unlike in the past, and the features of the present invention are utilized.

[Brief explanation of drawings]

FIG. 1 is a layout/wiring diagram of a standard cell according to Embodiment 1 of the present invention;
Figure 2 is a 14791 diagram of the standard cell used in Example 1;
FIG. 3 is a layout diagram of a standard cell according to Embodiment 2 of the present invention;
FIG. 4 is a layout and wiring diagram of a conventional standard cell, and a layout diagram of a fifth comparable conventional standard cell. 1...Standard cell, 2.2a, 2b, 2c, 2d...
Wiring channel, 3... First metal layer, 4... Second metal layer, 5... Via hole, 6... Output node, 7...
...Gate electrode, 8...Gate electrode contact, 9.
... Diffusion layer contact, 10... Channel electrode contact, 11... Channel via hole.

Claims (1)

[Claims] A standard cell type integrated circuit in which placement and wiring are performed using standard cells, characterized in that a wiring channel region for one or more lines is provided inside the standard cell.