JPH02250319A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02250319A JPH02250319A JP7353389A JP7353389A JPH02250319A JP H02250319 A JPH02250319 A JP H02250319A JP 7353389 A JP7353389 A JP 7353389A JP 7353389 A JP7353389 A JP 7353389A JP H02250319 A JPH02250319 A JP H02250319A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten silicide
- tungsten
- ions
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052721 tungsten Inorganic materials 0.000 abstract description 15
- 239000010937 tungsten Substances 0.000 abstract description 15
- 239000010410 layer Substances 0.000 abstract description 14
- 230000003647 oxidation Effects 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 238000002425 crystallisation Methods 0.000 abstract description 3
- 230000008025 crystallization Effects 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 3
- 238000004299 exfoliation Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多結晶シリコン膜とタングステンシリサイド
膜の積Ｎ構造（以下、タングステンポリサイド膜と略す
）を、後工程での高湯熱処理に対し、安定な状態に維持
するための半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a structure in which a product N structure of a polycrystalline silicon film and a tungsten silicide film (hereinafter abbreviated as tungsten polycide film) can be made stable against high-temperature heat treatment in a subsequent process. The present invention relates to a method of manufacturing a semiconductor device for maintaining the same state.
従来の技術
近年、半導体産業の急速な発畏に伴い、半導体デバイス
に対し、高速化の要求が高まりつつある。BACKGROUND OF THE INVENTION In recent years, with the rapid development of the semiconductor industry, there has been an increasing demand for higher speeds for semiconductor devices.
半導体デバイスにおいて高速化に対応する鏝も効果的な
手段は、従来よりゲート電極や配線材料として用いられ
てきた多結晶シリコン嗅に代えて、抵抗値の低い高融点
金属を使用することである。An effective way to increase the speed of semiconductor devices is to use a high-melting point metal with low resistance in place of polycrystalline silicon, which has traditionally been used as gate electrode and wiring material.
この金属として、タングステンシリサイドが最も広く使
用されている。しかし、タングステンシリサイド膜自身
は、下地のゲート酸化寝（二酸化シリコン膜）との密着
性が悪いため、多結晶シリコン嘆と重ねる構造が主流と
なっている。Tungsten silicide is most widely used as this metal. However, the tungsten silicide film itself has poor adhesion to the underlying gate oxide film (silicon dioxide film), so a structure in which it overlaps with polycrystalline silicon film has become mainstream.
従来の半導体装置の製造方法では、ゲート′ｌｔ層およ
び配線としてタングステンポリサイド膜ヲ形成した後、
通常のリングラフィ技術によりバｙ −ユングし、その
後イオン注入技術を用いたセルファツインゲート方式で
ソースおよびドレイン領域を形成し、イオン注入後アニ
ー／Ｌ’を行い、さらに層間絶縁膜の下地となる熱酸化
膿（前酸化膜）形成のために９００℃以上の熱工程を行
っている。In the conventional semiconductor device manufacturing method, after forming a tungsten polycide film as a gate layer and wiring,
By-young is performed using normal phosphorography technology, then the source and drain regions are formed using a self-twin gate method using ion implantation technology, annealing/L' is performed after ion implantation, and the base layer is further formed into an interlayer insulating film. A thermal process of 900° C. or higher is performed to form thermally oxidized pus (pre-oxidized film).
発明が解決しようとする課題
しかし従来の半導体装置の製造方法では、上記熱工程に
よる熱処理直購、タングステンシリサイド膜に剥れが発
生するという問題があった。特に、タングステンシリサ
イド膜形成後、２回以上に分割して熱工程を行うと、確
実にタングステンシリサイド膜に剥れが発生してい友。Problems to be Solved by the Invention However, in the conventional method of manufacturing a semiconductor device, there is a problem in that the tungsten silicide film is peeled off due to direct heat treatment in the above-mentioned thermal process. In particular, if the thermal process is performed in two or more parts after forming the tungsten silicide film, the tungsten silicide film will definitely peel off.
タングステンポリサイド膜形成後の熱工程でタングステ
ンシリサイド膜に剥れが発生する原因は次の２点が考え
られる。The following two reasons can be considered for the occurrence of peeling of the tungsten silicide film during the thermal process after the formation of the tungsten polycide film.
（１）熱工程を経ると、タングステンシリサイドの結晶
化が進み結晶粒径が非常に大きくなる。この現象により
、タングステンシリサイド膜のストレスが増大し、下地
の多結晶シリコン膜との密着性が悪化する。(1) After the thermal process, tungsten silicide crystallizes and the crystal grain size becomes extremely large. This phenomenon increases the stress on the tungsten silicide film and deteriorates its adhesion to the underlying polycrystalline silicon film.
（２）熱工程が酸化の場合は、炉雰囲気中の０！が、ま
た熱工程がアニー〜の場合には、ウェハーの炉内への導
入時に巻き込む虜が、それぞれタングステンシリサイド
層に入り込み、タングテンの酸化を引き起こし、ＷＯ２
−’Ａ’０３を形成する０タングステンの酸化は、膜組
成を変え、多結晶シリコンとの密着性を悪化させ、また
ＷＯ，が昇華性であることから、内部からの膜破壊を生
じる可能性も高い。(2) If the thermal process is oxidation, 0! However, if the thermal process is annealing, the particles that get caught up when the wafer is introduced into the furnace enter the tungsten silicide layer, causing tungsten oxidation and WO2
- Oxidation of 0 tungsten that forms 'A'03 changes the film composition and worsens the adhesion with polycrystalline silicon, and since WO, is sublimable, there is a possibility of internal film destruction. It's also expensive.
本発明は上記間Ｕｔ全解決るものであシ、タングステン
ポリサイド膜形成後の高温熱処理に対し、タングステン
ポリサイド膜を安定な状態に維持可能な半導体装置の製
造方法を提供することを目的とするものである。The present invention solves all of the above problems, and aims to provide a method for manufacturing a semiconductor device that can maintain a tungsten polycide film in a stable state during high-temperature heat treatment after forming a tungsten polycide film. It is something to do.
課題全解決するための手段
上記問題を解決するため本発明の半導体装置の製造方法
は、半導体基板上に、電界効果トランジスタのゲート電
極、もしくは配線として使用される多結晶シリコン膜と
タングステンシリサイド膜を順に積層し、その後前記タ
ングステンシリサイド膜に、Ｎ＋イオンを注入する工程
を備えたものである。Means for Solving All Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes forming a polycrystalline silicon film and a tungsten silicide film, which are used as a gate electrode or wiring of a field effect transistor, on a semiconductor substrate. The method includes a step of sequentially stacking layers and then implanting N+ ions into the tungsten silicide film.
作用
上記製造方法により、タングステンポリサイド膜形成後
にＮ＋イオン注入することによって、以下の作用が発生
する。Effects By using the above manufacturing method and implanting N+ ions after forming the tungsten polycide film, the following effects occur.
（１）Ｎ＋イオン注入を行うことにより、タングステン
シリサイド層のアモハ／ファス化が促進され、これによ
り熱工程時の急激な結晶化が抑制され、粒径が小さくな
る。よって、タングステンシリサイド層のストレス増大
が抑えられ、下地の多結晶シリコン膜との密着性が維持
される。(1) By performing the N+ ion implantation, the tungsten silicide layer is promoted to become amorphous/fast, thereby suppressing rapid crystallization during a thermal process and reducing the grain size. Therefore, stress increase in the tungsten silicide layer is suppressed, and adhesion to the underlying polycrystalline silicon film is maintained.
（２）Ｎ＋イオンを注入することによシ、タングステン
シリサイド膜の表面層が窒化され、タングステンの酸化
が抑制され、ｗｏ、 、 ｗｏ、の形成が防止される。(2) By implanting N+ ions, the surface layer of the tungsten silicide film is nitrided, oxidation of tungsten is suppressed, and the formation of wo, , wo, is prevented.
以上の２点の作用により、熱工程処理後のタングステン
シリサイド膜の−ｊれが防止される。The above two effects prevent the tungsten silicide film from deforming after the thermal process.
実施例 以下、本発明の一実施例を図面に基づいて説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図ｆａ）〜（ｆｌは本発明の一実施例として半導体
装置の製造工程を順に示す半導体装置の断面図である。FIGS. 1fa) to 1(fl) are cross-sectional views of a semiconductor device sequentially showing the manufacturing process of the semiconductor device as an embodiment of the present invention.
まず、第１図（ａｌに示すように、Ｐ型半導体基板ｌの
表面に通常のＬＯＣＯ５法による分喝頭域２に囲まれた
トランジスタ領域３を形成する。First, as shown in FIG. 1 (al), a transistor region 3 surrounded by a dividing region 2 is formed on the surface of a P-type semiconductor substrate 1 by the usual LOCO5 method.
次に第１図（ｂ）に示すように、熱酸化法により分！１
１１領域２およびトランジスタ領域３の上にゲート酸化
膜４を厚さ約５０ＯＡ形成し、さらにこのゲート酸化膜
４の上に多結晶シリコン膜５を厚さ約２００ＯＡ形成す
る。その後、高濃度のリンドープを行い、表面に形成さ
れたリンガラス層をエッチンクシタ後、ＷＦ６とＳｉＨ
４’！ｋ ３７０ ’Ｃ〜４００ ’Ｃ’ｔ”反応させ
、タングステンシリサイド（ＷＳｉｘ） 幌６ （Ｘ＝
２．４程度）を厚さ約２５０ＯＡ形成する。そして、タ
ングステンシリサイド膜６の形成後、表面よりＮ＋イオ
ンを加速エネルギー４０ＫｅＶ、注入１４Ｘ１０−の条
件で注入する。Next, as shown in FIG. 1(b), a thermal oxidation method is used to separate the particles. 1
A gate oxide film 4 is formed to a thickness of about 50 OA on the 11 region 2 and the transistor region 3, and a polycrystalline silicon film 5 is further formed on the gate oxide film 4 to a thickness of about 200 OA. After that, high-concentration phosphorus doping is performed, and after etching the phosphorus glass layer formed on the surface, WF6 and SiH
4'! k 370 'C~400 'C't'' React, tungsten silicide (WSix) hood 6 (X=
2.4) to a thickness of approximately 250 OA. After forming the tungsten silicide film 6, N+ ions are implanted from the surface under conditions of acceleration energy of 40 KeV and implantation of 14×10−.
イオン注入後表面洗浄を行い、第１図（ｃｌに示すよう
に、フォトリソグラフィー法およびエツチング？Ｊｆ用
い、タングステンシリサイド層６、多結晶シリコン層５
さらにゲート酸化膜４からなる配線またはゲート領域を
形成する。After ion implantation, the surface is cleaned, and as shown in FIG.
Further, wiring or gate regions made of gate oxide film 4 are formed.
その後第１図（ｄｌに示すように、セルファライン技術
によりソースおよびドレイン領域７を形成すへ＜、Ａｓ
イオンを加速エネルギー４０ＫｅＶ、注入量５×１
０σ の条件で注入する。そしてイオン注人によるダメ
ージ緩和とソース・ドレイン頭載７の注入イオンの活性
化のため９００℃窒素雰囲気中で３０分間アニールを行
う。Thereafter, as shown in FIG.
Ion acceleration energy 40KeV, implantation amount 5×1
Inject under 0σ conditions. Then, annealing is performed for 30 minutes at 900° C. in a nitrogen atmosphere to alleviate damage caused by the ion implanter and to activate the implanted ions in the source/drain head 7.
続いて、第１図ｔｅｌに示すように、層間絶縁膜形成前
の半導体基板１のトランジスタ領域３の上に熱酸化膜８
を形成するため、１０００℃酸素雰囲気中で５分間酸化
を行う。Subsequently, as shown in FIG. 1, a thermal oxide film 8 is formed on the transistor region 3 of the semiconductor substrate 1 before the interlayer insulating film is formed.
To form , oxidation is performed at 1000° C. in an oxygen atmosphere for 5 minutes.
最後に、第１図ｆｆｌに示すように、ＣＶＤ法によりを
層間絶縁膜９Ａ約１μｍ成長させ、コンタクト頭載１０
を形成し、アルミニウムによる配線１１を約１μｍ形成
し、表面保護膜１２を約１．２μｍ形成してデバイスを
形成する。Finally, as shown in FIG.
A wiring 11 made of aluminum is formed to a thickness of about 1 μm, and a surface protection film 12 is formed to a thickness of about 1.2 μm to form a device.
このように上記製造方法によれば、Ｎ 注入を行うこと
により、タングステンシリサイド膜６は、表面層が窒化
され、アモルファス化が促進され、よってタングステン
の酸化が抑制され、ｗｏ、 、ｗｏ。As described above, according to the above manufacturing method, by performing N2 implantation, the surface layer of the tungsten silicide film 6 is nitrided, and its amorphous state is promoted, thereby suppressing the oxidation of tungsten.
の形成が防止され、かつ熱工程時の急激な結晶が抑制さ
れて粒径が小さくなり、タングステンシリサイドのスト
レス増大が抑えられ、多結晶シリコン膜５との密着性が
維持される。したがってタングステンポリサイド膜は、
熱処理後もデポジション時の積層状態を維持でき、Ｎ＋
イオン注入を実施しない場合に発生する異常酸化や膜剥
れ現象を防止することができる。The formation of tungsten silicide is prevented, rapid crystallization during the thermal process is suppressed, the grain size is reduced, stress increase in the tungsten silicide is suppressed, and adhesion with the polycrystalline silicon film 5 is maintained. Therefore, the tungsten polycide film is
Even after heat treatment, the laminated state at the time of deposition can be maintained, and N+
Abnormal oxidation and film peeling phenomena that occur when ion implantation is not performed can be prevented.
なお、本実施例では、Ｐ型半導体基板１を使用し、第１
層目のゲート電極および配線にタングステンポリサイド
層を使用した場合について述べたが、使用半導体基板の
型、方位、トランジスタの種類、また何層目の電極また
は配線に使用するかには無関係に適用できることは言う
までもない。Note that in this embodiment, a P-type semiconductor substrate 1 is used, and the first
Although we have described the case where a tungsten polycide layer is used for the gate electrode and wiring of each layer, it is applicable regardless of the type and orientation of the semiconductor substrate used, the type of transistor, or which layer of the electrode or wiring it is used for. It goes without saying that it can be done.
発明の効果
以上のように本発明によれば、タングステンポリサイド
層形成後Ｎ イオン注入を行うことにより、熱工程を経
ても、タングステンシリサイド膜の異常酸化による組成
変化、膜剥れｔ防止でき、タングステンポリサイド構造
のゲート４極および配ｍｔ−安定して形成することがで
きる。Effects of the Invention As described above, according to the present invention, by performing N ion implantation after forming a tungsten polycide layer, composition change and film peeling due to abnormal oxidation of the tungsten silicide film can be prevented even after a thermal process. The gate quadrupole and mt arrangement of the tungsten polycide structure can be stably formed.
第１図（ａｌ〜ｌｆ）は本発明の一実施例として半導体
装置の製造工程を順に示す半導体装置の断面図である。
１・・・半導体基板、２・・・ＬＯＣＯ３分４頭域、３
頭載・トランジスタ形成明域、４・・・ゲート酸化嘆、
５・・・多結晶ポリシリコン襖、６・・・タングステン
シリサイド膜、７・・・ソース・ドレイン明域、８・・
・熱酸化膜、９・・・層間絶縁膜、１０・・・コンタク
ト鎖酸、１１・・・７Ｎミニウム膜、１２・・・表面Ｓ
；Ｓａ。
第１図（ｆの１）
代理人 森 木 義 弘FIGS. 1A to 1F are cross-sectional views of a semiconductor device sequentially showing the manufacturing process of the semiconductor device as an embodiment of the present invention. 1... Semiconductor substrate, 2... LOCO 3/4 head area, 3
Overhead/transistor formation bright area, 4... Gate oxidation,
5... Polycrystalline polysilicon sliding door, 6... Tungsten silicide film, 7... Source/drain bright area, 8...
・Thermal oxide film, 9... Interlayer insulating film, 10... Contact chain acid, 11... 7N aluminum film, 12... Surface S
;Sa. Figure 1 (f-1) Agent Yoshihiro Moriki
Claims (1)
極、もしくは配線として使用される多結晶シリコン膜と
タングステンシリサイド膜を順に積層し、その後前記タ
ングステンシリサイド膜に、Ｎ＾＋イオンを注入する工
程を備えた半導体装置の製造方法。1. A step of sequentially laminating a polycrystalline silicon film and a tungsten silicide film, which are used as a gate electrode or wiring of a field effect transistor, on a semiconductor substrate, and then implanting N^+ ions into the tungsten silicide film. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7353389A JPH02250319A (en) | 1989-03-23 | 1989-03-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7353389A JPH02250319A (en) | 1989-03-23 | 1989-03-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02250319A true JPH02250319A (en) | 1990-10-08 |
Family
ID=13520965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7353389A Pending JPH02250319A (en) | 1989-03-23 | 1989-03-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02250319A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159848A (en) * | 1999-02-02 | 2000-12-12 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device having a high melting point metal film |
-
1989
- 1989-03-23 JP JP7353389A patent/JPH02250319A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159848A (en) * | 1999-02-02 | 2000-12-12 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device having a high melting point metal film |
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