JP2004087877A - Field effect semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate electrode having a high melting metal structure of Si/WSi/WN, low in contact resistance and high in thermal stability. <P>SOLUTION: In the manufacturing of this field effect semiconductor device, it is so set that a mathematical expression d<SB>WSi</SB>≤(1.25d<SB>WN</SB>)<SP>1/2</SP>be satisfied, wherein d<SB>WSi</SB>[nm] is the thickness of a WSi layer 6 which is a constituent of a gate electrode 4 having a high melting metal structure of Si/WSi/WN and d<SB>WN</SB>[nm] is the thickness of a WN layer 7 which is another constituent located farther from a gate insulating film 2 than the WSi layer 6 is. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field-effect semiconductor device and a method for manufacturing the same, and more particularly, to a correlation between the layer thicknesses of WSi and WN in a polymetal (POLY-METAL) structure gate electrode having a polycrystalline Si / WSi / WN / W structure. And a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in a silicon semiconductor device, miniaturization and high-speed operation of an element have been demanded. To meet the demand, a resistance of a gate electrode has been reduced. One of them is a polymetal made of polycrystalline Si / WN / W. Since a DRAM (Dynamic Random Access Memory) using an FET having a gate electrode having a structure has been proposed, a conventional polymetal gate FET will be described with reference to FIG.
[0003]
Referring to FIG. 4A, first, after forming an element isolation insulating film 32 of a p-type silicon substrate 31, an n-type well region 33 is formed, and then, a gate insulating film 34 is formed. Is deposited, and B ions are implanted to form a B-doped amorphous silicon layer.
[0004]
Next, a WN layer 36 having a thickness of, for example, 5 nm, a W layer 37 having a thickness of, for example, 40 nm, and a SiN film 38 having a thickness of, for example, 200 nm are sequentially deposited and then patterned. Then, a gate electrode 39 is formed.
The B-doped amorphous layer is crystallized in the deposition step of the SiN film 38 or the annealing step after the above-described ion implantation, and is converted into the B-doped polycrystalline silicon layer 35 to form a polymetal gate structure.
[0005]
Referring to FIG. 4B, after B ions are implanted, a p-type source / drain region 40 is formed by performing an annealing process for activation.
[0006]
Since W is used in this polymetal gate structure, the sheet resistance can be much lower than that of a conventional polycrystalline Si electrode or a polycrystalline Si / WSi electrode electrode. And speeding up are realized.
[0007]
[Problems to be solved by the invention]
However, in the above-mentioned polymetal gate electrode, B is doped as a dopant into the polycrystalline silicon layer. Therefore, at the interface between the B-doped polycrystalline silicon layer 35 and the WN layer 36, B (boron) and N (nitrogen) Combine to form BN.
[0008]
This BN bond is chemically stable, rarely reacts with other elements once formed, and is electrically inactive, so that B doped as an impurity is inactivated. As a result, there is a problem that the resistance at the interface between the B-doped polycrystalline silicon layer 35 and the WN layer 36 greatly increases.
[0009]
Therefore, in order to reduce the contact resistance at such an interface, it is conceivable to insert WSi into a polycrystalline Si / WSi / WN / W structure. However, it is difficult to secure heat resistance with this structure. There is a problem that Si reacts with Si.
[0010]
That is, the WN layer 36 reacts with Si forming the B-doped polycrystalline silicon layer 35 to form WSiN, and the Si—N bond forming the WSiN acts as a barrier against further diffusion of Si. When the WN layer 36 is interposed for suppressing the formation of the N bond, there is a problem that the heat resistance is reduced because WSiN is hardly formed.
[0011]
Accordingly, an object of the present invention is to provide a gate electrode having a low contact resistance and a thermally stable Si / WSi / WN / high melting point metal structure.
[0012]
[Means for Solving the Problems]
FIG. 1 is a diagram showing the basic configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
Reference numeral 3 in the figure is a source / drain region.
Referring to FIG. 1, in order to achieve the above object, the present invention provides a field effect type semiconductor comprising at least a Si-based semiconductor 1 having a gate electrode 4 having a Si / WSi / WN / high melting point metal structure from the gate insulating film 2 side. In the semiconductor device, when the thickness of the WSi layer 6 is d _WSi [nm] and the thickness of the WN layer 7 is d _WN [nm],
d _WSi ≦ (1.25d _WN ) ^1/2
Is satisfied.
[0013]
As described above, the relationship between the layer thickness d _WSi [nm] of the WSi layer 6 and the layer thickness d _WN [nm] of the WN layer 7 is as follows.
d _WSi ≦ (1.25d _WN ) ^1/2
By doing so, the diffusion of Si constituting the Si layer 5 into the high melting point metal layer 8 can be effectively suppressed at the heat treatment temperature such as the activation step of the implanted impurity. The semiconductor 1 containing at least Si as a main component is typically Si, and includes a semiconductor such as SiGe.
[0014]
In this case, the person WSi layer 6 is thin is good heat resistance, because in order to suppress the formation of B-N bond is required a certain degree of thickness, the layer thickness d _WSi the WSi layer 6, It is desirable that the thickness be 2.5 nm to 5 nm.
[0015]
In the gate electrode 4 having the Si layer 5 / WSi / WN / high melting point metal structure, at a normal heat treatment temperature, at least a part of the WN layer 7 is converted to WSiN.
[0016]
Further, as the high melting point metal in the gate electrode 4 having the Si layer 5 / WSi / WN / high melting point metal structure, any of W, Ti, Ta, Mo, Nb, TiN, TaN, and NbN is preferable.
[0017]
When a Si / WSi / WN / high melting point metal structure is sequentially deposited from the gate insulating film 2 side, the layer thickness ratio of the layer thickness d _WSi of the WSi layer 6 to the layer thickness d _WN of the WN layer 7 is determined by the gate electrode. The ratio is set so that the Si constituting the Si layer 5 does not effectively diffuse into the refractory metal layer 8 at the maximum use temperature used in the process after the formation of the metal layer 4.
[0018]
As described above, the layer thickness ratio between the layer thickness d _WSi of the WSi layer 6 and the layer thickness d _WN of the WN layer 7 is determined by adjusting the layer thickness ratio of the Si layer 5 at the maximum operating temperature used in the process after the formation of the gate electrode 4. Is set to a ratio that does not effectively diffuse into the high melting point metal layer 8, the generation of BN bonds can be suppressed while maintaining the heat resistance, so that the gate electrode 4 having a polymetal structure has a low resistance. Becomes possible.
In this case, effectively suppressing the diffusion means that the change in the specific resistance of the refractory metal layer 8 after the heat treatment is within the range of the measurement error.
[0019]
Also, the layer thickness d _WSi [nm] of the WSi layer 6 and the layer thickness d _WN [nm] of the WN layer 7 are
d _WSi ≦ (1.25d _WN ) ^1/2
By satisfying the relationship, it is possible to guarantee a process of 950 ° C. which is a normal heat treatment temperature in the activation step of the implanted impurities.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, a polymetal gate FET according to an embodiment of the present invention will be described with reference to FIGS.
Referring to FIG. 2A, first, an element isolation insulating film 12 is formed on a p-type silicon substrate 11, an n-type well region 13 is formed, and then the surface of the n-type Then, for example, a gate oxide film 14 of 3.5 nm is formed.
In this case, for example, oxidation is performed in a 750 ° C. steam atmosphere generated by flowing and burning H ₂ gas and O ₂ gas at a flow ratio of 1: 1.
[0021]
Next, after depositing an amorphous silicon film having a thickness of, for example, 70 nm on the entire surface by using the CVD method, for example, B is doped at a dose of 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ^−2. It is implanted to form a B-doped amorphous silicon layer 15.
The acceleration energy at this time is, eg, 3 to 5 keV so that B ions do not penetrate the amorphous silicon layer.
[0022]
Referring to FIG. 2B, a WSi layer 16, a WN layer 17, and a W layer 18 each having a thickness of 2.5 to 5 nm are deposited using a sputtering method, and then the thickness is reduced using, for example, a plasma CVD method. A 200 nm SiN film 19 is formed, and then patterned to form a gate electrode 20.
The layer thickness of the W layer 18 may be an arbitrary layer thickness, but is determined so that the characteristics of the transistor affected by the sheet resistance satisfy design requirements, and is usually 40 to 60 nm, for example, 40 nm. I do.
In the step of depositing the SiN film 19 or the above-described annealing step after the ion implantation, the B-doped amorphous silicon layer 15 is converted into a B-doped polycrystalline silicon layer 21.
[0023]
At this time, the layer thickness d _WN [nm] of the WN layer 17 is smaller than the layer thickness d _WSi [nm] of the WSi layer 16 as described later.
d _WSi ≦ (1.25d _WN ) ^1/2
Is set so as to satisfy the relationship.
That is, when the layer thickness d _WSi of the WSi layer 16 is 2.5 nm, the layer thickness d _WN of the WN layer 17 is 5 nm or more, and when the layer thickness d _WSi of the WSi layer 16 is 5 nm, the WN layer 17 is formed. Has a layer thickness d _WN of 20 nm or more.
[0024]
Next, as shown in FIG. 2 (c), B ions are implanted, and the implanted B ions are activated by performing a heat treatment at 950 ° C. for 30 to 120 seconds in a N ₂ atmosphere using a rapid thermal anneal (RTA) method. To form the p-type source / drain regions 22 and recover the implantation damage, thereby completing the basic configuration of the p-channel FET having the gate electrode 20 of the polymetal structure.
[0025]
The reason for setting the relationship between the thickness of the WSi layer 16 and the thickness of the WN layer 17 as described above is to ensure that the maximum temperature used in the process can be tolerated. This is an activation annealing step for the drain region. In this annealing step, the thickness of each layer is set so that the B-doped polycrystalline silicon layer 21 and the W layer 18 constituting the gate electrode 20 do not react with each other.
[0026]
The relationship between the layer thicknesses will be described with reference to FIG.
FIG. 3 shows that the B-doped polycrystalline silicon layer 21 and the W layer 18 are separated by annealing at 950 ° C., 975 ° C., 1000 ° C., and 1025 ° C. for 120 seconds in an N ₂ atmosphere using the RTA method. FIG. 3 is a diagram showing a temperature boundary where no reaction occurs, and shows a layer thickness ratio at which no reaction was observed at the interface of the W layer 18 by observation with a transmission microscope. In this case, a certain amount of annealing time is required, but solid-phase diffusion is effectively regulated by the annealing temperature.
[0027]
Generally, activation of impurities such as boron, phosphorus, arsenic, antimony and the like forming the source / drain regions and recovery of defects require a temperature of 950 ° C. or higher. By setting the relationship between the thicknesses of the WSi layer 16 and the WN layer 17 so as to form a region, a 950 ° C. process can be guaranteed.
[0028]
When the correlation curve at 975 ° C. in FIG. 3 is approximated, assuming that the thickness of the WSi layer 16 is d _WSi [nm] and the thickness of the WN layer 17 is d _WN [nm],
d _WSi ≒ (1.25d _WN ) ^1/2
Can be approximated by
d _WSi ≦ (1.25d _WN ) ^1/2
May be set so as to satisfy the relationship.
[0029]
By setting such a relation of the layer thickness, it is possible to suppress an increase in contact resistance due to the formation of a BN bond due to the provision of the WSi layer 16 and to reduce the heat resistance due to the provision of the WSi layer 16. Can be suppressed.
[0030]
Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible.
For example, in the above embodiment, W is used as the refractory metal constituting the polymetal gate electrode. However, it is not always necessary to use W, and Ti, Ta, Mo, Nb, TiN, TaN, or NbN may be used.
[0031]
Further, in the above embodiment, the case where the p-channel FET is formed in the n-type well region using the semiconductor substrate as the p-type silicon substrate has been described, but the p-channel FET is directly formed on the n-type silicon substrate. It is needless to say that the same applies to the case of forming the n-channel FET in the p-type well region or the p-type silicon substrate.
[0032]
Further, in the above embodiment, a silicon semiconductor device is described. However, the present invention is not limited to a silicon semiconductor device, and a semiconductor containing at least Si as a main component, such as a SiGe semiconductor device in which diffusion of Si is a problem. It is also applied to the device.
[0033]
Further, in the above embodiment, the heat treatment step for activating the implanted ions is performed by the RTA method. However, the heat treatment step is not limited to the RTA method. It is.
[0034]
【The invention's effect】
According to the present invention, the relationship between the thickness of the WSi layer and the thickness of the WN layer in the polymetal gate electrode having the polycrystalline Si / WSi / WN / high melting point metal structure is set so as to ensure a process of at least 950 ° C. Therefore, a polymetal gate electrode having low interface contact resistance and being thermally stable can be realized, which greatly contributes to high integration and high speed of a semiconductor integrated circuit device such as a DRAM.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process of the polymetal gate FET according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram of a layer thickness dependence of a reaction temperature between a polycrystalline Si layer and a W layer in a polymetal gate structure.
FIG. 4 is an explanatory diagram of a manufacturing process of a conventional polymetal gate FET.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate containing Si as a main component 2 Gate insulating film 3 Source / drain region 4 Gate electrode 5 Polycrystalline Si layer 6 WSi layer 7 WN layer 8 Refractory metal layer 11 P-type silicon substrate 12 Element isolation insulating film 13 n-type Well region 14 gate oxide film 15 B-doped amorphous silicon layer 16 WSi layer 17 WN layer 18 W layer 19 SiN film 20 gate electrode 21 B-doped polycrystalline silicon layer 22 p-type source / drain electrode 31 p-type silicon substrate 32 element isolation insulation Film 33 n-type well region 34 gate insulating film 35 B-doped polycrystalline silicon layer 36 WN layer 37 W layer 38 SiN film 39 gate electrode 40 p-type source / drain electrode

Claims (5)

In a field-effect semiconductor device comprising a semiconductor containing at least Si as a main component and having a gate electrode having a Si / WSi / WN / high melting point metal structure from the gate insulating film side, the thickness of the WSi layer is d _WSi [nm]. When the thickness of the WN layer is d _WN [nm],
d _WSi ≦ (1.25d _WN ) ^1/2
A field-effect-type semiconductor device characterized by satisfying the following relationship: 2. The field effect type semiconductor device according to claim 1, wherein the layer thickness d _{WSi of the} WSi layer is 2.5 nm to 5 nm. 3. The field effect semiconductor device according to claim 1, wherein the WN layer is at least partially converted to WSiN. When sequentially depositing the Si / WSi / WN / high melting point metal structure from the gate insulating film side, the layer thickness ratio of the WSi layer thickness d _WSi to the WN layer thickness d _WN is determined by determining the layer thickness ratio after the gate electrode is formed. At a maximum operating temperature used in the step (b), a ratio is set so that Si constituting the Si layer does not effectively diffuse into the refractory metal layer. The maximum use temperature is 975 ° C. or lower, and the layer thickness d _WSi [nm] of the WSi layer and the layer thickness d _WN [nm] of the _WN are:
d _WSi ≦ (1.25d _WN ) ^1/2
5. The method according to claim 4, wherein the following relationship is satisfied.

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