JPH02244726A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high speed transistor having a small effective element area, a short base running distance of carrier, small parasitic capacity between a base and a collector and a small base outer resistance by interposing an insulating layer between a first semiconductor and an electrode lead of second semiconductor. CONSTITUTION:An insulating layer 104 is interposed between a collector 101 and a base lead (an inverted L-shaped horizontal part), thereby largely reducing a parasitic capacity formed by the collector and the base lead. An effective element area is provided by the product tXl of a film thickness (t) and the width l of an element. Since an emitter 103 is formed of a thin film, an effective element area can be reduced by decreasing the thickness (t). As an alternative, an emitter 101 and a collector 103 may be formed instead.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device formed on a semiconductor substrate and having excellent high-speed performance.

[Prior art] In order to operate a bipolar transistor at high speed, it is necessary to reduce the size of parasitic elements generated from the structure of the transistor.
It is necessary to make the base layer thin.

In order to meet this requirement, a device in which a horizontal npn structure is formed as shown in FIG. 4 (α) has been developed.

However, in conventionally manufactured lateral bipolar transistors, the base layer is formed by thermal diffusion of impurities or ion implantation, so the base width is 1 μm or more, which significantly deteriorates the current amplification factor and high frequency characteristics. There was a drawback that it could be stored away. Therefore, a method was proposed in which layers are formed layer by layer on an insulating substrate, as shown in FIG. 4(b). (Unexamined Japanese Patent Publication No. 62-15575.9> However, in this structure, the base electrode contact part (upper surface) is made large and the external resistance of the paste is made small. This increases the parasitic capacitance formed by the reflector, which actually reduces the operating speed of the transistor.

Furthermore, when forming on an insulating substrate, it is difficult to form a clean single crystal (fewer traps, high mobility), and it is extremely difficult to fabricate a high-performance transistor (high speed and high current amplification). Have difficulty.

[Problems to be Solved by the Invention] However, if the base extension portion is formed on the collector (or emitter), the collector (or emitter)-base junction capacitance increases, which impedes high-speed operation of the transistor. In addition, in order to reduce the collector (or emitter)-base junction capacitance, the base lead-out portion may be shortened (then the contact with the base electrode (or wiring) cannot be made sufficiently large, and the external resistance of the base becomes large. This impedes high-speed operation of the transistor.

[Means for Solving the Problems] A semiconductor device of the present invention includes: (1) a first semiconductor region having a first conductivity type existing in a semiconductor substrate; and a second conductivity region having a junction with the first semiconductor region. In the second semiconductor having a mold, an insulating layer is sandwiched between the first semiconductor and an electrode extension portion formed by the second semiconductor.

(2) In claim 1, the first semiconductor region is present in or on a semiconductor layer.

[Example] The present invention will be explained below according to the examples.

FIG. 1 is a conceptual diagram (vertical sectional view) of a semiconductor device of the present invention. 101 is a collector made of a semiconductor substrate, 102 is a base and a base extension part, 106 is an emitter, and 104 and 105 are insulating layers.

By sandwiching the insulating layer 104 between the collector 101 and the base extension (horizontal part of an inverted character), the parasitic capacitance generated by the collector and base extension can be significantly reduced. Conventionally, it was not possible to make the base electrode contact surface 106 (upper surface of the base lead-out part) thicker due to the increased parasitic capacitance, but by sandwiching the insulating layer 105, the base electrode contact surface 1 can be made thicker than before.
06 can be made thicker. Also, the effective element area is given by the product t By reducing t, the effective element area can be reduced.

Further, 101 may be an emitter and 103 may be a collector.

FIG. 2 shows an example in which a lateral npn type bipolar transistor was fabricated on an n type single crystal 81 substrate. By performing reactive ion etching on the n-type single crystal 81 substrate 201, an emitter formation area is cleared and steps are formed.

Next, by vertically implanting 02- ions from the substrate surface under DO bias, the parts other than the sidewalls KSi
An insulating film 204 of O, is formed. (Figure 2(a))
Next, after forming 500 p-type single crystals S1 on MJ3 using a photo-etching process, an inverted-shaped base (vertical portion) and a base extension portion (horizontal portion) are formed.

Next, after forming a 5in2 insulating film 205 using a low pressure QVD method, a photo-etching process is performed so that it remains above the base lead-out part but not on the base electrode surface. A polycrystalline S1 film is formed by a low pressure OVD method. (Figure 2(b)) Next, an n-type polycrystalline S1 film is
A photo-etching process is performed so that the emitter 203 does not remain above the base lead-out portion but remains on the base electrode surface to form the emitter 203. Furthermore, the 5in2 membrane was heated under reduced pressure OV'
It is formed by the D method, and windows for the collector, base, and emitter electrodes are opened by a photo-etching process.

(FIG. 2(C)) FIG. 3 is a completed diagram in which collector, base, and emitter electrodes are formed in the embodiment of FIG. 2.

FIG. 3(α) is a view seen from above the substrate, and FIG. 3(h) is a longitudinal sectional view taken along the AA' plane of FIG. 3(α).

Here, the base layer is formed of single crystal silicon using the MBE method, but non-single crystal silicon may also be used.
Other possible forming methods include a reduced pressure (or normal pressure) OVD method, a plasma OVD method, and a sputtering method. Furthermore, various materials and forming methods for the emitter layer can be used, similar to those for the base layer described above.

Before forming a bond, it is desirable to remove oxides and organic substances from the bond interface using diluted hydrofluoric acid. If impurities remain at the interface, interface states will be formed and the electrical potential of the bond will be reduced. Characteristics deteriorate.

The thickness of the p-type single crystal S1 serving as the base layer is 10 to 10 mm.
oooX may be used, and is determined according to the characteristics required for the semiconductor device (high speed, voltage resistance, etc.).

By using the present invention, a high-speed bipolar transistor can be formed in an n-type semiconductor layer formed on a substrate or an insulating layer. The same applies when forming using an n-type semiconductor region in and on a p-type semiconductor layer.

Although embodiments have been described above regarding bipolar transistors made of silicon, elemental semiconductors such as germanium and selenium, and compound semiconductors such as gallium arsenide, cadmium selenium, and indium phosphide may also be used. In addition, the emitter, base, and collector are all made of semiconductors with the same bandgap.

The present invention can also be used in cases other than the above.

In particular, in a heterojunction transistor with a wide-gap emitter, the impurity concentration of the base can be set higher than usual, so the resistance of the base and the lead-out part can be made low, and the base electrode contact part can be made thick ( This is particularly preferred in the present invention.

FIG. 4 shows an example in which a double heterostructure EOL circuit was fabricated using the present invention. It consists of four double heterostructure bipolar transistors using the same wide-gap material for the emitter and collector. In FIG. 4, 401 and 402 are collectors, 403 is an emitter, and 404 to 407 are bases.

In addition, bipolar transistors using the present invention and 0MO
By combining three circuits, high performance can be achieved with 10MO8
It is also possible to create circuits.

The semiconductor device of the present invention can also be applied to a circuit integrated with an LED, a semiconductor laser, a phototransistor, etc. on the same substrate. Of course, integration in the direction perpendicular to the substrate is also possible.

Since the semiconductor device of the present invention has a structure having a junction between a single crystal semiconductor (semiconductor substrate) and a base layer, plasma OV
A non-single-crystal semiconductor thin film formed by the D method can be made into a single crystal (or made into a large-grain polycrystal) by solid-phase growth using a thin crystal semiconductor (semiconductor substrate) as a seed.

Using this method, it is easy to form a transistor with excellent characteristics (high base mobility or few defects) over a large area.

As a method for forming the non-single crystal film, in addition to the plasma OVD method, a sputtering method, a low pressure OVD method, etc. can be used.

[Effects of the Invention] As described above, according to the present invention, in a bipolar transistor, the effective element area is small (and the carrier base traveling distance is short, and the parasitic effect between the base and collector (or base emitter) is small). It is possible to realize a high-speed transistor with a small capacitance and a low base external resistance.Also, it is easy to control the effective element area by controlling the film thickness.In the present invention, since it can be formed on a semiconductor substrate, carrier mobility can be reduced. It is possible to easily form large, high-performance transistors.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram (longitudinal sectional view) of the present invention. Figures 2 (oL), (b), and (C) are process cross-sectional views showing an embodiment of an npn type transistor using the present invention. Figure 3 (α)
(b) is a plan view and a cross-sectional view of a completed npn type transistor of the present invention. FIG. 4 is a diagram showing an embodiment of a FiOL circuit using the present invention. FIGS. 5(α) and 5(b) are diagrams showing a conventional example. 101.201... Collector (semiconductor substrate) 1
02.202...Base and base drawer part I
O3, 203, 403...Emitter 104,
, 105... Insulating layer 106... Base electrode contact surface 204, 205... Insulating film (
Insulating layer) 206...Collector electrode 207...Base electrode 208...Emitter electrode 401.402...Collector 404-407...Base 501.504...Collector 502.505...Base 503,,506...Emitter and above Applicant Seiko Epson Corporation Agent Patent attorney Kizobe Suzuki (1 other person) ) Figure 2↓ (a) Figure 3 (b) Figure 3 Figure 4 (a) Figure 5

Claims (2)

[Claims] (1) In a first semiconductor region having a first conductivity type existing in a semiconductor substrate and a second semiconductor having a second conductivity type having a junction with the first semiconductor region, the first semiconductor region; A semiconductor device characterized in that an insulating layer is sandwiched between the electrode extension portion made of the second semiconductor. (2) The semiconductor device according to claim 1, wherein the first semiconductor region is present in or on a semiconductor layer.