JP2686827B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a heterojunction bipolar transistor (HBT).
And a junction type field effect transistor (J-FET).

[Conventional technology]

With the progress of compound semiconductor technology, HBT and J-FET are often used in combination in a single electronic circuit. Conventionally, the HBT and the J-FET were separately formed on the substrate and interconnected by wiring.

[Problems to be solved by the invention]

However, if the elements are separately formed in this way, the process is remarkably complicated and diversified, and the degree of freedom in circuit design is reduced. Further, the pattern occupying area in the semiconductor substrate tends to be large, which is not suitable for high integration. In this regard, for example, JP-A-64-3
In 9073 etc., MESFET and Schottky diode are Ga
Techniques for integration on As substrates are shown. But HBT
No such attempt has been made for the combination of J-FET and.

The present invention aims to solve the drawbacks of the prior art.

[Means for solving the problem]

A semiconductor device according to the present invention is formed by growing a plurality of different types of semiconductor crystal layers on a semiconductor substrate, HBT having a lower semiconductor crystal layer as a base layer and an upper semiconductor crystal layer as an emitter layer, Formed on the same semiconductor substrate,
The semiconductor crystal layer used as the base layer of the HBT serves as a gate layer, and the J-FET having the semiconductor crystal layer used as the emitter layer of the HBT serves as a channel layer.

Here, at least three semiconductor crystal layers may be grown on the substrate, and the uppermost layer may form the emitter cap layer of HBT and the source and drain layers of J-FET.

[Action]

According to the present invention, the lower semiconductor crystal layer formed on the semiconductor substrate serves as the base of the HBT and the gate of the J-FET, and the upper semiconductor crystal layer is the emitter of the HBT and the J-F.
Acts as an ET channel.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment. As shown in the figure, on the semiconductor substrate 1 made of n-type GaAs, the first, second and third semiconductor crystal layers 2, 3, made of p-type GaAs, n-type GaAlAs and n-type GaAs are arranged from the bottom side, respectively. 4 is epitaxially grown. The HBT region and the J-FET region are separated by forming a groove 6 reaching the semiconductor substrate 1 by etching, and a collector electrode 5C is formed in ohmic contact with the back surface of the semiconductor substrate 1 in the HBT region.

A part of the first semiconductor crystal layer 2 is exposed in the HBT region, and a base electrode 5B is formed on this upper surface in ohmic contact. The surface of the first semiconductor crystal layer 2 is a J-FET
It is also exposed in the region, and the gate electrode 5G is formed here in ohmic contact. The second semiconductor crystal layer 3
It becomes an emitter layer in the HBT region, the third semiconductor crystal layer 4 on this becomes the emitter cap layer, and the emitter electrode 5E is formed on this in ohmic contact. The second semiconductor crystal layer 3 serves as a channel layer in the J-FET region, and the third semiconductor crystal layer 4 on the second semiconductor crystal layer 3 is divided into two, one serving as a source layer and the other serving as a drain layer. The electrode 5S and the drain electrode 5D are formed in ohmic contact.

 The semiconductor device of FIG. 1 is manufactured as follows.

First, a substrate 1 made of n-type GaAs is prepared, the surface is polished, and a p-type GaAs crystal layer 2, an n-type GaAlAs crystal layer 3 and an n-type GaAs crystal layer 4 are sequentially formed by an epitaxial growth method. . Next, a resist pattern is formed by using a photolithography technique, and a part of the n-type GaAs layer 4 and the n-type GaAlAs layer 3 is removed in the channel region of the J-FET. Next, another resist pattern is formed to form the base electrode region of the HBT, the gate electrode region of the J-FET and the J-FET.
In the isolation region between the HBTs, the n-type GaAs layer 4 and the n-type GaAlAs layer 3 are removed and the p-type GaAs layer 2 is exposed. Next, another resist pattern is formed and the HBT
And the J-FET, a part of the p-type GaAs layer 2 and the n-type GaAs substrate 1 is removed, and a groove 6 for isolation is formed.
After that, the ohmic electrodes 5D, 5S, 5G, 5E, 5 are formed by the lift-off method.
By forming B and 5C, the device structure shown in FIG. 1 is completed.

According to the above configuration, the load device and the pre-driver can be incorporated.

FIG. 2 is a circuit configuration diagram thereof. In the figure (a), J-
It shows a state where a load composed of a FET is built in an inverter circuit having an HBT. Further, FIG. 3B shows a drive circuit incorporating a J-FET for driving the HBT. It goes without saying that the present invention can be used not only in these circuits but also in various circuits.

The present invention is not limited to the embodiments, and various modifications can be made.

For example, the compound semiconductor material is not limited to GaAs and GaAlAs, but various materials such as InP may be used. Alternatively, the semiconductor substrate may be a semi-insulating substrate, and another semiconductor crystal layer may be formed between the semiconductor substrate and the first semiconductor crystal layer 2. In this case, the semiconductor crystal layer becomes the HBT collector layer, and the collector electrode 5C is formed on this semiconductor crystal layer.

〔The invention's effect〕

As described above in detail, in the present invention, the lower semiconductor crystal layer formed on the semiconductor substrate is the base of HBT and J
Acting as the gate of the FET, the upper semiconductor crystal layer acting as the emitter of the HBT and the channel of the J-FET. Therefore, the degree of freedom in circuit design can be significantly improved in the semiconductor device in which both the HBT and the J-FET are integrated. Further, since the manufacturing process can be simplified and the wiring can be reduced, there is an effect that the manufacturing yield can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a block diagram of a circuit to which the embodiment is applied. 1 ... semiconductor substrate, 2 ... first semiconductor crystal layer, 3 ...
Second semiconductor crystal layer, 4 ... Third semiconductor crystal layer, 5B ...
… Base electrode, 5E …… Emitter electrode, 5C …… Collector electrode, 5D …… Drain electrode, 5G …… Gate electrode, 6 ……
groove.

Claims (2)

(57) [Claims] 1. A heterojunction bipolar transistor formed by growing a plurality of different semiconductor crystal layers on a semiconductor substrate, wherein the lower semiconductor crystal layer is a base layer and the upper semiconductor crystal layer is an emitter layer. And a junction-type field effect transistor formed on the semiconductor substrate and using the semiconductor crystal layer used as the base layer as a gate layer and the semiconductor crystal layer used as the emitter layer as a channel layer. A semiconductor device characterized by the above. 2. The semiconductor crystal layer is grown in at least three layers, and the uppermost layer forms the emitter cap layer of the heterojunction bipolar transistor and the source and drain layers of the junction field effect transistor. The semiconductor device according to claim 1.